target/linux/s3c24xx/patches/0237-fix-glamo-turbo-host-interface.patch.patch

   1 From 27d53aa3a33766bb3882f1adcf73c0b3402a5572 Mon Sep 17 00:00:00 2001
   2 From: Andy Green <andy@openmoko.com>
   3 Date: Mon, 4 Aug 2008 08:34:51 +0100
   4 Subject: [PATCH] fix-glamo-turbo-host-interface.patch
   5
   6 Signed-off-by: Andy Green <andy@openmoko.com>
   7 ---
   8  arch/arm/mach-s3c2440/mach-gta02.c |    4 ++++
   9  drivers/mfd/glamo/glamo-core.c     |   12 ++++++------
  10  2 files changed, 10 insertions(+), 6 deletions(-)
  11
  12 diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
  13 index 8e43c4a..be2d901 100644
  14 --- a/arch/arm/mach-s3c2440/mach-gta02.c
  15 +++ b/arch/arm/mach-s3c2440/mach-gta02.c
  16 @@ -66,6 +66,7 @@
  17  #include <asm/arch/spi.h>
  18  #include <asm/arch/spi-gpio.h>
  19  #include <asm/arch/usb-control.h>
  20 +#include <asm/arch/regs-mem.h>
  21
  22  #include <asm/arch/gta02.h>
  23
  24 @@ -1562,6 +1563,9 @@ static void __init gta02_machine_init(void)
  25
  26         spin_lock_init(&motion_irq_lock);
  27
  28 +       /* Glamo chip select optimization */
  29 +/*      *((u32 *)(S3C2410_MEMREG(((1 + 1) << 2)))) = 0x1280; */
  30 +
  31         s3c_device_usb.dev.platform_data = &gta02_usb_info;
  32         s3c_device_nand.dev.platform_data = &gta02_nand_info;
  33         s3c_device_sdi.dev.platform_data = &gta02_mmc_cfg;
  34 diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c
  35 index 0e7a650..92dbd65 100644
  36 --- a/drivers/mfd/glamo/glamo-core.c
  37 +++ b/drivers/mfd/glamo/glamo-core.c
  38 @@ -740,18 +740,18 @@ static struct glamo_script glamo_init_script[] = {
  39         { GLAMO_REG_CLOCK_GEN7,         0x0101 },
  40         { GLAMO_REG_CLOCK_GEN8,         0x0100 },
  41         { GLAMO_REG_CLOCK_HOST,         0x000d },
  42 -       { 0x200,        0x0ef0 },
  43 +       /*
  44 +        * b7..b4 = 0 = no wait states on read or write
  45 +        * b0 = 1 select PLL2 for Host interface, b1 = enable it
  46 +        */
  47 +       { 0x200,        0x0e03 },
  48         { 0x202,        0x07ff },
  49         { 0x212,        0x0000 },
  50         { 0x214,        0x4000 },
  51         { 0x216,        0xf00e },
  52         { GLAMO_REG_MEM_TYPE,           0x0874 }, /* 8MB, 16 word pg wr+rd */
  53         { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
  54 -       /*
  55 -        * the register below originally 0x0108 makes unreliable Glamo MMC
  56 -        * write operations.  Cranked to 0x05ad to add a wait state, the
  57 -        * unreliability is not seen after 4GB of write / read testing
  58 -        */
  59 +
  60         { GLAMO_REG_MEM_TIMING1,        0x0108 },
  61         { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
  62         { GLAMO_REG_MEM_TIMING3,        0x0000 },
  63 --
  64 1.5.6.3
  65