target/linux/ramips/patches-4.4/0047-DMA-ralink-add-rt2880-dma-engine.patch

   1 From f1c4d9e622c800e1f38b3818f933ec7597d1ccfb Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:29:51 +0100
   4 Subject: [PATCH 47/53] DMA: ralink: add rt2880 dma engine
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/dma/Kconfig       |    6 +
   9  drivers/dma/Makefile      |    1 +
  10  drivers/dma/ralink-gdma.c |  577 +++++++++++++++++++++++++++++++++++++++++++++
  11  include/linux/dmaengine.h |    1 +
  12  4 files changed, 585 insertions(+)
  13  create mode 100644 drivers/dma/ralink-gdma.c
  14
  15 --- a/drivers/dma/Kconfig
  16 +++ b/drivers/dma/Kconfig
  17 @@ -40,6 +40,12 @@ config ASYNC_TX_ENABLE_CHANNEL_SWITCH
  18  config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  19         bool
  20
  21 +config DMA_RALINK
  22 +       tristate "RALINK DMA support"
  23 +       depends on RALINK && SOC_MT7620
  24 +       select DMA_ENGINE
  25 +       select DMA_VIRTUAL_CHANNELS
  26 +
  27  config DMA_ENGINE
  28         bool
  29
  30 --- a/drivers/dma/Makefile
  31 +++ b/drivers/dma/Makefile
  32 @@ -65,5 +65,6 @@ obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-
  33  obj-$(CONFIG_TI_EDMA) += edma.o
  34  obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
  35  obj-$(CONFIG_ZX_DMA) += zx296702_dma.o
  36 +obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
  37
  38  obj-y += xilinx/
  39 --- /dev/null
  40 +++ b/drivers/dma/ralink-gdma.c
  41 @@ -0,0 +1,577 @@
  42 +/*
  43 + *  Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
  44 + *  GDMA4740 DMAC support
  45 + *
  46 + *  This program is free software; you can redistribute it and/or modify it
  47 + *  under  the terms of the GNU General         Public License as published by the
  48 + *  Free Software Foundation;  either version 2 of the License, or (at your
  49 + *  option) any later version.
  50 + *
  51 + *  You should have received a copy of the GNU General Public License along
  52 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  53 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  54 + *
  55 + */
  56 +
  57 +#include <linux/dmaengine.h>
  58 +#include <linux/dma-mapping.h>
  59 +#include <linux/err.h>
  60 +#include <linux/init.h>
  61 +#include <linux/list.h>
  62 +#include <linux/module.h>
  63 +#include <linux/platform_device.h>
  64 +#include <linux/slab.h>
  65 +#include <linux/spinlock.h>
  66 +#include <linux/irq.h>
  67 +#include <linux/of_dma.h>
  68 +
  69 +#include "virt-dma.h"
  70 +
  71 +#define GDMA_NR_CHANS                  16
  72 +
  73 +#define GDMA_REG_SRC_ADDR(x)           (0x00 + (x) * 0x10)
  74 +#define GDMA_REG_DST_ADDR(x)           (0x04 + (x) * 0x10)
  75 +
  76 +#define GDMA_REG_CTRL0(x)              (0x08 + (x) * 0x10)
  77 +#define GDMA_REG_CTRL0_TX_MASK         0xffff
  78 +#define GDMA_REG_CTRL0_TX_SHIFT                16
  79 +#define GDMA_REG_CTRL0_CURR_MASK       0xff
  80 +#define GDMA_REG_CTRL0_CURR_SHIFT      8
  81 +#define        GDMA_REG_CTRL0_SRC_ADDR_FIXED   BIT(7)
  82 +#define GDMA_REG_CTRL0_DST_ADDR_FIXED  BIT(6)
  83 +#define GDMA_REG_CTRL0_BURST_MASK      0x7
  84 +#define GDMA_REG_CTRL0_BURST_SHIFT     3
  85 +#define        GDMA_REG_CTRL0_DONE_INT         BIT(2)
  86 +#define        GDMA_REG_CTRL0_ENABLE           BIT(1)
  87 +#define        GDMA_REG_CTRL0_HW_MODE          0
  88 +
  89 +#define GDMA_REG_CTRL1(x)              (0x0c + (x) * 0x10)
  90 +#define GDMA_REG_CTRL1_SEG_MASK                0xf
  91 +#define GDMA_REG_CTRL1_SEG_SHIFT       22
  92 +#define GDMA_REG_CTRL1_REQ_MASK                0x3f
  93 +#define GDMA_REG_CTRL1_SRC_REQ_SHIFT   16
  94 +#define GDMA_REG_CTRL1_DST_REQ_SHIFT   8
  95 +#define GDMA_REG_CTRL1_CONTINOUS       BIT(14)
  96 +#define GDMA_REG_CTRL1_NEXT_MASK       0x1f
  97 +#define GDMA_REG_CTRL1_NEXT_SHIFT      3
  98 +#define GDMA_REG_CTRL1_COHERENT                BIT(2)
  99 +#define GDMA_REG_CTRL1_FAIL            BIT(1)
 100 +#define GDMA_REG_CTRL1_MASK            BIT(0)
 101 +
 102 +#define GDMA_REG_UNMASK_INT            0x200
 103 +#define GDMA_REG_DONE_INT              0x204
 104 +
 105 +#define GDMA_REG_GCT                   0x220
 106 +#define GDMA_REG_GCT_CHAN_MASK         0x3
 107 +#define GDMA_REG_GCT_CHAN_SHIFT                3
 108 +#define GDMA_REG_GCT_VER_MASK          0x3
 109 +#define GDMA_REG_GCT_VER_SHIFT         1
 110 +#define GDMA_REG_GCT_ARBIT_RR          BIT(0)
 111 +
 112 +enum gdma_dma_transfer_size {
 113 +       GDMA_TRANSFER_SIZE_4BYTE        = 0,
 114 +       GDMA_TRANSFER_SIZE_8BYTE        = 1,
 115 +       GDMA_TRANSFER_SIZE_16BYTE       = 2,
 116 +       GDMA_TRANSFER_SIZE_32BYTE       = 3,
 117 +};
 118 +
 119 +struct gdma_dma_sg {
 120 +       dma_addr_t addr;
 121 +       unsigned int len;
 122 +};
 123 +
 124 +struct gdma_dma_desc {
 125 +       struct virt_dma_desc vdesc;
 126 +
 127 +       enum dma_transfer_direction direction;
 128 +       bool cyclic;
 129 +
 130 +       unsigned int num_sgs;
 131 +       struct gdma_dma_sg sg[];
 132 +};
 133 +
 134 +struct gdma_dmaengine_chan {
 135 +       struct virt_dma_chan vchan;
 136 +       unsigned int id;
 137 +
 138 +       dma_addr_t fifo_addr;
 139 +       unsigned int transfer_shift;
 140 +
 141 +       struct gdma_dma_desc *desc;
 142 +       unsigned int next_sg;
 143 +};
 144 +
 145 +struct gdma_dma_dev {
 146 +       struct dma_device ddev;
 147 +       void __iomem *base;
 148 +       struct clk *clk;
 149 +
 150 +       struct gdma_dmaengine_chan chan[GDMA_NR_CHANS];
 151 +};
 152 +
 153 +static struct gdma_dma_dev *gdma_dma_chan_get_dev(
 154 +       struct gdma_dmaengine_chan *chan)
 155 +{
 156 +       return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
 157 +               ddev);
 158 +}
 159 +
 160 +static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
 161 +{
 162 +       return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
 163 +}
 164 +
 165 +static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
 166 +{
 167 +       return container_of(vdesc, struct gdma_dma_desc, vdesc);
 168 +}
 169 +
 170 +static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
 171 +       unsigned int reg)
 172 +{
 173 +       return readl(dma_dev->base + reg);
 174 +}
 175 +
 176 +static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
 177 +       unsigned reg, uint32_t val)
 178 +{
 179 +       //printk("gdma --> %p = 0x%08X\n", dma_dev->base + reg, val);
 180 +       writel(val, dma_dev->base + reg);
 181 +}
 182 +
 183 +static inline void gdma_dma_write_mask(struct gdma_dma_dev *dma_dev,
 184 +       unsigned int reg, uint32_t val, uint32_t mask)
 185 +{
 186 +       uint32_t tmp;
 187 +
 188 +       tmp = gdma_dma_read(dma_dev, reg);
 189 +       tmp &= ~mask;
 190 +       tmp |= val;
 191 +       gdma_dma_write(dma_dev, reg, tmp);
 192 +}
 193 +
 194 +static struct gdma_dma_desc *gdma_dma_alloc_desc(unsigned int num_sgs)
 195 +{
 196 +       return kzalloc(sizeof(struct gdma_dma_desc) +
 197 +               sizeof(struct gdma_dma_sg) * num_sgs, GFP_ATOMIC);
 198 +}
 199 +
 200 +static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
 201 +{
 202 +       if (maxburst <= 7)
 203 +               return GDMA_TRANSFER_SIZE_4BYTE;
 204 +       else if (maxburst <= 15)
 205 +               return GDMA_TRANSFER_SIZE_8BYTE;
 206 +       else if (maxburst <= 31)
 207 +               return GDMA_TRANSFER_SIZE_16BYTE;
 208 +
 209 +       return GDMA_TRANSFER_SIZE_32BYTE;
 210 +}
 211 +
 212 +static int gdma_dma_slave_config(struct dma_chan *c,
 213 +       const struct dma_slave_config *config)
 214 +{
 215 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 216 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 217 +       enum gdma_dma_transfer_size transfer_size;
 218 +       uint32_t flags;
 219 +       uint32_t ctrl0, ctrl1;
 220 +
 221 +       switch (config->direction) {
 222 +       case DMA_MEM_TO_DEV:
 223 +               ctrl1 = 32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
 224 +               ctrl1 |= config->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT;
 225 +               flags = GDMA_REG_CTRL0_DST_ADDR_FIXED;
 226 +               transfer_size = gdma_dma_maxburst(config->dst_maxburst);
 227 +               chan->fifo_addr = config->dst_addr;
 228 +               break;
 229 +
 230 +       case DMA_DEV_TO_MEM:
 231 +               ctrl1 = config->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
 232 +               ctrl1 |= 32 << GDMA_REG_CTRL1_DST_REQ_SHIFT;
 233 +               flags = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
 234 +               transfer_size = gdma_dma_maxburst(config->src_maxburst);
 235 +               chan->fifo_addr = config->src_addr;
 236 +               break;
 237 +
 238 +       default:
 239 +               return -EINVAL;
 240 +       }
 241 +
 242 +       chan->transfer_shift = 1 + transfer_size;
 243 +
 244 +       ctrl0 = flags | GDMA_REG_CTRL0_HW_MODE;
 245 +       ctrl0 |= GDMA_REG_CTRL0_DONE_INT;
 246 +
 247 +       ctrl1 &= ~(GDMA_REG_CTRL1_NEXT_MASK << GDMA_REG_CTRL1_NEXT_SHIFT);
 248 +       ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
 249 +       ctrl1 |= GDMA_REG_CTRL1_FAIL;
 250 +       ctrl1 &= ~GDMA_REG_CTRL1_CONTINOUS;
 251 +       gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
 252 +       gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
 253 +
 254 +       return 0;
 255 +}
 256 +
 257 +static int gdma_dma_terminate_all(struct dma_chan *c)
 258 +{
 259 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 260 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 261 +       unsigned long flags;
 262 +       LIST_HEAD(head);
 263 +
 264 +       spin_lock_irqsave(&chan->vchan.lock, flags);
 265 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
 266 +                       GDMA_REG_CTRL0_ENABLE);
 267 +       chan->desc = NULL;
 268 +       vchan_get_all_descriptors(&chan->vchan, &head);
 269 +       spin_unlock_irqrestore(&chan->vchan.lock, flags);
 270 +
 271 +       vchan_dma_desc_free_list(&chan->vchan, &head);
 272 +
 273 +       return 0;
 274 +}
 275 +
 276 +static int gdma_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 277 +       unsigned long arg)
 278 +{
 279 +       struct dma_slave_config *config = (struct dma_slave_config *)arg;
 280 +
 281 +       switch (cmd) {
 282 +       case DMA_SLAVE_CONFIG:
 283 +               return gdma_dma_slave_config(chan, config);
 284 +       case DMA_TERMINATE_ALL:
 285 +               return gdma_dma_terminate_all(chan);
 286 +       default:
 287 +               return -ENOSYS;
 288 +       }
 289 +}
 290 +
 291 +static int gdma_dma_start_transfer(struct gdma_dmaengine_chan *chan)
 292 +{
 293 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 294 +       dma_addr_t src_addr, dst_addr;
 295 +       struct virt_dma_desc *vdesc;
 296 +       struct gdma_dma_sg *sg;
 297 +
 298 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
 299 +                       GDMA_REG_CTRL0_ENABLE);
 300 +
 301 +       if (!chan->desc) {
 302 +               vdesc = vchan_next_desc(&chan->vchan);
 303 +               if (!vdesc)
 304 +                       return 0;
 305 +               chan->desc = to_gdma_dma_desc(vdesc);
 306 +               chan->next_sg = 0;
 307 +       }
 308 +
 309 +       if (chan->next_sg == chan->desc->num_sgs)
 310 +               chan->next_sg = 0;
 311 +
 312 +       sg = &chan->desc->sg[chan->next_sg];
 313 +
 314 +       if (chan->desc->direction == DMA_MEM_TO_DEV) {
 315 +               src_addr = sg->addr;
 316 +               dst_addr = chan->fifo_addr;
 317 +       } else {
 318 +               src_addr = chan->fifo_addr;
 319 +               dst_addr = sg->addr;
 320 +       }
 321 +       gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
 322 +       gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
 323 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id),
 324 +                       (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | GDMA_REG_CTRL0_ENABLE,
 325 +                       GDMA_REG_CTRL0_TX_MASK << GDMA_REG_CTRL0_TX_SHIFT);
 326 +       chan->next_sg++;
 327 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL1(chan->id), 0, GDMA_REG_CTRL1_MASK);
 328 +
 329 +       return 0;
 330 +}
 331 +
 332 +static void gdma_dma_chan_irq(struct gdma_dmaengine_chan *chan)
 333 +{
 334 +       spin_lock(&chan->vchan.lock);
 335 +       if (chan->desc) {
 336 +               if (chan->desc && chan->desc->cyclic) {
 337 +                       vchan_cyclic_callback(&chan->desc->vdesc);
 338 +               } else {
 339 +                       if (chan->next_sg == chan->desc->num_sgs) {
 340 +                               chan->desc = NULL;
 341 +                               vchan_cookie_complete(&chan->desc->vdesc);
 342 +                       }
 343 +               }
 344 +       }
 345 +       gdma_dma_start_transfer(chan);
 346 +       spin_unlock(&chan->vchan.lock);
 347 +}
 348 +
 349 +static irqreturn_t gdma_dma_irq(int irq, void *devid)
 350 +{
 351 +       struct gdma_dma_dev *dma_dev = devid;
 352 +       uint32_t unmask, done;
 353 +       unsigned int i;
 354 +
 355 +       unmask = gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT);
 356 +       gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, unmask);
 357 +       done = gdma_dma_read(dma_dev, GDMA_REG_DONE_INT);
 358 +
 359 +       for (i = 0; i < GDMA_NR_CHANS; ++i)
 360 +               if (done & BIT(i))
 361 +                       gdma_dma_chan_irq(&dma_dev->chan[i]);
 362 +       gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, done);
 363 +
 364 +       return IRQ_HANDLED;
 365 +}
 366 +
 367 +static void gdma_dma_issue_pending(struct dma_chan *c)
 368 +{
 369 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 370 +       unsigned long flags;
 371 +
 372 +       spin_lock_irqsave(&chan->vchan.lock, flags);
 373 +       if (vchan_issue_pending(&chan->vchan) && !chan->desc)
 374 +               gdma_dma_start_transfer(chan);
 375 +       spin_unlock_irqrestore(&chan->vchan.lock, flags);
 376 +}
 377 +
 378 +static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
 379 +       struct dma_chan *c, struct scatterlist *sgl,
 380 +       unsigned int sg_len, enum dma_transfer_direction direction,
 381 +       unsigned long flags, void *context)
 382 +{
 383 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 384 +       struct gdma_dma_desc *desc;
 385 +       struct scatterlist *sg;
 386 +       unsigned int i;
 387 +
 388 +       desc = gdma_dma_alloc_desc(sg_len);
 389 +       if (!desc)
 390 +               return NULL;
 391 +
 392 +       for_each_sg(sgl, sg, sg_len, i) {
 393 +               desc->sg[i].addr = sg_dma_address(sg);
 394 +               desc->sg[i].len = sg_dma_len(sg);
 395 +       }
 396 +
 397 +       desc->num_sgs = sg_len;
 398 +       desc->direction = direction;
 399 +       desc->cyclic = false;
 400 +
 401 +       return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 402 +}
 403 +
 404 +static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
 405 +       struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 406 +       size_t period_len, enum dma_transfer_direction direction,
 407 +       unsigned long flags, void *context)
 408 +{
 409 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 410 +       struct gdma_dma_desc *desc;
 411 +       unsigned int num_periods, i;
 412 +
 413 +       if (buf_len % period_len)
 414 +               return NULL;
 415 +
 416 +       num_periods = buf_len / period_len;
 417 +
 418 +       desc = gdma_dma_alloc_desc(num_periods);
 419 +       if (!desc)
 420 +               return NULL;
 421 +
 422 +       for (i = 0; i < num_periods; i++) {
 423 +               desc->sg[i].addr = buf_addr;
 424 +               desc->sg[i].len = period_len;
 425 +               buf_addr += period_len;
 426 +       }
 427 +
 428 +       desc->num_sgs = num_periods;
 429 +       desc->direction = direction;
 430 +       desc->cyclic = true;
 431 +
 432 +       return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 433 +}
 434 +
 435 +static size_t gdma_dma_desc_residue(struct gdma_dmaengine_chan *chan,
 436 +       struct gdma_dma_desc *desc, unsigned int next_sg)
 437 +{
 438 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 439 +       unsigned int residue, count;
 440 +       unsigned int i;
 441 +
 442 +       residue = 0;
 443 +
 444 +       for (i = next_sg; i < desc->num_sgs; i++)
 445 +               residue += desc->sg[i].len;
 446 +
 447 +       if (next_sg != 0) {
 448 +               count = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
 449 +               count >>= GDMA_REG_CTRL0_CURR_SHIFT;
 450 +               count &= GDMA_REG_CTRL0_CURR_MASK;
 451 +               residue += count << chan->transfer_shift;
 452 +       }
 453 +
 454 +       return residue;
 455 +}
 456 +
 457 +static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
 458 +       dma_cookie_t cookie, struct dma_tx_state *state)
 459 +{
 460 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 461 +       struct virt_dma_desc *vdesc;
 462 +       enum dma_status status;
 463 +       unsigned long flags;
 464 +
 465 +       status = dma_cookie_status(c, cookie, state);
 466 +       if (status == DMA_SUCCESS || !state)
 467 +               return status;
 468 +
 469 +       spin_lock_irqsave(&chan->vchan.lock, flags);
 470 +       vdesc = vchan_find_desc(&chan->vchan, cookie);
 471 +       if (cookie == chan->desc->vdesc.tx.cookie) {
 472 +               state->residue = gdma_dma_desc_residue(chan, chan->desc,
 473 +                               chan->next_sg);
 474 +       } else if (vdesc) {
 475 +               state->residue = gdma_dma_desc_residue(chan,
 476 +                               to_gdma_dma_desc(vdesc), 0);
 477 +       } else {
 478 +               state->residue = 0;
 479 +       }
 480 +       spin_unlock_irqrestore(&chan->vchan.lock, flags);
 481 +
 482 +       return status;
 483 +}
 484 +
 485 +static int gdma_dma_alloc_chan_resources(struct dma_chan *c)
 486 +{
 487 +       return 0;
 488 +}
 489 +
 490 +static void gdma_dma_free_chan_resources(struct dma_chan *c)
 491 +{
 492 +       vchan_free_chan_resources(to_virt_chan(c));
 493 +}
 494 +
 495 +static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
 496 +{
 497 +       kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
 498 +}
 499 +
 500 +static struct dma_chan *
 501 +of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec,
 502 +                       struct of_dma *ofdma)
 503 +{
 504 +       struct gdma_dma_dev *dma_dev = ofdma->of_dma_data;
 505 +       unsigned int request = dma_spec->args[0];
 506 +
 507 +       if (request >= GDMA_NR_CHANS)
 508 +               return NULL;
 509 +
 510 +       return dma_get_slave_channel(&(dma_dev->chan[request].vchan.chan));
 511 +}
 512 +
 513 +static int gdma_dma_probe(struct platform_device *pdev)
 514 +{
 515 +       struct gdma_dmaengine_chan *chan;
 516 +       struct gdma_dma_dev *dma_dev;
 517 +       struct dma_device *dd;
 518 +       unsigned int i;
 519 +       struct resource *res;
 520 +       uint32_t gct;
 521 +       int ret;
 522 +       int irq;
 523 +
 524 +
 525 +       dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
 526 +       if (!dma_dev)
 527 +               return -EINVAL;
 528 +
 529 +       dd = &dma_dev->ddev;
 530 +
 531 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 532 +       dma_dev->base = devm_ioremap_resource(&pdev->dev, res);
 533 +       if (IS_ERR(dma_dev->base))
 534 +               return PTR_ERR(dma_dev->base);
 535 +
 536 +       dma_cap_set(DMA_SLAVE, dd->cap_mask);
 537 +       dma_cap_set(DMA_CYCLIC, dd->cap_mask);
 538 +       dd->device_alloc_chan_resources = gdma_dma_alloc_chan_resources;
 539 +       dd->device_free_chan_resources = gdma_dma_free_chan_resources;
 540 +       dd->device_tx_status = gdma_dma_tx_status;
 541 +       dd->device_issue_pending = gdma_dma_issue_pending;
 542 +       dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
 543 +       dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
 544 +       dd->device_control = gdma_dma_control;
 545 +       dd->dev = &pdev->dev;
 546 +       dd->chancnt = GDMA_NR_CHANS;
 547 +       INIT_LIST_HEAD(&dd->channels);
 548 +
 549 +       for (i = 0; i < dd->chancnt; i++) {
 550 +               chan = &dma_dev->chan[i];
 551 +               chan->id = i;
 552 +               chan->vchan.desc_free = gdma_dma_desc_free;
 553 +               vchan_init(&chan->vchan, dd);
 554 +       }
 555 +
 556 +       ret = dma_async_device_register(dd);
 557 +       if (ret)
 558 +               return ret;
 559 +
 560 +       ret = of_dma_controller_register(pdev->dev.of_node,
 561 +               of_dma_xlate_by_chan_id, dma_dev);
 562 +       if (ret)
 563 +               goto err_unregister;
 564 +
 565 +       irq = platform_get_irq(pdev, 0);
 566 +       ret = request_irq(irq, gdma_dma_irq, 0, dev_name(&pdev->dev), dma_dev);
 567 +       if (ret)
 568 +               goto err_unregister;
 569 +
 570 +       gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, 0);
 571 +       gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, BIT(dd->chancnt) - 1);
 572 +
 573 +       gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
 574 +       dev_info(&pdev->dev, "revision: %d, channels: %d\n",
 575 +               (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
 576 +               8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & GDMA_REG_GCT_CHAN_MASK));
 577 +       platform_set_drvdata(pdev, dma_dev);
 578 +
 579 +       gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
 580 +
 581 +       return 0;
 582 +
 583 +err_unregister:
 584 +       dma_async_device_unregister(dd);
 585 +       return ret;
 586 +}
 587 +
 588 +static int gdma_dma_remove(struct platform_device *pdev)
 589 +{
 590 +       struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
 591 +       int irq = platform_get_irq(pdev, 0);
 592 +
 593 +       free_irq(irq, dma_dev);
 594 +        of_dma_controller_free(pdev->dev.of_node);
 595 +       dma_async_device_unregister(&dma_dev->ddev);
 596 +
 597 +       return 0;
 598 +}
 599 +
 600 +static const struct of_device_id gdma_of_match_table[] = {
 601 +       { .compatible = "ralink,rt2880-gdma" },
 602 +       { },
 603 +};
 604 +
 605 +static struct platform_driver gdma_dma_driver = {
 606 +       .probe = gdma_dma_probe,
 607 +       .remove = gdma_dma_remove,
 608 +       .driver = {
 609 +               .name = "gdma-rt2880",
 610 +               .owner = THIS_MODULE,
 611 +               .of_match_table = gdma_of_match_table,
 612 +       },
 613 +};
 614 +module_platform_driver(gdma_dma_driver);
 615 +
 616 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 617 +MODULE_DESCRIPTION("GDMA4740 DMA driver");
 618 +MODULE_LICENSE("GPLv2");
 619 --- a/include/linux/dmaengine.h
 620 +++ b/include/linux/dmaengine.h
 621 @@ -496,6 +496,7 @@ static inline void dma_set_unmap(struct
 622  struct dmaengine_unmap_data *
 623  dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
 624  void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
 625 +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
 626  #else
 627  static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
 628                                  struct dmaengine_unmap_data *unmap)