target/linux/ramips/patches-4.3/0501-net-next-mediatek-add-the-drivers-core-files.patch

   1 From 2abe91b53ca4d2528ef1fc9c44c6e69f8c805776 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 18 Nov 2015 03:12:19 +0100
   4 Subject: [PATCH 501/513] net-next: mediatek: add the drivers core files
   5
   6 This patch adds the main chunk of the driver. The ethernet core is used in all
   7 of the Mediatek/Ralink Wireless SoCs. Over the years we have seen verious
   8 changes to
   9
  10 * the register layout
  11 * the type of ports (single/dual gbit, internal FE/Gbit switch)
  12 * dma engine
  13
  14 and new offloading features were added, such as
  15
  16 * checksum
  17 * vlan tx/rx
  18 * gso
  19 * lro
  20
  21 However the core functionality has remained the sama allowing us to use the
  22 same core for all SoCs.
  23
  24 The abstraction for the various SoCs uses the typical ops struct pattern which
  25 allows us to extend or override the cores functionality depending on which SoC
  26 we are on. The code to bring up the switches and external ports has also been
  27 split into separate files.
  28
  29 Signed-off-by: John Crispin <blogic@openwrt.org>
  30 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  31 Signed-off-by: Michael Lee <igvtee@gmail.com>
  32 ---
  33  drivers/net/ethernet/mediatek/ethtool.c     |  235 ++++
  34  drivers/net/ethernet/mediatek/ethtool.h     |   22 +
  35  drivers/net/ethernet/mediatek/mdio.c        |  258 +++++
  36  drivers/net/ethernet/mediatek/mdio.h        |   27 +
  37  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1607 +++++++++++++++++++++++++++
  38  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  522 +++++++++
  39  6 files changed, 2671 insertions(+)
  40  create mode 100644 drivers/net/ethernet/mediatek/ethtool.c
  41  create mode 100644 drivers/net/ethernet/mediatek/ethtool.h
  42  create mode 100644 drivers/net/ethernet/mediatek/mdio.c
  43  create mode 100644 drivers/net/ethernet/mediatek/mdio.h
  44  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.c
  45  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.h
  46
  47 --- /dev/null
  48 +++ b/drivers/net/ethernet/mediatek/ethtool.c
  49 @@ -0,0 +1,235 @@
  50 +/*   This program is free software; you can redistribute it and/or modify
  51 + *   it under the terms of the GNU General Public License as published by
  52 + *   the Free Software Foundation; version 2 of the License
  53 + *
  54 + *   This program is distributed in the hope that it will be useful,
  55 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  56 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  57 + *   GNU General Public License for more details.
  58 + *
  59 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  60 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
  61 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  62 + */
  63 +
  64 +#include "mtk_eth_soc.h"
  65 +
  66 +static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
  67 +#define _FE(x...)      # x,
  68 +FE_STAT_REG_DECLARE
  69 +#undef _FE
  70 +};
  71 +
  72 +static int fe_get_settings(struct net_device *dev,
  73 +                          struct ethtool_cmd *cmd)
  74 +{
  75 +       struct fe_priv *priv = netdev_priv(dev);
  76 +       int err;
  77 +
  78 +       if (!priv->phy_dev)
  79 +               goto out_gset;
  80 +
  81 +       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
  82 +               err = phy_read_status(priv->phy_dev);
  83 +               if (err)
  84 +                       goto out_gset;
  85 +       }
  86 +
  87 +       return phy_ethtool_gset(priv->phy_dev, cmd);
  88 +
  89 +out_gset:
  90 +       return -ENODEV;
  91 +}
  92 +
  93 +static int fe_set_settings(struct net_device *dev,
  94 +                          struct ethtool_cmd *cmd)
  95 +{
  96 +       struct fe_priv *priv = netdev_priv(dev);
  97 +
  98 +       if (!priv->phy_dev)
  99 +               goto out_sset;
 100 +
 101 +       if (cmd->phy_address != priv->phy_dev->addr) {
 102 +               if (priv->phy->phy_node[cmd->phy_address]) {
 103 +                       priv->phy_dev = priv->phy->phy[cmd->phy_address];
 104 +                       priv->phy_flags = FE_PHY_FLAG_PORT;
 105 +               } else if (priv->mii_bus &&
 106 +                          priv->mii_bus->phy_map[cmd->phy_address]) {
 107 +                       priv->phy_dev =
 108 +                               priv->mii_bus->phy_map[cmd->phy_address];
 109 +                       priv->phy_flags = FE_PHY_FLAG_ATTACH;
 110 +               } else {
 111 +                       goto out_sset;
 112 +               }
 113 +       }
 114 +
 115 +       return phy_ethtool_sset(priv->phy_dev, cmd);
 116 +
 117 +out_sset:
 118 +       return -ENODEV;
 119 +}
 120 +
 121 +static void fe_get_drvinfo(struct net_device *dev,
 122 +                          struct ethtool_drvinfo *info)
 123 +{
 124 +       struct fe_priv *priv = netdev_priv(dev);
 125 +       struct fe_soc_data *soc = priv->soc;
 126 +
 127 +       strlcpy(info->driver, priv->device->driver->name, sizeof(info->driver));
 128 +       strlcpy(info->version, MTK_FE_DRV_VERSION, sizeof(info->version));
 129 +       strlcpy(info->bus_info, dev_name(priv->device), sizeof(info->bus_info));
 130 +
 131 +       if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
 132 +               info->n_stats = ARRAY_SIZE(fe_gdma_str);
 133 +}
 134 +
 135 +static u32 fe_get_msglevel(struct net_device *dev)
 136 +{
 137 +       struct fe_priv *priv = netdev_priv(dev);
 138 +
 139 +       return priv->msg_enable;
 140 +}
 141 +
 142 +static void fe_set_msglevel(struct net_device *dev, u32 value)
 143 +{
 144 +       struct fe_priv *priv = netdev_priv(dev);
 145 +
 146 +       priv->msg_enable = value;
 147 +}
 148 +
 149 +static int fe_nway_reset(struct net_device *dev)
 150 +{
 151 +       struct fe_priv *priv = netdev_priv(dev);
 152 +
 153 +       if (!priv->phy_dev)
 154 +               goto out_nway_reset;
 155 +
 156 +       return genphy_restart_aneg(priv->phy_dev);
 157 +
 158 +out_nway_reset:
 159 +       return -EOPNOTSUPP;
 160 +}
 161 +
 162 +static u32 fe_get_link(struct net_device *dev)
 163 +{
 164 +       struct fe_priv *priv = netdev_priv(dev);
 165 +       int err;
 166 +
 167 +       if (!priv->phy_dev)
 168 +               goto out_get_link;
 169 +
 170 +       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
 171 +               err = genphy_update_link(priv->phy_dev);
 172 +               if (err)
 173 +                       goto out_get_link;
 174 +       }
 175 +
 176 +       return priv->phy_dev->link;
 177 +
 178 +out_get_link:
 179 +       return ethtool_op_get_link(dev);
 180 +}
 181 +
 182 +static int fe_set_ringparam(struct net_device *dev,
 183 +                           struct ethtool_ringparam *ring)
 184 +{
 185 +       struct fe_priv *priv = netdev_priv(dev);
 186 +
 187 +       if ((ring->tx_pending < 2) ||
 188 +           (ring->rx_pending < 2) ||
 189 +           (ring->rx_pending > MAX_DMA_DESC) ||
 190 +           (ring->tx_pending > MAX_DMA_DESC))
 191 +               return -EINVAL;
 192 +
 193 +       dev->netdev_ops->ndo_stop(dev);
 194 +
 195 +       priv->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);
 196 +       priv->rx_ring.rx_ring_size = BIT(fls(ring->rx_pending) - 1);
 197 +
 198 +       dev->netdev_ops->ndo_open(dev);
 199 +
 200 +       return 0;
 201 +}
 202 +
 203 +static void fe_get_ringparam(struct net_device *dev,
 204 +                            struct ethtool_ringparam *ring)
 205 +{
 206 +       struct fe_priv *priv = netdev_priv(dev);
 207 +
 208 +       ring->rx_max_pending = MAX_DMA_DESC;
 209 +       ring->tx_max_pending = MAX_DMA_DESC;
 210 +       ring->rx_pending = priv->rx_ring.rx_ring_size;
 211 +       ring->tx_pending = priv->tx_ring.tx_ring_size;
 212 +}
 213 +
 214 +static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 215 +{
 216 +       switch (stringset) {
 217 +       case ETH_SS_STATS:
 218 +               memcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));
 219 +               break;
 220 +       }
 221 +}
 222 +
 223 +static int fe_get_sset_count(struct net_device *dev, int sset)
 224 +{
 225 +       switch (sset) {
 226 +       case ETH_SS_STATS:
 227 +               return ARRAY_SIZE(fe_gdma_str);
 228 +       default:
 229 +               return -EOPNOTSUPP;
 230 +       }
 231 +}
 232 +
 233 +static void fe_get_ethtool_stats(struct net_device *dev,
 234 +                                struct ethtool_stats *stats, u64 *data)
 235 +{
 236 +       struct fe_priv *priv = netdev_priv(dev);
 237 +       struct fe_hw_stats *hwstats = priv->hw_stats;
 238 +       u64 *data_src, *data_dst;
 239 +       unsigned int start;
 240 +       int i;
 241 +
 242 +       if (netif_running(dev) && netif_device_present(dev)) {
 243 +               if (spin_trylock(&hwstats->stats_lock)) {
 244 +                       fe_stats_update(priv);
 245 +                       spin_unlock(&hwstats->stats_lock);
 246 +               }
 247 +       }
 248 +
 249 +       do {
 250 +               data_src = &hwstats->tx_bytes;
 251 +               data_dst = data;
 252 +               start = u64_stats_fetch_begin_irq(&hwstats->syncp);
 253 +
 254 +               for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
 255 +                       *data_dst++ = *data_src++;
 256 +
 257 +       } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
 258 +}
 259 +
 260 +static struct ethtool_ops fe_ethtool_ops = {
 261 +       .get_settings           = fe_get_settings,
 262 +       .set_settings           = fe_set_settings,
 263 +       .get_drvinfo            = fe_get_drvinfo,
 264 +       .get_msglevel           = fe_get_msglevel,
 265 +       .set_msglevel           = fe_set_msglevel,
 266 +       .nway_reset             = fe_nway_reset,
 267 +       .get_link               = fe_get_link,
 268 +       .set_ringparam          = fe_set_ringparam,
 269 +       .get_ringparam          = fe_get_ringparam,
 270 +};
 271 +
 272 +void fe_set_ethtool_ops(struct net_device *netdev)
 273 +{
 274 +       struct fe_priv *priv = netdev_priv(netdev);
 275 +       struct fe_soc_data *soc = priv->soc;
 276 +
 277 +       if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
 278 +               fe_ethtool_ops.get_strings = fe_get_strings;
 279 +               fe_ethtool_ops.get_sset_count = fe_get_sset_count;
 280 +               fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
 281 +       }
 282 +
 283 +       netdev->ethtool_ops = &fe_ethtool_ops;
 284 +}
 285 --- /dev/null
 286 +++ b/drivers/net/ethernet/mediatek/ethtool.h
 287 @@ -0,0 +1,22 @@
 288 +/*   This program is free software; you can redistribute it and/or modify
 289 + *   it under the terms of the GNU General Public License as published by
 290 + *   the Free Software Foundation; version 2 of the License
 291 + *
 292 + *   This program is distributed in the hope that it will be useful,
 293 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 294 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 295 + *   GNU General Public License for more details.
 296 + *
 297 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 298 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
 299 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 300 + */
 301 +
 302 +#ifndef FE_ETHTOOL_H
 303 +#define FE_ETHTOOL_H
 304 +
 305 +#include <linux/ethtool.h>
 306 +
 307 +void fe_set_ethtool_ops(struct net_device *netdev);
 308 +
 309 +#endif /* FE_ETHTOOL_H */
 310 --- /dev/null
 311 +++ b/drivers/net/ethernet/mediatek/mdio.c
 312 @@ -0,0 +1,258 @@
 313 +/*   This program is free software; you can redistribute it and/or modify
 314 + *   it under the terms of the GNU General Public License as published by
 315 + *   the Free Software Foundation; version 2 of the License
 316 + *
 317 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 318 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
 319 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 320 + */
 321 +
 322 +#include <linux/module.h>
 323 +#include <linux/kernel.h>
 324 +#include <linux/phy.h>
 325 +#include <linux/of_net.h>
 326 +#include <linux/of_mdio.h>
 327 +
 328 +#include "mtk_eth_soc.h"
 329 +#include "mdio.h"
 330 +
 331 +static int fe_mdio_reset(struct mii_bus *bus)
 332 +{
 333 +       /* TODO */
 334 +       return 0;
 335 +}
 336 +
 337 +static void fe_phy_link_adjust(struct net_device *dev)
 338 +{
 339 +       struct fe_priv *priv = netdev_priv(dev);
 340 +       unsigned long flags;
 341 +       int i;
 342 +
 343 +       spin_lock_irqsave(&priv->phy->lock, flags);
 344 +       for (i = 0; i < 8; i++) {
 345 +               if (priv->phy->phy_node[i]) {
 346 +                       struct phy_device *phydev = priv->phy->phy[i];
 347 +                       int status_change = 0;
 348 +
 349 +                       if (phydev->link)
 350 +                               if (priv->phy->duplex[i] != phydev->duplex ||
 351 +                                   priv->phy->speed[i] != phydev->speed)
 352 +                                       status_change = 1;
 353 +
 354 +                       if (phydev->link != priv->link[i])
 355 +                               status_change = 1;
 356 +
 357 +                       switch (phydev->speed) {
 358 +                       case SPEED_1000:
 359 +                       case SPEED_100:
 360 +                       case SPEED_10:
 361 +                               priv->link[i] = phydev->link;
 362 +                               priv->phy->duplex[i] = phydev->duplex;
 363 +                               priv->phy->speed[i] = phydev->speed;
 364 +
 365 +                               if (status_change &&
 366 +                                   priv->soc->mdio_adjust_link)
 367 +                                       priv->soc->mdio_adjust_link(priv, i);
 368 +                               break;
 369 +                       }
 370 +               }
 371 +       }
 372 +}
 373 +
 374 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
 375 +{
 376 +       const __be32 *_port = NULL;
 377 +       struct phy_device *phydev;
 378 +       int phy_mode, port;
 379 +
 380 +       _port = of_get_property(phy_node, "reg", NULL);
 381 +
 382 +       if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
 383 +               pr_err("%s: invalid port id\n", phy_node->name);
 384 +               return -EINVAL;
 385 +       }
 386 +       port = be32_to_cpu(*_port);
 387 +       phy_mode = of_get_phy_mode(phy_node);
 388 +       if (phy_mode < 0) {
 389 +               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
 390 +               priv->phy->phy_node[port] = NULL;
 391 +               return -EINVAL;
 392 +       }
 393 +
 394 +       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
 395 +                               0, phy_mode);
 396 +       if (IS_ERR(phydev)) {
 397 +               dev_err(priv->device, "could not connect to PHY\n");
 398 +               priv->phy->phy_node[port] = NULL;
 399 +               return PTR_ERR(phydev);
 400 +       }
 401 +
 402 +       phydev->supported &= PHY_GBIT_FEATURES;
 403 +       phydev->advertising = phydev->supported;
 404 +
 405 +       dev_info(priv->device,
 406 +                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
 407 +                port, dev_name(&phydev->dev), phydev->phy_id,
 408 +                phydev->drv->name);
 409 +
 410 +       priv->phy->phy[port] = phydev;
 411 +       priv->link[port] = 0;
 412 +
 413 +       return 0;
 414 +}
 415 +
 416 +static void phy_init(struct fe_priv *priv, struct phy_device *phy)
 417 +{
 418 +       phy_attach(priv->netdev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
 419 +
 420 +       phy->autoneg = AUTONEG_ENABLE;
 421 +       phy->speed = 0;
 422 +       phy->duplex = 0;
 423 +       phy->supported &= PHY_BASIC_FEATURES;
 424 +       phy->advertising = phy->supported | ADVERTISED_Autoneg;
 425 +
 426 +       phy_start_aneg(phy);
 427 +}
 428 +
 429 +static int fe_phy_connect(struct fe_priv *priv)
 430 +{
 431 +       int i;
 432 +
 433 +       for (i = 0; i < 8; i++) {
 434 +               if (priv->phy->phy_node[i]) {
 435 +                       if (!priv->phy_dev) {
 436 +                               priv->phy_dev = priv->phy->phy[i];
 437 +                               priv->phy_flags = FE_PHY_FLAG_PORT;
 438 +                       }
 439 +               } else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
 440 +                       phy_init(priv, priv->mii_bus->phy_map[i]);
 441 +                       if (!priv->phy_dev) {
 442 +                               priv->phy_dev = priv->mii_bus->phy_map[i];
 443 +                               priv->phy_flags = FE_PHY_FLAG_ATTACH;
 444 +                       }
 445 +               }
 446 +       }
 447 +
 448 +       return 0;
 449 +}
 450 +
 451 +static void fe_phy_disconnect(struct fe_priv *priv)
 452 +{
 453 +       unsigned long flags;
 454 +       int i;
 455 +
 456 +       for (i = 0; i < 8; i++)
 457 +               if (priv->phy->phy_fixed[i]) {
 458 +                       spin_lock_irqsave(&priv->phy->lock, flags);
 459 +                       priv->link[i] = 0;
 460 +                       if (priv->soc->mdio_adjust_link)
 461 +                               priv->soc->mdio_adjust_link(priv, i);
 462 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
 463 +               } else if (priv->phy->phy[i]) {
 464 +                       phy_disconnect(priv->phy->phy[i]);
 465 +               } else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
 466 +                       phy_detach(priv->mii_bus->phy_map[i]);
 467 +               }
 468 +}
 469 +
 470 +static void fe_phy_start(struct fe_priv *priv)
 471 +{
 472 +       unsigned long flags;
 473 +       int i;
 474 +
 475 +       for (i = 0; i < 8; i++) {
 476 +               if (priv->phy->phy_fixed[i]) {
 477 +                       spin_lock_irqsave(&priv->phy->lock, flags);
 478 +                       priv->link[i] = 1;
 479 +                       if (priv->soc->mdio_adjust_link)
 480 +                               priv->soc->mdio_adjust_link(priv, i);
 481 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
 482 +               } else if (priv->phy->phy[i]) {
 483 +                       phy_start(priv->phy->phy[i]);
 484 +               }
 485 +       }
 486 +}
 487 +
 488 +static void fe_phy_stop(struct fe_priv *priv)
 489 +{
 490 +       unsigned long flags;
 491 +       int i;
 492 +
 493 +       for (i = 0; i < 8; i++)
 494 +               if (priv->phy->phy_fixed[i]) {
 495 +                       spin_lock_irqsave(&priv->phy->lock, flags);
 496 +                       priv->link[i] = 0;
 497 +                       if (priv->soc->mdio_adjust_link)
 498 +                               priv->soc->mdio_adjust_link(priv, i);
 499 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
 500 +               } else if (priv->phy->phy[i]) {
 501 +                       phy_stop(priv->phy->phy[i]);
 502 +               }
 503 +}
 504 +
 505 +static struct fe_phy phy_ralink = {
 506 +       .connect = fe_phy_connect,
 507 +       .disconnect = fe_phy_disconnect,
 508 +       .start = fe_phy_start,
 509 +       .stop = fe_phy_stop,
 510 +};
 511 +
 512 +int fe_mdio_init(struct fe_priv *priv)
 513 +{
 514 +       struct device_node *mii_np;
 515 +       int err;
 516 +
 517 +       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
 518 +               return 0;
 519 +
 520 +       spin_lock_init(&phy_ralink.lock);
 521 +       priv->phy = &phy_ralink;
 522 +
 523 +       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
 524 +       if (!mii_np) {
 525 +               dev_err(priv->device, "no %s child node found", "mdio-bus");
 526 +               return -ENODEV;
 527 +       }
 528 +
 529 +       if (!of_device_is_available(mii_np)) {
 530 +               err = 0;
 531 +               goto err_put_node;
 532 +       }
 533 +
 534 +       priv->mii_bus = mdiobus_alloc();
 535 +       if (!priv->mii_bus) {
 536 +               err = -ENOMEM;
 537 +               goto err_put_node;
 538 +       }
 539 +
 540 +       priv->mii_bus->name = "mdio";
 541 +       priv->mii_bus->read = priv->soc->mdio_read;
 542 +       priv->mii_bus->write = priv->soc->mdio_write;
 543 +       priv->mii_bus->reset = fe_mdio_reset;
 544 +       priv->mii_bus->priv = priv;
 545 +       priv->mii_bus->parent = priv->device;
 546 +
 547 +       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
 548 +       err = of_mdiobus_register(priv->mii_bus, mii_np);
 549 +       if (err)
 550 +               goto err_free_bus;
 551 +
 552 +       return 0;
 553 +
 554 +err_free_bus:
 555 +       kfree(priv->mii_bus);
 556 +err_put_node:
 557 +       of_node_put(mii_np);
 558 +       priv->mii_bus = NULL;
 559 +       return err;
 560 +}
 561 +
 562 +void fe_mdio_cleanup(struct fe_priv *priv)
 563 +{
 564 +       if (!priv->mii_bus)
 565 +               return;
 566 +
 567 +       mdiobus_unregister(priv->mii_bus);
 568 +       of_node_put(priv->mii_bus->dev.of_node);
 569 +       kfree(priv->mii_bus);
 570 +}
 571 --- /dev/null
 572 +++ b/drivers/net/ethernet/mediatek/mdio.h
 573 @@ -0,0 +1,27 @@
 574 +/*   This program is free software; you can redistribute it and/or modify
 575 + *   it under the terms of the GNU General Public License as published by
 576 + *   the Free Software Foundation; version 2 of the License
 577 + *
 578 + *   This program is distributed in the hope that it will be useful,
 579 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 580 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 581 + *   GNU General Public License for more details.
 582 + *
 583 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 584 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
 585 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 586 + */
 587 +
 588 +#ifndef _RALINK_MDIO_H__
 589 +#define _RALINK_MDIO_H__
 590 +
 591 +#ifdef CONFIG_NET_MEDIATEK_MDIO
 592 +int fe_mdio_init(struct fe_priv *priv);
 593 +void fe_mdio_cleanup(struct fe_priv *priv);
 594 +int fe_connect_phy_node(struct fe_priv *priv,
 595 +                       struct device_node *phy_node);
 596 +#else
 597 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
 598 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
 599 +#endif
 600 +#endif
 601 --- /dev/null
 602 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 603 @@ -0,0 +1,1607 @@
 604 +/*   This program is free software; you can redistribute it and/or modify
 605 + *   it under the terms of the GNU General Public License as published by
 606 + *   the Free Software Foundation; version 2 of the License
 607 + *
 608 + *   This program is distributed in the hope that it will be useful,
 609 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 610 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 611 + *   GNU General Public License for more details.
 612 + *
 613 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 614 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
 615 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 616 + */
 617 +
 618 +#include <linux/module.h>
 619 +#include <linux/kernel.h>
 620 +#include <linux/types.h>
 621 +#include <linux/dma-mapping.h>
 622 +#include <linux/init.h>
 623 +#include <linux/skbuff.h>
 624 +#include <linux/etherdevice.h>
 625 +#include <linux/ethtool.h>
 626 +#include <linux/platform_device.h>
 627 +#include <linux/of_device.h>
 628 +#include <linux/clk.h>
 629 +#include <linux/of_net.h>
 630 +#include <linux/of_mdio.h>
 631 +#include <linux/if_vlan.h>
 632 +#include <linux/reset.h>
 633 +#include <linux/tcp.h>
 634 +#include <linux/io.h>
 635 +#include <linux/bug.h>
 636 +
 637 +#include <asm/mach-ralink/ralink_regs.h>
 638 +
 639 +#include "mtk_eth_soc.h"
 640 +#include "mdio.h"
 641 +#include "ethtool.h"
 642 +
 643 +#define        MAX_RX_LENGTH           1536
 644 +#define FE_RX_ETH_HLEN         (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
 645 +#define FE_RX_HLEN             (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
 646 +#define DMA_DUMMY_DESC         0xffffffff
 647 +#define FE_DEFAULT_MSG_ENABLE \
 648 +               (NETIF_MSG_DRV | \
 649 +               NETIF_MSG_PROBE | \
 650 +               NETIF_MSG_LINK | \
 651 +               NETIF_MSG_TIMER | \
 652 +               NETIF_MSG_IFDOWN | \
 653 +               NETIF_MSG_IFUP | \
 654 +               NETIF_MSG_RX_ERR | \
 655 +               NETIF_MSG_TX_ERR)
 656 +
 657 +#define TX_DMA_DESP2_DEF       (TX_DMA_LS0 | TX_DMA_DONE)
 658 +#define TX_DMA_DESP4_DEF       (TX_DMA_QN(3) | TX_DMA_PN(1))
 659 +#define NEXT_TX_DESP_IDX(X)    (((X) + 1) & (ring->tx_ring_size - 1))
 660 +#define NEXT_RX_DESP_IDX(X)    (((X) + 1) & (ring->rx_ring_size - 1))
 661 +
 662 +#define SYSC_REG_RSTCTRL       0x34
 663 +
 664 +static int fe_msg_level = -1;
 665 +module_param_named(msg_level, fe_msg_level, int, 0);
 666 +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
 667 +
 668 +static const u16 fe_reg_table_default[FE_REG_COUNT] = {
 669 +       [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
 670 +       [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
 671 +       [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
 672 +       [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
 673 +       [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
 674 +       [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
 675 +       [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
 676 +       [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
 677 +       [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
 678 +       [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
 679 +       [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
 680 +       [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
 681 +       [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
 682 +       [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
 683 +       [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
 684 +       [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
 685 +};
 686 +
 687 +static const u16 *fe_reg_table = fe_reg_table_default;
 688 +
 689 +struct fe_work_t {
 690 +       int bitnr;
 691 +       void (*action)(struct fe_priv *);
 692 +};
 693 +
 694 +static void __iomem *fe_base;
 695 +
 696 +void fe_w32(u32 val, unsigned reg)
 697 +{
 698 +       __raw_writel(val, fe_base + reg);
 699 +}
 700 +
 701 +u32 fe_r32(unsigned reg)
 702 +{
 703 +       return __raw_readl(fe_base + reg);
 704 +}
 705 +
 706 +void fe_reg_w32(u32 val, enum fe_reg reg)
 707 +{
 708 +       fe_w32(val, fe_reg_table[reg]);
 709 +}
 710 +
 711 +u32 fe_reg_r32(enum fe_reg reg)
 712 +{
 713 +       return fe_r32(fe_reg_table[reg]);
 714 +}
 715 +
 716 +void fe_reset(u32 reset_bits)
 717 +{
 718 +       u32 t;
 719 +
 720 +       t = rt_sysc_r32(SYSC_REG_RSTCTRL);
 721 +       t |= reset_bits;
 722 +       rt_sysc_w32(t, SYSC_REG_RSTCTRL);
 723 +       usleep_range(10, 20);
 724 +
 725 +       t &= ~reset_bits;
 726 +       rt_sysc_w32(t, SYSC_REG_RSTCTRL);
 727 +       usleep_range(10, 20);
 728 +}
 729 +
 730 +static inline void fe_int_disable(u32 mask)
 731 +{
 732 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
 733 +                  FE_REG_FE_INT_ENABLE);
 734 +       /* flush write */
 735 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
 736 +}
 737 +
 738 +static inline void fe_int_enable(u32 mask)
 739 +{
 740 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
 741 +                  FE_REG_FE_INT_ENABLE);
 742 +       /* flush write */
 743 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
 744 +}
 745 +
 746 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
 747 +{
 748 +       unsigned long flags;
 749 +
 750 +       spin_lock_irqsave(&priv->page_lock, flags);
 751 +       fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
 752 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 753 +              FE_GDMA1_MAC_ADRL);
 754 +       spin_unlock_irqrestore(&priv->page_lock, flags);
 755 +}
 756 +
 757 +static int fe_set_mac_address(struct net_device *dev, void *p)
 758 +{
 759 +       int ret = eth_mac_addr(dev, p);
 760 +
 761 +       if (!ret) {
 762 +               struct fe_priv *priv = netdev_priv(dev);
 763 +
 764 +               if (priv->soc->set_mac)
 765 +                       priv->soc->set_mac(priv, dev->dev_addr);
 766 +               else
 767 +                       fe_hw_set_macaddr(priv, p);
 768 +       }
 769 +
 770 +       return ret;
 771 +}
 772 +
 773 +static inline int fe_max_frag_size(int mtu)
 774 +{
 775 +       /* make sure buf_size will be at least MAX_RX_LENGTH */
 776 +       if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
 777 +               mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
 778 +
 779 +       return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
 780 +               SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 781 +}
 782 +
 783 +static inline int fe_max_buf_size(int frag_size)
 784 +{
 785 +       int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
 786 +                      SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 787 +
 788 +       BUG_ON(buf_size < MAX_RX_LENGTH);
 789 +       return buf_size;
 790 +}
 791 +
 792 +static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
 793 +{
 794 +       rxd->rxd1 = dma_rxd->rxd1;
 795 +       rxd->rxd2 = dma_rxd->rxd2;
 796 +       rxd->rxd3 = dma_rxd->rxd3;
 797 +       rxd->rxd4 = dma_rxd->rxd4;
 798 +}
 799 +
 800 +static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
 801 +{
 802 +       dma_txd->txd1 = txd->txd1;
 803 +       dma_txd->txd3 = txd->txd3;
 804 +       dma_txd->txd4 = txd->txd4;
 805 +       /* clean dma done flag last */
 806 +       dma_txd->txd2 = txd->txd2;
 807 +}
 808 +
 809 +static void fe_clean_rx(struct fe_priv *priv)
 810 +{
 811 +       int i;
 812 +       struct fe_rx_ring *ring = &priv->rx_ring;
 813 +
 814 +       if (ring->rx_data) {
 815 +               for (i = 0; i < ring->rx_ring_size; i++)
 816 +                       if (ring->rx_data[i]) {
 817 +                               if (ring->rx_dma && ring->rx_dma[i].rxd1)
 818 +                                       dma_unmap_single(&priv->netdev->dev,
 819 +                                                        ring->rx_dma[i].rxd1,
 820 +                                                        ring->rx_buf_size,
 821 +                                                        DMA_FROM_DEVICE);
 822 +                               put_page(virt_to_head_page(ring->rx_data[i]));
 823 +                       }
 824 +
 825 +               kfree(ring->rx_data);
 826 +               ring->rx_data = NULL;
 827 +       }
 828 +
 829 +       if (ring->rx_dma) {
 830 +               dma_free_coherent(&priv->netdev->dev,
 831 +                                 ring->rx_ring_size * sizeof(*ring->rx_dma),
 832 +                                 ring->rx_dma,
 833 +                                 ring->rx_phys);
 834 +               ring->rx_dma = NULL;
 835 +       }
 836 +}
 837 +
 838 +static int fe_alloc_rx(struct fe_priv *priv)
 839 +{
 840 +       struct net_device *netdev = priv->netdev;
 841 +       struct fe_rx_ring *ring = &priv->rx_ring;
 842 +       int i, pad;
 843 +
 844 +       ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
 845 +                       GFP_KERNEL);
 846 +       if (!ring->rx_data)
 847 +               goto no_rx_mem;
 848 +
 849 +       for (i = 0; i < ring->rx_ring_size; i++) {
 850 +               ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
 851 +               if (!ring->rx_data[i])
 852 +                       goto no_rx_mem;
 853 +       }
 854 +
 855 +       ring->rx_dma = dma_alloc_coherent(&netdev->dev,
 856 +                       ring->rx_ring_size * sizeof(*ring->rx_dma),
 857 +                       &ring->rx_phys,
 858 +                       GFP_ATOMIC | __GFP_ZERO);
 859 +       if (!ring->rx_dma)
 860 +               goto no_rx_mem;
 861 +
 862 +       if (priv->flags & FE_FLAG_RX_2B_OFFSET)
 863 +               pad = 0;
 864 +       else
 865 +               pad = NET_IP_ALIGN;
 866 +       for (i = 0; i < ring->rx_ring_size; i++) {
 867 +               dma_addr_t dma_addr = dma_map_single(&netdev->dev,
 868 +                               ring->rx_data[i] + NET_SKB_PAD + pad,
 869 +                               ring->rx_buf_size,
 870 +                               DMA_FROM_DEVICE);
 871 +               if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
 872 +                       goto no_rx_mem;
 873 +               ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
 874 +
 875 +               if (priv->flags & FE_FLAG_RX_SG_DMA)
 876 +                       ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
 877 +               else
 878 +                       ring->rx_dma[i].rxd2 = RX_DMA_LSO;
 879 +       }
 880 +       ring->rx_calc_idx = ring->rx_ring_size - 1;
 881 +       /* make sure that all changes to the dma ring are flushed before we
 882 +        * continue
 883 +        */
 884 +       wmb();
 885 +
 886 +       fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
 887 +       fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
 888 +       fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
 889 +       fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
 890 +
 891 +       return 0;
 892 +
 893 +no_rx_mem:
 894 +       return -ENOMEM;
 895 +}
 896 +
 897 +static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
 898 +{
 899 +       if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
 900 +               dma_unmap_single(dev,
 901 +                                dma_unmap_addr(tx_buf, dma_addr0),
 902 +                                dma_unmap_len(tx_buf, dma_len0),
 903 +                                DMA_TO_DEVICE);
 904 +       } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
 905 +               dma_unmap_page(dev,
 906 +                              dma_unmap_addr(tx_buf, dma_addr0),
 907 +                              dma_unmap_len(tx_buf, dma_len0),
 908 +                              DMA_TO_DEVICE);
 909 +       }
 910 +       if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
 911 +               dma_unmap_page(dev,
 912 +                              dma_unmap_addr(tx_buf, dma_addr1),
 913 +                              dma_unmap_len(tx_buf, dma_len1),
 914 +                              DMA_TO_DEVICE);
 915 +
 916 +       tx_buf->flags = 0;
 917 +       if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
 918 +               dev_kfree_skb_any(tx_buf->skb);
 919 +       tx_buf->skb = NULL;
 920 +}
 921 +
 922 +static void fe_clean_tx(struct fe_priv *priv)
 923 +{
 924 +       int i;
 925 +       struct device *dev = &priv->netdev->dev;
 926 +       struct fe_tx_ring *ring = &priv->tx_ring;
 927 +
 928 +       if (ring->tx_buf) {
 929 +               for (i = 0; i < ring->tx_ring_size; i++)
 930 +                       fe_txd_unmap(dev, &ring->tx_buf[i]);
 931 +               kfree(ring->tx_buf);
 932 +               ring->tx_buf = NULL;
 933 +       }
 934 +
 935 +       if (ring->tx_dma) {
 936 +               dma_free_coherent(dev,
 937 +                                 ring->tx_ring_size * sizeof(*ring->tx_dma),
 938 +                                 ring->tx_dma,
 939 +                                 ring->tx_phys);
 940 +               ring->tx_dma = NULL;
 941 +       }
 942 +
 943 +       netdev_reset_queue(priv->netdev);
 944 +}
 945 +
 946 +static int fe_alloc_tx(struct fe_priv *priv)
 947 +{
 948 +       int i;
 949 +       struct fe_tx_ring *ring = &priv->tx_ring;
 950 +
 951 +       ring->tx_free_idx = 0;
 952 +       ring->tx_next_idx = 0;
 953 +       ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
 954 +                             MAX_SKB_FRAGS);
 955 +
 956 +       ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
 957 +                       GFP_KERNEL);
 958 +       if (!ring->tx_buf)
 959 +               goto no_tx_mem;
 960 +
 961 +       ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
 962 +                       ring->tx_ring_size * sizeof(*ring->tx_dma),
 963 +                       &ring->tx_phys,
 964 +                       GFP_ATOMIC | __GFP_ZERO);
 965 +       if (!ring->tx_dma)
 966 +               goto no_tx_mem;
 967 +
 968 +       for (i = 0; i < ring->tx_ring_size; i++) {
 969 +               if (priv->soc->tx_dma)
 970 +                       priv->soc->tx_dma(&ring->tx_dma[i]);
 971 +               ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
 972 +       }
 973 +       /* make sure that all changes to the dma ring are flushed before we
 974 +        * continue
 975 +        */
 976 +       wmb();
 977 +
 978 +       fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
 979 +       fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
 980 +       fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
 981 +       fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
 982 +
 983 +       return 0;
 984 +
 985 +no_tx_mem:
 986 +       return -ENOMEM;
 987 +}
 988 +
 989 +static int fe_init_dma(struct fe_priv *priv)
 990 +{
 991 +       int err;
 992 +
 993 +       err = fe_alloc_tx(priv);
 994 +       if (err)
 995 +               return err;
 996 +
 997 +       err = fe_alloc_rx(priv);
 998 +       if (err)
 999 +               return err;
1000 +
1001 +       return 0;
1002 +}
1003 +
1004 +static void fe_free_dma(struct fe_priv *priv)
1005 +{
1006 +       fe_clean_tx(priv);
1007 +       fe_clean_rx(priv);
1008 +}
1009 +
1010 +void fe_stats_update(struct fe_priv *priv)
1011 +{
1012 +       struct fe_hw_stats *hwstats = priv->hw_stats;
1013 +       unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
1014 +       u64 stats;
1015 +
1016 +       u64_stats_update_begin(&hwstats->syncp);
1017 +
1018 +       if (IS_ENABLED(CONFIG_SOC_MT7621)) {
1019 +               hwstats->rx_bytes                       += fe_r32(base);
1020 +               stats                                   =  fe_r32(base + 0x04);
1021 +               if (stats)
1022 +                       hwstats->rx_bytes               += (stats << 32);
1023 +               hwstats->rx_packets                     += fe_r32(base + 0x08);
1024 +               hwstats->rx_overflow                    += fe_r32(base + 0x10);
1025 +               hwstats->rx_fcs_errors                  += fe_r32(base + 0x14);
1026 +               hwstats->rx_short_errors                += fe_r32(base + 0x18);
1027 +               hwstats->rx_long_errors                 += fe_r32(base + 0x1c);
1028 +               hwstats->rx_checksum_errors             += fe_r32(base + 0x20);
1029 +               hwstats->rx_flow_control_packets        += fe_r32(base + 0x24);
1030 +               hwstats->tx_skip                        += fe_r32(base + 0x28);
1031 +               hwstats->tx_collisions                  += fe_r32(base + 0x2c);
1032 +               hwstats->tx_bytes                       += fe_r32(base + 0x30);
1033 +               stats                                   =  fe_r32(base + 0x34);
1034 +               if (stats)
1035 +                       hwstats->tx_bytes               += (stats << 32);
1036 +               hwstats->tx_packets                     += fe_r32(base + 0x38);
1037 +       } else {
1038 +               hwstats->tx_bytes                       += fe_r32(base);
1039 +               hwstats->tx_packets                     += fe_r32(base + 0x04);
1040 +               hwstats->tx_skip                        += fe_r32(base + 0x08);
1041 +               hwstats->tx_collisions                  += fe_r32(base + 0x0c);
1042 +               hwstats->rx_bytes                       += fe_r32(base + 0x20);
1043 +               hwstats->rx_packets                     += fe_r32(base + 0x24);
1044 +               hwstats->rx_overflow                    += fe_r32(base + 0x28);
1045 +               hwstats->rx_fcs_errors                  += fe_r32(base + 0x2c);
1046 +               hwstats->rx_short_errors                += fe_r32(base + 0x30);
1047 +               hwstats->rx_long_errors                 += fe_r32(base + 0x34);
1048 +               hwstats->rx_checksum_errors             += fe_r32(base + 0x38);
1049 +               hwstats->rx_flow_control_packets        += fe_r32(base + 0x3c);
1050 +       }
1051 +
1052 +       u64_stats_update_end(&hwstats->syncp);
1053 +}
1054 +
1055 +static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
1056 +                               struct rtnl_link_stats64 *storage)
1057 +{
1058 +       struct fe_priv *priv = netdev_priv(dev);
1059 +       struct fe_hw_stats *hwstats = priv->hw_stats;
1060 +       unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
1061 +       unsigned int start;
1062 +
1063 +       if (!base) {
1064 +               netdev_stats_to_stats64(storage, &dev->stats);
1065 +               return storage;
1066 +       }
1067 +
1068 +       if (netif_running(dev) && netif_device_present(dev)) {
1069 +               if (spin_trylock(&hwstats->stats_lock)) {
1070 +                       fe_stats_update(priv);
1071 +                       spin_unlock(&hwstats->stats_lock);
1072 +               }
1073 +       }
1074 +
1075 +       do {
1076 +               start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1077 +               storage->rx_packets = hwstats->rx_packets;
1078 +               storage->tx_packets = hwstats->tx_packets;
1079 +               storage->rx_bytes = hwstats->rx_bytes;
1080 +               storage->tx_bytes = hwstats->tx_bytes;
1081 +               storage->collisions = hwstats->tx_collisions;
1082 +               storage->rx_length_errors = hwstats->rx_short_errors +
1083 +                       hwstats->rx_long_errors;
1084 +               storage->rx_over_errors = hwstats->rx_overflow;
1085 +               storage->rx_crc_errors = hwstats->rx_fcs_errors;
1086 +               storage->rx_errors = hwstats->rx_checksum_errors;
1087 +               storage->tx_aborted_errors = hwstats->tx_skip;
1088 +       } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1089 +
1090 +       storage->tx_errors = priv->netdev->stats.tx_errors;
1091 +       storage->rx_dropped = priv->netdev->stats.rx_dropped;
1092 +       storage->tx_dropped = priv->netdev->stats.tx_dropped;
1093 +
1094 +       return storage;
1095 +}
1096 +
1097 +static int fe_vlan_rx_add_vid(struct net_device *dev,
1098 +                             __be16 proto, u16 vid)
1099 +{
1100 +       struct fe_priv *priv = netdev_priv(dev);
1101 +       u32 idx = (vid & 0xf);
1102 +       u32 vlan_cfg;
1103 +
1104 +       if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
1105 +             (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
1106 +               return 0;
1107 +
1108 +       if (test_bit(idx, &priv->vlan_map)) {
1109 +               netdev_warn(dev, "disable tx vlan offload\n");
1110 +               dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1111 +               netdev_update_features(dev);
1112 +       } else {
1113 +               vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1114 +                               ((idx >> 1) << 2));
1115 +               if (idx & 0x1) {
1116 +                       vlan_cfg &= 0xffff;
1117 +                       vlan_cfg |= (vid << 16);
1118 +               } else {
1119 +                       vlan_cfg &= 0xffff0000;
1120 +                       vlan_cfg |= vid;
1121 +               }
1122 +               fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1123 +                               ((idx >> 1) << 2));
1124 +               set_bit(idx, &priv->vlan_map);
1125 +       }
1126 +
1127 +       return 0;
1128 +}
1129 +
1130 +static int fe_vlan_rx_kill_vid(struct net_device *dev,
1131 +                              __be16 proto, u16 vid)
1132 +{
1133 +       struct fe_priv *priv = netdev_priv(dev);
1134 +       u32 idx = (vid & 0xf);
1135 +
1136 +       if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
1137 +             (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
1138 +               return 0;
1139 +
1140 +       clear_bit(idx, &priv->vlan_map);
1141 +
1142 +       return 0;
1143 +}
1144 +
1145 +static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
1146 +{
1147 +       barrier();
1148 +       return (u32)(ring->tx_ring_size -
1149 +                       ((ring->tx_next_idx - ring->tx_free_idx) &
1150 +                        (ring->tx_ring_size - 1)));
1151 +}
1152 +
1153 +static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
1154 +                        int tx_num, struct fe_tx_ring *ring)
1155 +{
1156 +       struct fe_priv *priv = netdev_priv(dev);
1157 +       struct skb_frag_struct *frag;
1158 +       struct fe_tx_dma txd, *ptxd;
1159 +       struct fe_tx_buf *tx_buf;
1160 +       dma_addr_t mapped_addr;
1161 +       unsigned int nr_frags;
1162 +       u32 def_txd4;
1163 +       int i, j, k, frag_size, frag_map_size, offset;
1164 +
1165 +       tx_buf = &ring->tx_buf[ring->tx_next_idx];
1166 +       memset(tx_buf, 0, sizeof(*tx_buf));
1167 +       memset(&txd, 0, sizeof(txd));
1168 +       nr_frags = skb_shinfo(skb)->nr_frags;
1169 +
1170 +       /* init tx descriptor */
1171 +       if (priv->soc->tx_dma)
1172 +               priv->soc->tx_dma(&txd);
1173 +       else
1174 +               txd.txd4 = TX_DMA_DESP4_DEF;
1175 +       def_txd4 = txd.txd4;
1176 +
1177 +       /* TX Checksum offload */
1178 +       if (skb->ip_summed == CHECKSUM_PARTIAL)
1179 +               txd.txd4 |= TX_DMA_CHKSUM;
1180 +
1181 +       /* VLAN header offload */
1182 +       if (skb_vlan_tag_present(skb)) {
1183 +               u16 tag = skb_vlan_tag_get(skb);
1184 +
1185 +               if (IS_ENABLED(CONFIG_SOC_MT7621))
1186 +                       txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
1187 +               else
1188 +                       txd.txd4 |= TX_DMA_INS_VLAN |
1189 +                               ((tag >> VLAN_PRIO_SHIFT) << 4) |
1190 +                               (tag & 0xF);
1191 +       }
1192 +
1193 +       /* TSO: fill MSS info in tcp checksum field */
1194 +       if (skb_is_gso(skb)) {
1195 +               if (skb_cow_head(skb, 0)) {
1196 +                       netif_warn(priv, tx_err, dev,
1197 +                                  "GSO expand head fail.\n");
1198 +                       goto err_out;
1199 +               }
1200 +               if (skb_shinfo(skb)->gso_type &
1201 +                               (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1202 +                       txd.txd4 |= TX_DMA_TSO;
1203 +                       tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1204 +               }
1205 +       }
1206 +
1207 +       mapped_addr = dma_map_single(&dev->dev, skb->data,
1208 +                                    skb_headlen(skb), DMA_TO_DEVICE);
1209 +       if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
1210 +               goto err_out;
1211 +       txd.txd1 = mapped_addr;
1212 +       txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
1213 +
1214 +       tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
1215 +       dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1216 +       dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
1217 +
1218 +       /* TX SG offload */
1219 +       j = ring->tx_next_idx;
1220 +       k = 0;
1221 +       for (i = 0; i < nr_frags; i++) {
1222 +               offset = 0;
1223 +               frag = &skb_shinfo(skb)->frags[i];
1224 +               frag_size = skb_frag_size(frag);
1225 +
1226 +               while (frag_size > 0) {
1227 +                       frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
1228 +                       mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
1229 +                                                      frag_map_size,
1230 +                                                      DMA_TO_DEVICE);
1231 +                       if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
1232 +                               goto err_dma;
1233 +
1234 +                       if (k & 0x1) {
1235 +                               j = NEXT_TX_DESP_IDX(j);
1236 +                               txd.txd1 = mapped_addr;
1237 +                               txd.txd2 = TX_DMA_PLEN0(frag_map_size);
1238 +                               txd.txd4 = def_txd4;
1239 +
1240 +                               tx_buf = &ring->tx_buf[j];
1241 +                               memset(tx_buf, 0, sizeof(*tx_buf));
1242 +
1243 +                               tx_buf->flags |= FE_TX_FLAGS_PAGE0;
1244 +                               dma_unmap_addr_set(tx_buf, dma_addr0,
1245 +                                                  mapped_addr);
1246 +                               dma_unmap_len_set(tx_buf, dma_len0,
1247 +                                                 frag_map_size);
1248 +                       } else {
1249 +                               txd.txd3 = mapped_addr;
1250 +                               txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
1251 +
1252 +                               tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
1253 +                               tx_buf->flags |= FE_TX_FLAGS_PAGE1;
1254 +                               dma_unmap_addr_set(tx_buf, dma_addr1,
1255 +                                                  mapped_addr);
1256 +                               dma_unmap_len_set(tx_buf, dma_len1,
1257 +                                                 frag_map_size);
1258 +
1259 +                               if (!((i == (nr_frags - 1)) &&
1260 +                                     (frag_map_size == frag_size))) {
1261 +                                       fe_set_txd(&txd, &ring->tx_dma[j]);
1262 +                                       memset(&txd, 0, sizeof(txd));
1263 +                               }
1264 +                       }
1265 +                       frag_size -= frag_map_size;
1266 +                       offset += frag_map_size;
1267 +                       k++;
1268 +               }
1269 +       }
1270 +
1271 +       /* set last segment */
1272 +       if (k & 0x1)
1273 +               txd.txd2 |= TX_DMA_LS1;
1274 +       else
1275 +               txd.txd2 |= TX_DMA_LS0;
1276 +       fe_set_txd(&txd, &ring->tx_dma[j]);
1277 +
1278 +       /* store skb to cleanup */
1279 +       tx_buf->skb = skb;
1280 +
1281 +       netdev_sent_queue(dev, skb->len);
1282 +       skb_tx_timestamp(skb);
1283 +
1284 +       ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
1285 +       /* make sure that all changes to the dma ring are flushed before we
1286 +        * continue
1287 +        */
1288 +       wmb();
1289 +       if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
1290 +               netif_stop_queue(dev);
1291 +               smp_mb();
1292 +               if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
1293 +                       netif_wake_queue(dev);
1294 +       }
1295 +
1296 +       if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
1297 +               fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
1298 +
1299 +       return 0;
1300 +
1301 +err_dma:
1302 +       j = ring->tx_next_idx;
1303 +       for (i = 0; i < tx_num; i++) {
1304 +               ptxd = &ring->tx_dma[j];
1305 +               tx_buf = &ring->tx_buf[j];
1306 +
1307 +               /* unmap dma */
1308 +               fe_txd_unmap(&dev->dev, tx_buf);
1309 +
1310 +               ptxd->txd2 = TX_DMA_DESP2_DEF;
1311 +               j = NEXT_TX_DESP_IDX(j);
1312 +       }
1313 +       /* make sure that all changes to the dma ring are flushed before we
1314 +        * continue
1315 +        */
1316 +       wmb();
1317 +
1318 +err_out:
1319 +       return -1;
1320 +}
1321 +
1322 +static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
1323 +{
1324 +       unsigned int len;
1325 +       int ret;
1326 +
1327 +       ret = 0;
1328 +       if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
1329 +               if ((priv->flags & FE_FLAG_PADDING_64B) &&
1330 +                   !(priv->flags & FE_FLAG_PADDING_BUG))
1331 +                       return ret;
1332 +
1333 +               if (skb_vlan_tag_present(skb))
1334 +                       len = ETH_ZLEN;
1335 +               else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
1336 +                       len = VLAN_ETH_ZLEN;
1337 +               else if (!(priv->flags & FE_FLAG_PADDING_64B))
1338 +                       len = ETH_ZLEN;
1339 +               else
1340 +                       return ret;
1341 +
1342 +               if (skb->len < len) {
1343 +                       ret = skb_pad(skb, len - skb->len);
1344 +                       if (ret < 0)
1345 +                               return ret;
1346 +                       skb->len = len;
1347 +                       skb_set_tail_pointer(skb, len);
1348 +               }
1349 +       }
1350 +
1351 +       return ret;
1352 +}
1353 +
1354 +static inline int fe_cal_txd_req(struct sk_buff *skb)
1355 +{
1356 +       int i, nfrags;
1357 +       struct skb_frag_struct *frag;
1358 +
1359 +       nfrags = 1;
1360 +       if (skb_is_gso(skb)) {
1361 +               for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1362 +                       frag = &skb_shinfo(skb)->frags[i];
1363 +                       nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
1364 +               }
1365 +       } else {
1366 +               nfrags += skb_shinfo(skb)->nr_frags;
1367 +       }
1368 +
1369 +       return DIV_ROUND_UP(nfrags, 2);
1370 +}
1371 +
1372 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
1373 +{
1374 +       struct fe_priv *priv = netdev_priv(dev);
1375 +       struct fe_tx_ring *ring = &priv->tx_ring;
1376 +       struct net_device_stats *stats = &dev->stats;
1377 +       int tx_num;
1378 +       int len = skb->len;
1379 +
1380 +       if (fe_skb_padto(skb, priv)) {
1381 +               netif_warn(priv, tx_err, dev, "tx padding failed!\n");
1382 +               return NETDEV_TX_OK;
1383 +       }
1384 +
1385 +       tx_num = fe_cal_txd_req(skb);
1386 +       if (unlikely(fe_empty_txd(ring) <= tx_num)) {
1387 +               netif_stop_queue(dev);
1388 +               netif_err(priv, tx_queued, dev,
1389 +                         "Tx Ring full when queue awake!\n");
1390 +               return NETDEV_TX_BUSY;
1391 +       }
1392 +
1393 +       if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
1394 +               stats->tx_dropped++;
1395 +       } else {
1396 +               stats->tx_packets++;
1397 +               stats->tx_bytes += len;
1398 +       }
1399 +
1400 +       return NETDEV_TX_OK;
1401 +}
1402 +
1403 +static inline void fe_rx_vlan(struct sk_buff *skb)
1404 +{
1405 +       struct ethhdr *ehdr;
1406 +       u16 vlanid;
1407 +
1408 +       if (!__vlan_get_tag(skb, &vlanid)) {
1409 +               /* pop the vlan tag */
1410 +               ehdr = (struct ethhdr *)skb->data;
1411 +               memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
1412 +               skb_pull(skb, VLAN_HLEN);
1413 +               __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
1414 +       }
1415 +}
1416 +
1417 +static int fe_poll_rx(struct napi_struct *napi, int budget,
1418 +                     struct fe_priv *priv, u32 rx_intr)
1419 +{
1420 +       struct net_device *netdev = priv->netdev;
1421 +       struct net_device_stats *stats = &netdev->stats;
1422 +       struct fe_soc_data *soc = priv->soc;
1423 +       struct fe_rx_ring *ring = &priv->rx_ring;
1424 +       int idx = ring->rx_calc_idx;
1425 +       u32 checksum_bit;
1426 +       struct sk_buff *skb;
1427 +       u8 *data, *new_data;
1428 +       struct fe_rx_dma *rxd, trxd;
1429 +       int done = 0, pad;
1430 +       bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
1431 +
1432 +       if (netdev->features & NETIF_F_RXCSUM)
1433 +               checksum_bit = soc->checksum_bit;
1434 +       else
1435 +               checksum_bit = 0;
1436 +
1437 +       if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1438 +               pad = 0;
1439 +       else
1440 +               pad = NET_IP_ALIGN;
1441 +
1442 +       while (done < budget) {
1443 +               unsigned int pktlen;
1444 +               dma_addr_t dma_addr;
1445 +
1446 +               idx = NEXT_RX_DESP_IDX(idx);
1447 +               rxd = &ring->rx_dma[idx];
1448 +               data = ring->rx_data[idx];
1449 +
1450 +               fe_get_rxd(&trxd, rxd);
1451 +               if (!(trxd.rxd2 & RX_DMA_DONE))
1452 +                       break;
1453 +
1454 +               /* alloc new buffer */
1455 +               new_data = netdev_alloc_frag(ring->frag_size);
1456 +               if (unlikely(!new_data)) {
1457 +                       stats->rx_dropped++;
1458 +                       goto release_desc;
1459 +               }
1460 +               dma_addr = dma_map_single(&netdev->dev,
1461 +                                         new_data + NET_SKB_PAD + pad,
1462 +                                         ring->rx_buf_size,
1463 +                                         DMA_FROM_DEVICE);
1464 +               if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
1465 +                       put_page(virt_to_head_page(new_data));
1466 +                       goto release_desc;
1467 +               }
1468 +
1469 +               /* receive data */
1470 +               skb = build_skb(data, ring->frag_size);
1471 +               if (unlikely(!skb)) {
1472 +                       put_page(virt_to_head_page(new_data));
1473 +                       goto release_desc;
1474 +               }
1475 +               skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1476 +
1477 +               dma_unmap_single(&netdev->dev, trxd.rxd1,
1478 +                                ring->rx_buf_size, DMA_FROM_DEVICE);
1479 +               pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1480 +               skb->dev = netdev;
1481 +               skb_put(skb, pktlen);
1482 +               if (trxd.rxd4 & checksum_bit)
1483 +                       skb->ip_summed = CHECKSUM_UNNECESSARY;
1484 +               else
1485 +                       skb_checksum_none_assert(skb);
1486 +               if (rx_vlan)
1487 +                       fe_rx_vlan(skb);
1488 +               skb->protocol = eth_type_trans(skb, netdev);
1489 +
1490 +               stats->rx_packets++;
1491 +               stats->rx_bytes += pktlen;
1492 +
1493 +               napi_gro_receive(napi, skb);
1494 +
1495 +               ring->rx_data[idx] = new_data;
1496 +               rxd->rxd1 = (unsigned int)dma_addr;
1497 +
1498 +release_desc:
1499 +               if (priv->flags & FE_FLAG_RX_SG_DMA)
1500 +                       rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
1501 +               else
1502 +                       rxd->rxd2 = RX_DMA_LSO;
1503 +
1504 +               ring->rx_calc_idx = idx;
1505 +               /* make sure that all changes to the dma ring are flushed before
1506 +                * we continue
1507 +                */
1508 +               wmb();
1509 +               fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
1510 +               done++;
1511 +       }
1512 +
1513 +       if (done < budget)
1514 +               fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
1515 +
1516 +       return done;
1517 +}
1518 +
1519 +static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
1520 +                     int *tx_again)
1521 +{
1522 +       struct net_device *netdev = priv->netdev;
1523 +       struct device *dev = &netdev->dev;
1524 +       unsigned int bytes_compl = 0;
1525 +       struct sk_buff *skb;
1526 +       struct fe_tx_buf *tx_buf;
1527 +       int done = 0;
1528 +       u32 idx, hwidx;
1529 +       struct fe_tx_ring *ring = &priv->tx_ring;
1530 +
1531 +       idx = ring->tx_free_idx;
1532 +       hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
1533 +
1534 +       while ((idx != hwidx) && budget) {
1535 +               tx_buf = &ring->tx_buf[idx];
1536 +               skb = tx_buf->skb;
1537 +
1538 +               if (!skb)
1539 +                       break;
1540 +
1541 +               if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
1542 +                       bytes_compl += skb->len;
1543 +                       done++;
1544 +                       budget--;
1545 +               }
1546 +               fe_txd_unmap(dev, tx_buf);
1547 +               idx = NEXT_TX_DESP_IDX(idx);
1548 +       }
1549 +       ring->tx_free_idx = idx;
1550 +
1551 +       if (idx == hwidx) {
1552 +               /* read hw index again make sure no new tx packet */
1553 +               hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
1554 +               if (idx == hwidx)
1555 +                       fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
1556 +               else
1557 +                       *tx_again = 1;
1558 +       } else {
1559 +               *tx_again = 1;
1560 +       }
1561 +
1562 +       if (done) {
1563 +               netdev_completed_queue(netdev, done, bytes_compl);
1564 +               smp_mb();
1565 +               if (unlikely(netif_queue_stopped(netdev) &&
1566 +                            (fe_empty_txd(ring) > ring->tx_thresh)))
1567 +                       netif_wake_queue(netdev);
1568 +       }
1569 +
1570 +       return done;
1571 +}
1572 +
1573 +static int fe_poll(struct napi_struct *napi, int budget)
1574 +{
1575 +       struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
1576 +       struct fe_hw_stats *hwstat = priv->hw_stats;
1577 +       int tx_done, rx_done, tx_again;
1578 +       u32 status, fe_status, status_reg, mask;
1579 +       u32 tx_intr, rx_intr, status_intr;
1580 +
1581 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1582 +       fe_status = status;
1583 +       tx_intr = priv->soc->tx_int;
1584 +       rx_intr = priv->soc->rx_int;
1585 +       status_intr = priv->soc->status_int;
1586 +       tx_done = 0;
1587 +       rx_done = 0;
1588 +       tx_again = 0;
1589 +
1590 +       if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
1591 +               fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
1592 +               status_reg = FE_REG_FE_INT_STATUS2;
1593 +       } else {
1594 +               status_reg = FE_REG_FE_INT_STATUS;
1595 +       }
1596 +
1597 +       if (status & tx_intr)
1598 +               tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
1599 +
1600 +       if (status & rx_intr)
1601 +               rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1602 +
1603 +       if (unlikely(fe_status & status_intr)) {
1604 +               if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1605 +                       fe_stats_update(priv);
1606 +                       spin_unlock(&hwstat->stats_lock);
1607 +               }
1608 +               fe_reg_w32(status_intr, status_reg);
1609 +       }
1610 +
1611 +       if (unlikely(netif_msg_intr(priv))) {
1612 +               mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1613 +               netdev_info(priv->netdev,
1614 +                           "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1615 +                           tx_done, rx_done, status, mask);
1616 +       }
1617 +
1618 +       if (!tx_again && (rx_done < budget)) {
1619 +               status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1620 +               if (status & (tx_intr | rx_intr)) {
1621 +                       /* let napi poll again */
1622 +                       rx_done = budget;
1623 +                       goto poll_again;
1624 +               }
1625 +
1626 +               napi_complete(napi);
1627 +               fe_int_enable(tx_intr | rx_intr);
1628 +       } else {
1629 +               rx_done = budget;
1630 +       }
1631 +
1632 +poll_again:
1633 +       return rx_done;
1634 +}
1635 +
1636 +static void fe_tx_timeout(struct net_device *dev)
1637 +{
1638 +       struct fe_priv *priv = netdev_priv(dev);
1639 +       struct fe_tx_ring *ring = &priv->tx_ring;
1640 +
1641 +       priv->netdev->stats.tx_errors++;
1642 +       netif_err(priv, tx_err, dev,
1643 +                 "transmit timed out\n");
1644 +       netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1645 +                  fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1646 +       netif_info(priv, drv, dev, "tx_ring=%d, "
1647 +                  "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1648 +                  0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1649 +                  fe_reg_r32(FE_REG_TX_MAX_CNT0),
1650 +                  fe_reg_r32(FE_REG_TX_CTX_IDX0),
1651 +                  fe_reg_r32(FE_REG_TX_DTX_IDX0),
1652 +                  ring->tx_free_idx,
1653 +                  ring->tx_next_idx);
1654 +       netif_info(priv, drv, dev,
1655 +                  "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1656 +                  0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1657 +                  fe_reg_r32(FE_REG_RX_MAX_CNT0),
1658 +                  fe_reg_r32(FE_REG_RX_CALC_IDX0),
1659 +                  fe_reg_r32(FE_REG_RX_DRX_IDX0));
1660 +
1661 +       if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1662 +               schedule_work(&priv->pending_work);
1663 +}
1664 +
1665 +static irqreturn_t fe_handle_irq(int irq, void *dev)
1666 +{
1667 +       struct fe_priv *priv = netdev_priv(dev);
1668 +       u32 status, int_mask;
1669 +
1670 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1671 +
1672 +       if (unlikely(!status))
1673 +               return IRQ_NONE;
1674 +
1675 +       int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1676 +       if (likely(status & int_mask)) {
1677 +               if (likely(napi_schedule_prep(&priv->rx_napi))) {
1678 +                       fe_int_disable(int_mask);
1679 +                       __napi_schedule(&priv->rx_napi);
1680 +               }
1681 +       } else {
1682 +               fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1683 +       }
1684 +
1685 +       return IRQ_HANDLED;
1686 +}
1687 +
1688 +#ifdef CONFIG_NET_POLL_CONTROLLER
1689 +static void fe_poll_controller(struct net_device *dev)
1690 +{
1691 +       struct fe_priv *priv = netdev_priv(dev);
1692 +       u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1693 +
1694 +       fe_int_disable(int_mask);
1695 +       fe_handle_irq(dev->irq, dev);
1696 +       fe_int_enable(int_mask);
1697 +}
1698 +#endif
1699 +
1700 +int fe_set_clock_cycle(struct fe_priv *priv)
1701 +{
1702 +       unsigned long sysclk = priv->sysclk;
1703 +
1704 +       sysclk /= FE_US_CYC_CNT_DIVISOR;
1705 +       sysclk <<= FE_US_CYC_CNT_SHIFT;
1706 +
1707 +       fe_w32((fe_r32(FE_FE_GLO_CFG) &
1708 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1709 +                       sysclk,
1710 +                       FE_FE_GLO_CFG);
1711 +       return 0;
1712 +}
1713 +
1714 +void fe_fwd_config(struct fe_priv *priv)
1715 +{
1716 +       u32 fwd_cfg;
1717 +
1718 +       fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1719 +
1720 +       /* disable jumbo frame */
1721 +       if (priv->flags & FE_FLAG_JUMBO_FRAME)
1722 +               fwd_cfg &= ~FE_GDM1_JMB_EN;
1723 +
1724 +       /* set unicast/multicast/broadcast frame to cpu */
1725 +       fwd_cfg &= ~0xffff;
1726 +
1727 +       fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1728 +}
1729 +
1730 +static void fe_rxcsum_config(bool enable)
1731 +{
1732 +       if (enable)
1733 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1734 +                                       FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1735 +                               FE_GDMA1_FWD_CFG);
1736 +       else
1737 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1738 +                                       FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1739 +                               FE_GDMA1_FWD_CFG);
1740 +}
1741 +
1742 +static void fe_txcsum_config(bool enable)
1743 +{
1744 +       if (enable)
1745 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1746 +                                       FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1747 +                               FE_CDMA_CSG_CFG);
1748 +       else
1749 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1750 +                                       FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1751 +                               FE_CDMA_CSG_CFG);
1752 +}
1753 +
1754 +void fe_csum_config(struct fe_priv *priv)
1755 +{
1756 +       struct net_device *dev = priv_netdev(priv);
1757 +
1758 +       fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1759 +       fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1760 +}
1761 +
1762 +static int fe_hw_init(struct net_device *dev)
1763 +{
1764 +       struct fe_priv *priv = netdev_priv(dev);
1765 +       int i, err;
1766 +
1767 +       err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1768 +                              dev_name(priv->device), dev);
1769 +       if (err)
1770 +               return err;
1771 +
1772 +       if (priv->soc->set_mac)
1773 +               priv->soc->set_mac(priv, dev->dev_addr);
1774 +       else
1775 +               fe_hw_set_macaddr(priv, dev->dev_addr);
1776 +
1777 +       /* disable delay interrupt */
1778 +       fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1779 +
1780 +       fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1781 +
1782 +       /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1783 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1784 +               for (i = 0; i < 16; i += 2)
1785 +                       fe_w32(((i + 1) << 16) + i,
1786 +                              fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1787 +                              (i * 2));
1788 +
1789 +       if (priv->soc->fwd_config(priv))
1790 +               netdev_err(dev, "unable to get clock\n");
1791 +
1792 +       if (fe_reg_table[FE_REG_FE_RST_GL]) {
1793 +               fe_reg_w32(1, FE_REG_FE_RST_GL);
1794 +               fe_reg_w32(0, FE_REG_FE_RST_GL);
1795 +       }
1796 +
1797 +       return 0;
1798 +}
1799 +
1800 +static int fe_open(struct net_device *dev)
1801 +{
1802 +       struct fe_priv *priv = netdev_priv(dev);
1803 +       unsigned long flags;
1804 +       u32 val;
1805 +       int err;
1806 +
1807 +       err = fe_init_dma(priv);
1808 +       if (err) {
1809 +               fe_free_dma(priv);
1810 +               return err;
1811 +       }
1812 +
1813 +       spin_lock_irqsave(&priv->page_lock, flags);
1814 +
1815 +       val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1816 +       if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1817 +               val |= FE_RX_2B_OFFSET;
1818 +       val |= priv->soc->pdma_glo_cfg;
1819 +       fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1820 +
1821 +       spin_unlock_irqrestore(&priv->page_lock, flags);
1822 +
1823 +       if (priv->phy)
1824 +               priv->phy->start(priv);
1825 +
1826 +       if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1827 +               netif_carrier_on(dev);
1828 +
1829 +       napi_enable(&priv->rx_napi);
1830 +       fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1831 +       netif_start_queue(dev);
1832 +
1833 +       return 0;
1834 +}
1835 +
1836 +static int fe_stop(struct net_device *dev)
1837 +{
1838 +       struct fe_priv *priv = netdev_priv(dev);
1839 +       unsigned long flags;
1840 +       int i;
1841 +
1842 +       netif_tx_disable(dev);
1843 +       fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1844 +       napi_disable(&priv->rx_napi);
1845 +
1846 +       if (priv->phy)
1847 +               priv->phy->stop(priv);
1848 +
1849 +       spin_lock_irqsave(&priv->page_lock, flags);
1850 +
1851 +       fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1852 +                    ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1853 +                    FE_REG_PDMA_GLO_CFG);
1854 +       spin_unlock_irqrestore(&priv->page_lock, flags);
1855 +
1856 +       /* wait dma stop */
1857 +       for (i = 0; i < 10; i++) {
1858 +               if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1859 +                               (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1860 +                       msleep(20);
1861 +                       continue;
1862 +               }
1863 +               break;
1864 +       }
1865 +
1866 +       fe_free_dma(priv);
1867 +
1868 +       return 0;
1869 +}
1870 +
1871 +static int __init fe_init(struct net_device *dev)
1872 +{
1873 +       struct fe_priv *priv = netdev_priv(dev);
1874 +       struct device_node *port;
1875 +       const char *mac_addr;
1876 +       int err;
1877 +
1878 +       priv->soc->reset_fe();
1879 +
1880 +       if (priv->soc->switch_init)
1881 +               if (priv->soc->switch_init(priv)) {
1882 +                       netdev_err(dev, "failed to initialize switch core\n");
1883 +                       return -ENODEV;
1884 +               }
1885 +
1886 +       mac_addr = of_get_mac_address(priv->device->of_node);
1887 +       if (mac_addr)
1888 +               ether_addr_copy(dev->dev_addr, mac_addr);
1889 +
1890 +       /* If the mac address is invalid, use random mac address  */
1891 +       if (!is_valid_ether_addr(dev->dev_addr)) {
1892 +               random_ether_addr(dev->dev_addr);
1893 +               dev_err(priv->device, "generated random MAC address %pM\n",
1894 +                       dev->dev_addr);
1895 +       }
1896 +
1897 +       err = fe_mdio_init(priv);
1898 +       if (err)
1899 +               return err;
1900 +
1901 +       if (priv->soc->port_init)
1902 +               for_each_child_of_node(priv->device->of_node, port)
1903 +                       if (of_device_is_compatible(port, "mediatek,eth-port") &&
1904 +                           of_device_is_available(port))
1905 +                               priv->soc->port_init(priv, port);
1906 +
1907 +       if (priv->phy) {
1908 +               err = priv->phy->connect(priv);
1909 +               if (err)
1910 +                       goto err_phy_disconnect;
1911 +       }
1912 +
1913 +       err = fe_hw_init(dev);
1914 +       if (!err)
1915 +               return 0;
1916 +
1917 +err_phy_disconnect:
1918 +       if (priv->phy)
1919 +               priv->phy->disconnect(priv);
1920 +       fe_mdio_cleanup(priv);
1921 +
1922 +       return err;
1923 +}
1924 +
1925 +static void fe_uninit(struct net_device *dev)
1926 +{
1927 +       struct fe_priv *priv = netdev_priv(dev);
1928 +
1929 +       if (priv->phy)
1930 +               priv->phy->disconnect(priv);
1931 +       fe_mdio_cleanup(priv);
1932 +
1933 +       fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1934 +       free_irq(dev->irq, dev);
1935 +}
1936 +
1937 +static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1938 +{
1939 +       struct fe_priv *priv = netdev_priv(dev);
1940 +
1941 +       if (!priv->phy_dev)
1942 +               return -ENODEV;
1943 +
1944 +       switch (cmd) {
1945 +       case SIOCGMIIPHY:
1946 +       case SIOCGMIIREG:
1947 +       case SIOCSMIIREG:
1948 +               return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1949 +       default:
1950 +               break;
1951 +       }
1952 +
1953 +       return -EOPNOTSUPP;
1954 +}
1955 +
1956 +static int fe_change_mtu(struct net_device *dev, int new_mtu)
1957 +{
1958 +       struct fe_priv *priv = netdev_priv(dev);
1959 +       int frag_size, old_mtu;
1960 +       u32 fwd_cfg;
1961 +
1962 +       if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1963 +               return eth_change_mtu(dev, new_mtu);
1964 +
1965 +       frag_size = fe_max_frag_size(new_mtu);
1966 +       if (new_mtu < 68 || frag_size > PAGE_SIZE)
1967 +               return -EINVAL;
1968 +
1969 +       old_mtu = dev->mtu;
1970 +       dev->mtu = new_mtu;
1971 +
1972 +       /* return early if the buffer sizes will not change */
1973 +       if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1974 +               return 0;
1975 +       if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1976 +               return 0;
1977 +
1978 +       if (new_mtu <= ETH_DATA_LEN)
1979 +               priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1980 +       else
1981 +               priv->rx_ring.frag_size = PAGE_SIZE;
1982 +       priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1983 +
1984 +       if (!netif_running(dev))
1985 +               return 0;
1986 +
1987 +       fe_stop(dev);
1988 +       fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1989 +       if (new_mtu <= ETH_DATA_LEN) {
1990 +               fwd_cfg &= ~FE_GDM1_JMB_EN;
1991 +       } else {
1992 +               fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1993 +               fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1994 +                               FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1995 +       }
1996 +       fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1997 +
1998 +       return fe_open(dev);
1999 +}
2000 +
2001 +static const struct net_device_ops fe_netdev_ops = {
2002 +       .ndo_init               = fe_init,
2003 +       .ndo_uninit             = fe_uninit,
2004 +       .ndo_open               = fe_open,
2005 +       .ndo_stop               = fe_stop,
2006 +       .ndo_start_xmit         = fe_start_xmit,
2007 +       .ndo_set_mac_address    = fe_set_mac_address,
2008 +       .ndo_validate_addr      = eth_validate_addr,
2009 +       .ndo_do_ioctl           = fe_do_ioctl,
2010 +       .ndo_change_mtu         = fe_change_mtu,
2011 +       .ndo_tx_timeout         = fe_tx_timeout,
2012 +       .ndo_get_stats64        = fe_get_stats64,
2013 +       .ndo_vlan_rx_add_vid    = fe_vlan_rx_add_vid,
2014 +       .ndo_vlan_rx_kill_vid   = fe_vlan_rx_kill_vid,
2015 +#ifdef CONFIG_NET_POLL_CONTROLLER
2016 +       .ndo_poll_controller    = fe_poll_controller,
2017 +#endif
2018 +};
2019 +
2020 +static void fe_reset_pending(struct fe_priv *priv)
2021 +{
2022 +       struct net_device *dev = priv->netdev;
2023 +       int err;
2024 +
2025 +       rtnl_lock();
2026 +       fe_stop(dev);
2027 +
2028 +       err = fe_open(dev);
2029 +       if (err) {
2030 +               netif_alert(priv, ifup, dev,
2031 +                           "Driver up/down cycle failed, closing device.\n");
2032 +               dev_close(dev);
2033 +       }
2034 +       rtnl_unlock();
2035 +}
2036 +
2037 +static const struct fe_work_t fe_work[] = {
2038 +       {FE_FLAG_RESET_PENDING, fe_reset_pending},
2039 +};
2040 +
2041 +static void fe_pending_work(struct work_struct *work)
2042 +{
2043 +       struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
2044 +       int i;
2045 +       bool pending;
2046 +
2047 +       for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
2048 +               pending = test_and_clear_bit(fe_work[i].bitnr,
2049 +                                            priv->pending_flags);
2050 +               if (pending)
2051 +                       fe_work[i].action(priv);
2052 +       }
2053 +}
2054 +
2055 +static int fe_probe(struct platform_device *pdev)
2056 +{
2057 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2058 +       const struct of_device_id *match;
2059 +       struct fe_soc_data *soc;
2060 +       struct net_device *netdev;
2061 +       struct fe_priv *priv;
2062 +       struct clk *sysclk;
2063 +       int err, napi_weight;
2064 +
2065 +       device_reset(&pdev->dev);
2066 +
2067 +       match = of_match_device(of_fe_match, &pdev->dev);
2068 +       soc = (struct fe_soc_data *)match->data;
2069 +
2070 +       if (soc->reg_table)
2071 +               fe_reg_table = soc->reg_table;
2072 +       else
2073 +               soc->reg_table = fe_reg_table;
2074 +
2075 +       fe_base = devm_ioremap_resource(&pdev->dev, res);
2076 +       if (!fe_base) {
2077 +               err = -EADDRNOTAVAIL;
2078 +               goto err_out;
2079 +       }
2080 +
2081 +       netdev = alloc_etherdev(sizeof(*priv));
2082 +       if (!netdev) {
2083 +               dev_err(&pdev->dev, "alloc_etherdev failed\n");
2084 +               err = -ENOMEM;
2085 +               goto err_iounmap;
2086 +       }
2087 +
2088 +       SET_NETDEV_DEV(netdev, &pdev->dev);
2089 +       netdev->netdev_ops = &fe_netdev_ops;
2090 +       netdev->base_addr = (unsigned long)fe_base;
2091 +
2092 +       netdev->irq = platform_get_irq(pdev, 0);
2093 +       if (netdev->irq < 0) {
2094 +               dev_err(&pdev->dev, "no IRQ resource found\n");
2095 +               err = -ENXIO;
2096 +               goto err_free_dev;
2097 +       }
2098 +
2099 +       if (soc->init_data)
2100 +               soc->init_data(soc, netdev);
2101 +       /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
2102 +       netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2103 +       netdev->vlan_features = netdev->hw_features &
2104 +               ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2105 +       netdev->features |= netdev->hw_features;
2106 +
2107 +       /* fake rx vlan filter func. to support tx vlan offload func */
2108 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
2109 +               netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2110 +
2111 +       priv = netdev_priv(netdev);
2112 +       spin_lock_init(&priv->page_lock);
2113 +       if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
2114 +               priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
2115 +               if (!priv->hw_stats) {
2116 +                       err = -ENOMEM;
2117 +                       goto err_free_dev;
2118 +               }
2119 +               spin_lock_init(&priv->hw_stats->stats_lock);
2120 +       }
2121 +
2122 +       sysclk = devm_clk_get(&pdev->dev, NULL);
2123 +       if (!IS_ERR(sysclk)) {
2124 +               priv->sysclk = clk_get_rate(sysclk);
2125 +       } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
2126 +               dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
2127 +               err = -ENXIO;
2128 +               goto err_free_dev;
2129 +       }
2130 +
2131 +       priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
2132 +       if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
2133 +               dev_err(&pdev->dev, "failed to read switch phandle\n");
2134 +               err = -ENODEV;
2135 +               goto err_free_dev;
2136 +       }
2137 +
2138 +       priv->netdev = netdev;
2139 +       priv->device = &pdev->dev;
2140 +       priv->soc = soc;
2141 +       priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
2142 +       priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
2143 +       priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
2144 +       priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
2145 +       priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
2146 +       INIT_WORK(&priv->pending_work, fe_pending_work);
2147 +
2148 +       napi_weight = 32;
2149 +       if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
2150 +               napi_weight *= 4;
2151 +               priv->tx_ring.tx_ring_size *= 4;
2152 +               priv->rx_ring.rx_ring_size *= 4;
2153 +       }
2154 +       netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
2155 +       fe_set_ethtool_ops(netdev);
2156 +
2157 +       err = register_netdev(netdev);
2158 +       if (err) {
2159 +               dev_err(&pdev->dev, "error bringing up device\n");
2160 +               goto err_free_dev;
2161 +       }
2162 +
2163 +       platform_set_drvdata(pdev, netdev);
2164 +
2165 +       netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
2166 +                  netdev->base_addr, netdev->irq);
2167 +
2168 +       return 0;
2169 +
2170 +err_free_dev:
2171 +       free_netdev(netdev);
2172 +err_iounmap:
2173 +       devm_iounmap(&pdev->dev, fe_base);
2174 +err_out:
2175 +       return err;
2176 +}
2177 +
2178 +static int fe_remove(struct platform_device *pdev)
2179 +{
2180 +       struct net_device *dev = platform_get_drvdata(pdev);
2181 +       struct fe_priv *priv = netdev_priv(dev);
2182 +
2183 +       netif_napi_del(&priv->rx_napi);
2184 +       kfree(priv->hw_stats);
2185 +
2186 +       cancel_work_sync(&priv->pending_work);
2187 +
2188 +       unregister_netdev(dev);
2189 +       free_netdev(dev);
2190 +       platform_set_drvdata(pdev, NULL);
2191 +
2192 +       return 0;
2193 +}
2194 +
2195 +static struct platform_driver fe_driver = {
2196 +       .probe = fe_probe,
2197 +       .remove = fe_remove,
2198 +       .driver = {
2199 +               .name = "mtk_soc_eth",
2200 +               .owner = THIS_MODULE,
2201 +               .of_match_table = of_fe_match,
2202 +       },
2203 +};
2204 +
2205 +module_platform_driver(fe_driver);
2206 +
2207 +MODULE_LICENSE("GPL");
2208 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2209 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
2210 +MODULE_VERSION(MTK_FE_DRV_VERSION);
2211 --- /dev/null
2212 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
2213 @@ -0,0 +1,522 @@
2214 +/*   This program is free software; you can redistribute it and/or modify
2215 + *   it under the terms of the GNU General Public License as published by
2216 + *   the Free Software Foundation; version 2 of the License
2217 + *
2218 + *   This program is distributed in the hope that it will be useful,
2219 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2220 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2221 + *   GNU General Public License for more details.
2222 + *
2223 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
2224 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
2225 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
2226 + */
2227 +
2228 +#ifndef FE_ETH_H
2229 +#define FE_ETH_H
2230 +
2231 +#include <linux/mii.h>
2232 +#include <linux/interrupt.h>
2233 +#include <linux/netdevice.h>
2234 +#include <linux/dma-mapping.h>
2235 +#include <linux/phy.h>
2236 +#include <linux/ethtool.h>
2237 +#include <linux/version.h>
2238 +
2239 +enum fe_reg {
2240 +       FE_REG_PDMA_GLO_CFG = 0,
2241 +       FE_REG_PDMA_RST_CFG,
2242 +       FE_REG_DLY_INT_CFG,
2243 +       FE_REG_TX_BASE_PTR0,
2244 +       FE_REG_TX_MAX_CNT0,
2245 +       FE_REG_TX_CTX_IDX0,
2246 +       FE_REG_TX_DTX_IDX0,
2247 +       FE_REG_RX_BASE_PTR0,
2248 +       FE_REG_RX_MAX_CNT0,
2249 +       FE_REG_RX_CALC_IDX0,
2250 +       FE_REG_RX_DRX_IDX0,
2251 +       FE_REG_FE_INT_ENABLE,
2252 +       FE_REG_FE_INT_STATUS,
2253 +       FE_REG_FE_DMA_VID_BASE,
2254 +       FE_REG_FE_COUNTER_BASE,
2255 +       FE_REG_FE_RST_GL,
2256 +       FE_REG_FE_INT_STATUS2,
2257 +       FE_REG_COUNT
2258 +};
2259 +
2260 +enum fe_work_flag {
2261 +       FE_FLAG_RESET_PENDING,
2262 +       FE_FLAG_MAX
2263 +};
2264 +
2265 +#define MTK_FE_DRV_VERSION             "0.1.2"
2266 +
2267 +/* power of 2 to let NEXT_TX_DESP_IDX work */
2268 +#define NUM_DMA_DESC           BIT(7)
2269 +#define MAX_DMA_DESC           0xfff
2270 +
2271 +#define FE_DELAY_EN_INT                0x80
2272 +#define FE_DELAY_MAX_INT       0x04
2273 +#define FE_DELAY_MAX_TOUT      0x04
2274 +#define FE_DELAY_TIME          20
2275 +#define FE_DELAY_CHAN          (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \
2276 +                                FE_DELAY_MAX_TOUT)
2277 +#define FE_DELAY_INIT          ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
2278 +#define FE_PSE_FQFC_CFG_INIT   0x80504000
2279 +#define FE_PSE_FQFC_CFG_256Q   0xff908000
2280 +
2281 +/* interrupt bits */
2282 +#define FE_CNT_PPE_AF          BIT(31)
2283 +#define FE_CNT_GDM_AF          BIT(29)
2284 +#define FE_PSE_P2_FC           BIT(26)
2285 +#define FE_PSE_BUF_DROP                BIT(24)
2286 +#define FE_GDM_OTHER_DROP      BIT(23)
2287 +#define FE_PSE_P1_FC           BIT(22)
2288 +#define FE_PSE_P0_FC           BIT(21)
2289 +#define FE_PSE_FQ_EMPTY                BIT(20)
2290 +#define FE_GE1_STA_CHG         BIT(18)
2291 +#define FE_TX_COHERENT         BIT(17)
2292 +#define FE_RX_COHERENT         BIT(16)
2293 +#define FE_TX_DONE_INT3                BIT(11)
2294 +#define FE_TX_DONE_INT2                BIT(10)
2295 +#define FE_TX_DONE_INT1                BIT(9)
2296 +#define FE_TX_DONE_INT0                BIT(8)
2297 +#define FE_RX_DONE_INT0                BIT(2)
2298 +#define FE_TX_DLY_INT          BIT(1)
2299 +#define FE_RX_DLY_INT          BIT(0)
2300 +
2301 +#define FE_RX_DONE_INT         FE_RX_DONE_INT0
2302 +#define FE_TX_DONE_INT         (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
2303 +                                FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
2304 +
2305 +#define RT5350_RX_DLY_INT      BIT(30)
2306 +#define RT5350_TX_DLY_INT      BIT(28)
2307 +#define RT5350_RX_DONE_INT1    BIT(17)
2308 +#define RT5350_RX_DONE_INT0    BIT(16)
2309 +#define RT5350_TX_DONE_INT3    BIT(3)
2310 +#define RT5350_TX_DONE_INT2    BIT(2)
2311 +#define RT5350_TX_DONE_INT1    BIT(1)
2312 +#define RT5350_TX_DONE_INT0    BIT(0)
2313 +
2314 +#define RT5350_RX_DONE_INT     (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
2315 +#define RT5350_TX_DONE_INT     (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
2316 +                                RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
2317 +
2318 +/* registers */
2319 +#define FE_FE_OFFSET           0x0000
2320 +#define FE_GDMA_OFFSET         0x0020
2321 +#define FE_PSE_OFFSET          0x0040
2322 +#define FE_GDMA2_OFFSET                0x0060
2323 +#define FE_CDMA_OFFSET         0x0080
2324 +#define FE_DMA_VID0            0x00a8
2325 +#define FE_PDMA_OFFSET         0x0100
2326 +#define FE_PPE_OFFSET          0x0200
2327 +#define FE_CMTABLE_OFFSET      0x0400
2328 +#define FE_POLICYTABLE_OFFSET  0x1000
2329 +
2330 +#define RT5350_PDMA_OFFSET     0x0800
2331 +#define RT5350_SDM_OFFSET      0x0c00
2332 +
2333 +#define FE_MDIO_ACCESS         (FE_FE_OFFSET + 0x00)
2334 +#define FE_MDIO_CFG            (FE_FE_OFFSET + 0x04)
2335 +#define FE_FE_GLO_CFG          (FE_FE_OFFSET + 0x08)
2336 +#define FE_FE_RST_GL           (FE_FE_OFFSET + 0x0C)
2337 +#define FE_FE_INT_STATUS       (FE_FE_OFFSET + 0x10)
2338 +#define FE_FE_INT_ENABLE       (FE_FE_OFFSET + 0x14)
2339 +#define FE_MDIO_CFG2           (FE_FE_OFFSET + 0x18)
2340 +#define FE_FOC_TS_T            (FE_FE_OFFSET + 0x1C)
2341 +
2342 +#define        FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
2343 +#define FE_GDMA1_SCH_CFG       (FE_GDMA_OFFSET + 0x04)
2344 +#define FE_GDMA1_SHPR_CFG      (FE_GDMA_OFFSET + 0x08)
2345 +#define FE_GDMA1_MAC_ADRL      (FE_GDMA_OFFSET + 0x0C)
2346 +#define FE_GDMA1_MAC_ADRH      (FE_GDMA_OFFSET + 0x10)
2347 +
2348 +#define        FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
2349 +#define FE_GDMA2_SCH_CFG       (FE_GDMA2_OFFSET + 0x04)
2350 +#define FE_GDMA2_SHPR_CFG      (FE_GDMA2_OFFSET + 0x08)
2351 +#define FE_GDMA2_MAC_ADRL      (FE_GDMA2_OFFSET + 0x0C)
2352 +#define FE_GDMA2_MAC_ADRH      (FE_GDMA2_OFFSET + 0x10)
2353 +
2354 +#define FE_PSE_FQ_CFG          (FE_PSE_OFFSET + 0x00)
2355 +#define FE_CDMA_FC_CFG         (FE_PSE_OFFSET + 0x04)
2356 +#define FE_GDMA1_FC_CFG                (FE_PSE_OFFSET + 0x08)
2357 +#define FE_GDMA2_FC_CFG                (FE_PSE_OFFSET + 0x0C)
2358 +
2359 +#define FE_CDMA_CSG_CFG                (FE_CDMA_OFFSET + 0x00)
2360 +#define FE_CDMA_SCH_CFG                (FE_CDMA_OFFSET + 0x04)
2361 +
2362 +#ifdef CONFIG_SOC_MT7621
2363 +#define MT7620A_GDMA_OFFSET            0x0500
2364 +#else
2365 +#define MT7620A_GDMA_OFFSET            0x0600
2366 +#endif
2367 +#define        MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
2368 +#define MT7620A_FE_GDMA1_SCH_CFG       (MT7620A_GDMA_OFFSET + 0x04)
2369 +#define MT7620A_FE_GDMA1_SHPR_CFG      (MT7620A_GDMA_OFFSET + 0x08)
2370 +#define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
2371 +#define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
2372 +
2373 +#define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
2374 +#define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
2375 +#define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)
2376 +#define RT5350_TX_DTX_IDX0     (RT5350_PDMA_OFFSET + 0x0C)
2377 +#define RT5350_TX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x10)
2378 +#define RT5350_TX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x14)
2379 +#define RT5350_TX_CTX_IDX1     (RT5350_PDMA_OFFSET + 0x18)
2380 +#define RT5350_TX_DTX_IDX1     (RT5350_PDMA_OFFSET + 0x1C)
2381 +#define RT5350_TX_BASE_PTR2    (RT5350_PDMA_OFFSET + 0x20)
2382 +#define RT5350_TX_MAX_CNT2     (RT5350_PDMA_OFFSET + 0x24)
2383 +#define RT5350_TX_CTX_IDX2     (RT5350_PDMA_OFFSET + 0x28)
2384 +#define RT5350_TX_DTX_IDX2     (RT5350_PDMA_OFFSET + 0x2C)
2385 +#define RT5350_TX_BASE_PTR3    (RT5350_PDMA_OFFSET + 0x30)
2386 +#define RT5350_TX_MAX_CNT3     (RT5350_PDMA_OFFSET + 0x34)
2387 +#define RT5350_TX_CTX_IDX3     (RT5350_PDMA_OFFSET + 0x38)
2388 +#define RT5350_TX_DTX_IDX3     (RT5350_PDMA_OFFSET + 0x3C)
2389 +#define RT5350_RX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x100)
2390 +#define RT5350_RX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x104)
2391 +#define RT5350_RX_CALC_IDX0    (RT5350_PDMA_OFFSET + 0x108)
2392 +#define RT5350_RX_DRX_IDX0     (RT5350_PDMA_OFFSET + 0x10C)
2393 +#define RT5350_RX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x110)
2394 +#define RT5350_RX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x114)
2395 +#define RT5350_RX_CALC_IDX1    (RT5350_PDMA_OFFSET + 0x118)
2396 +#define RT5350_RX_DRX_IDX1     (RT5350_PDMA_OFFSET + 0x11C)
2397 +#define RT5350_PDMA_GLO_CFG    (RT5350_PDMA_OFFSET + 0x204)
2398 +#define RT5350_PDMA_RST_CFG    (RT5350_PDMA_OFFSET + 0x208)
2399 +#define RT5350_DLY_INT_CFG     (RT5350_PDMA_OFFSET + 0x20c)
2400 +#define RT5350_FE_INT_STATUS   (RT5350_PDMA_OFFSET + 0x220)
2401 +#define RT5350_FE_INT_ENABLE   (RT5350_PDMA_OFFSET + 0x228)
2402 +#define RT5350_PDMA_SCH_CFG    (RT5350_PDMA_OFFSET + 0x280)
2403 +
2404 +#define FE_PDMA_GLO_CFG                (FE_PDMA_OFFSET + 0x00)
2405 +#define FE_PDMA_RST_CFG                (FE_PDMA_OFFSET + 0x04)
2406 +#define FE_PDMA_SCH_CFG                (FE_PDMA_OFFSET + 0x08)
2407 +#define FE_DLY_INT_CFG         (FE_PDMA_OFFSET + 0x0C)
2408 +#define FE_TX_BASE_PTR0                (FE_PDMA_OFFSET + 0x10)
2409 +#define FE_TX_MAX_CNT0         (FE_PDMA_OFFSET + 0x14)
2410 +#define FE_TX_CTX_IDX0         (FE_PDMA_OFFSET + 0x18)
2411 +#define FE_TX_DTX_IDX0         (FE_PDMA_OFFSET + 0x1C)
2412 +#define FE_TX_BASE_PTR1                (FE_PDMA_OFFSET + 0x20)
2413 +#define FE_TX_MAX_CNT1         (FE_PDMA_OFFSET + 0x24)
2414 +#define FE_TX_CTX_IDX1         (FE_PDMA_OFFSET + 0x28)
2415 +#define FE_TX_DTX_IDX1         (FE_PDMA_OFFSET + 0x2C)
2416 +#define FE_RX_BASE_PTR0                (FE_PDMA_OFFSET + 0x30)
2417 +#define FE_RX_MAX_CNT0         (FE_PDMA_OFFSET + 0x34)
2418 +#define FE_RX_CALC_IDX0                (FE_PDMA_OFFSET + 0x38)
2419 +#define FE_RX_DRX_IDX0         (FE_PDMA_OFFSET + 0x3C)
2420 +#define FE_TX_BASE_PTR2                (FE_PDMA_OFFSET + 0x40)
2421 +#define FE_TX_MAX_CNT2         (FE_PDMA_OFFSET + 0x44)
2422 +#define FE_TX_CTX_IDX2         (FE_PDMA_OFFSET + 0x48)
2423 +#define FE_TX_DTX_IDX2         (FE_PDMA_OFFSET + 0x4C)
2424 +#define FE_TX_BASE_PTR3                (FE_PDMA_OFFSET + 0x50)
2425 +#define FE_TX_MAX_CNT3         (FE_PDMA_OFFSET + 0x54)
2426 +#define FE_TX_CTX_IDX3         (FE_PDMA_OFFSET + 0x58)
2427 +#define FE_TX_DTX_IDX3         (FE_PDMA_OFFSET + 0x5C)
2428 +#define FE_RX_BASE_PTR1                (FE_PDMA_OFFSET + 0x60)
2429 +#define FE_RX_MAX_CNT1         (FE_PDMA_OFFSET + 0x64)
2430 +#define FE_RX_CALC_IDX1                (FE_PDMA_OFFSET + 0x68)
2431 +#define FE_RX_DRX_IDX1         (FE_PDMA_OFFSET + 0x6C)
2432 +
2433 +/* Switch DMA configuration */
2434 +#define RT5350_SDM_CFG         (RT5350_SDM_OFFSET + 0x00)
2435 +#define RT5350_SDM_RRING       (RT5350_SDM_OFFSET + 0x04)
2436 +#define RT5350_SDM_TRING       (RT5350_SDM_OFFSET + 0x08)
2437 +#define RT5350_SDM_MAC_ADRL    (RT5350_SDM_OFFSET + 0x0C)
2438 +#define RT5350_SDM_MAC_ADRH    (RT5350_SDM_OFFSET + 0x10)
2439 +#define RT5350_SDM_TPCNT       (RT5350_SDM_OFFSET + 0x100)
2440 +#define RT5350_SDM_TBCNT       (RT5350_SDM_OFFSET + 0x104)
2441 +#define RT5350_SDM_RPCNT       (RT5350_SDM_OFFSET + 0x108)
2442 +#define RT5350_SDM_RBCNT       (RT5350_SDM_OFFSET + 0x10C)
2443 +#define RT5350_SDM_CS_ERR      (RT5350_SDM_OFFSET + 0x110)
2444 +
2445 +#define RT5350_SDM_ICS_EN      BIT(16)
2446 +#define RT5350_SDM_TCS_EN      BIT(17)
2447 +#define RT5350_SDM_UCS_EN      BIT(18)
2448 +
2449 +/* MDIO_CFG register bits */
2450 +#define FE_MDIO_CFG_AUTO_POLL_EN       BIT(29)
2451 +#define FE_MDIO_CFG_GP1_BP_EN          BIT(16)
2452 +#define FE_MDIO_CFG_GP1_FRC_EN         BIT(15)
2453 +#define FE_MDIO_CFG_GP1_SPEED_10       (0 << 13)
2454 +#define FE_MDIO_CFG_GP1_SPEED_100      (1 << 13)
2455 +#define FE_MDIO_CFG_GP1_SPEED_1000     (2 << 13)
2456 +#define FE_MDIO_CFG_GP1_DUPLEX         BIT(12)
2457 +#define FE_MDIO_CFG_GP1_FC_TX          BIT(11)
2458 +#define FE_MDIO_CFG_GP1_FC_RX          BIT(10)
2459 +#define FE_MDIO_CFG_GP1_LNK_DWN                BIT(9)
2460 +#define FE_MDIO_CFG_GP1_AN_FAIL                BIT(8)
2461 +#define FE_MDIO_CFG_MDC_CLK_DIV_1      (0 << 6)
2462 +#define FE_MDIO_CFG_MDC_CLK_DIV_2      (1 << 6)
2463 +#define FE_MDIO_CFG_MDC_CLK_DIV_4      (2 << 6)
2464 +#define FE_MDIO_CFG_MDC_CLK_DIV_8      (3 << 6)
2465 +#define FE_MDIO_CFG_TURBO_MII_FREQ     BIT(5)
2466 +#define FE_MDIO_CFG_TURBO_MII_MODE     BIT(4)
2467 +#define FE_MDIO_CFG_RX_CLK_SKEW_0      (0 << 2)
2468 +#define FE_MDIO_CFG_RX_CLK_SKEW_200    (1 << 2)
2469 +#define FE_MDIO_CFG_RX_CLK_SKEW_400    (2 << 2)
2470 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV    (3 << 2)
2471 +#define FE_MDIO_CFG_TX_CLK_SKEW_0      0
2472 +#define FE_MDIO_CFG_TX_CLK_SKEW_200    1
2473 +#define FE_MDIO_CFG_TX_CLK_SKEW_400    2
2474 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV    3
2475 +
2476 +/* uni-cast port */
2477 +#define FE_GDM1_JMB_LEN_MASK   0xf
2478 +#define FE_GDM1_JMB_LEN_SHIFT  28
2479 +#define FE_GDM1_ICS_EN         BIT(22)
2480 +#define FE_GDM1_TCS_EN         BIT(21)
2481 +#define FE_GDM1_UCS_EN         BIT(20)
2482 +#define FE_GDM1_JMB_EN         BIT(19)
2483 +#define FE_GDM1_STRPCRC                BIT(16)
2484 +#define FE_GDM1_UFRC_P_CPU     (0 << 12)
2485 +#define FE_GDM1_UFRC_P_GDMA1   (1 << 12)
2486 +#define FE_GDM1_UFRC_P_PPE     (6 << 12)
2487 +
2488 +/* checksums */
2489 +#define FE_ICS_GEN_EN          BIT(2)
2490 +#define FE_UCS_GEN_EN          BIT(1)
2491 +#define FE_TCS_GEN_EN          BIT(0)
2492 +
2493 +/* dma ring */
2494 +#define FE_PST_DRX_IDX0                BIT(16)
2495 +#define FE_PST_DTX_IDX3                BIT(3)
2496 +#define FE_PST_DTX_IDX2                BIT(2)
2497 +#define FE_PST_DTX_IDX1                BIT(1)
2498 +#define FE_PST_DTX_IDX0                BIT(0)
2499 +
2500 +#define FE_RX_2B_OFFSET                BIT(31)
2501 +#define FE_TX_WB_DDONE         BIT(6)
2502 +#define FE_RX_DMA_BUSY         BIT(3)
2503 +#define FE_TX_DMA_BUSY         BIT(1)
2504 +#define FE_RX_DMA_EN           BIT(2)
2505 +#define FE_TX_DMA_EN           BIT(0)
2506 +
2507 +#define FE_PDMA_SIZE_4DWORDS   (0 << 4)
2508 +#define FE_PDMA_SIZE_8DWORDS   (1 << 4)
2509 +#define FE_PDMA_SIZE_16DWORDS  (2 << 4)
2510 +
2511 +#define FE_US_CYC_CNT_MASK     0xff
2512 +#define FE_US_CYC_CNT_SHIFT    0x8
2513 +#define FE_US_CYC_CNT_DIVISOR  1000000
2514 +
2515 +/* rxd2 */
2516 +#define RX_DMA_DONE            BIT(31)
2517 +#define RX_DMA_LSO             BIT(30)
2518 +#define RX_DMA_PLEN0(_x)       (((_x) & 0x3fff) << 16)
2519 +#define RX_DMA_GET_PLEN0(_x)   (((_x) >> 16) & 0x3fff)
2520 +#define RX_DMA_TAG             BIT(15)
2521 +/* rxd3 */
2522 +#define RX_DMA_TPID(_x)                (((_x) >> 16) & 0xffff)
2523 +#define RX_DMA_VID(_x)         ((_x) & 0xffff)
2524 +/* rxd4 */
2525 +#define RX_DMA_L4VALID         BIT(30)
2526 +
2527 +struct fe_rx_dma {
2528 +       unsigned int rxd1;
2529 +       unsigned int rxd2;
2530 +       unsigned int rxd3;
2531 +       unsigned int rxd4;
2532 +} __packed __aligned(4);
2533 +
2534 +#define TX_DMA_BUF_LEN         0x3fff
2535 +#define TX_DMA_PLEN0_MASK      (TX_DMA_BUF_LEN << 16)
2536 +#define TX_DMA_PLEN0(_x)       (((_x) & TX_DMA_BUF_LEN) << 16)
2537 +#define TX_DMA_PLEN1(_x)       ((_x) & TX_DMA_BUF_LEN)
2538 +#define TX_DMA_GET_PLEN0(_x)    (((_x) >> 16) & TX_DMA_BUF_LEN)
2539 +#define TX_DMA_GET_PLEN1(_x)    ((_x) & TX_DMA_BUF_LEN)
2540 +#define TX_DMA_LS1             BIT(14)
2541 +#define TX_DMA_LS0             BIT(30)
2542 +#define TX_DMA_DONE            BIT(31)
2543 +
2544 +#define TX_DMA_INS_VLAN_MT7621 BIT(16)
2545 +#define TX_DMA_INS_VLAN                BIT(7)
2546 +#define TX_DMA_INS_PPPOE       BIT(12)
2547 +#define TX_DMA_QN(_x)          ((_x) << 16)
2548 +#define TX_DMA_PN(_x)          ((_x) << 24)
2549 +#define TX_DMA_QN_MASK         TX_DMA_QN(0x7)
2550 +#define TX_DMA_PN_MASK         TX_DMA_PN(0x7)
2551 +#define TX_DMA_UDF             BIT(20)
2552 +#define TX_DMA_CHKSUM          (0x7 << 29)
2553 +#define TX_DMA_TSO             BIT(28)
2554 +
2555 +/* frame engine counters */
2556 +#define FE_PPE_AC_BCNT0                (FE_CMTABLE_OFFSET + 0x00)
2557 +#define FE_GDMA1_TX_GBCNT      (FE_CMTABLE_OFFSET + 0x300)
2558 +#define FE_GDMA2_TX_GBCNT      (FE_GDMA1_TX_GBCNT + 0x40)
2559 +
2560 +/* phy device flags */
2561 +#define FE_PHY_FLAG_PORT       BIT(0)
2562 +#define FE_PHY_FLAG_ATTACH     BIT(1)
2563 +
2564 +struct fe_tx_dma {
2565 +       unsigned int txd1;
2566 +       unsigned int txd2;
2567 +       unsigned int txd3;
2568 +       unsigned int txd4;
2569 +} __packed __aligned(4);
2570 +
2571 +struct fe_priv;
2572 +
2573 +struct fe_phy {
2574 +       /* make sure that phy operations are atomic */
2575 +       spinlock_t              lock;
2576 +
2577 +       struct phy_device       *phy[8];
2578 +       struct device_node      *phy_node[8];
2579 +       const __be32            *phy_fixed[8];
2580 +       int                     duplex[8];
2581 +       int                     speed[8];
2582 +       int                     tx_fc[8];
2583 +       int                     rx_fc[8];
2584 +       int (*connect)(struct fe_priv *priv);
2585 +       void (*disconnect)(struct fe_priv *priv);
2586 +       void (*start)(struct fe_priv *priv);
2587 +       void (*stop)(struct fe_priv *priv);
2588 +};
2589 +
2590 +struct fe_soc_data {
2591 +       const u16 *reg_table;
2592 +
2593 +       void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
2594 +       void (*reset_fe)(void);
2595 +       void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
2596 +       int (*fwd_config)(struct fe_priv *priv);
2597 +       void (*tx_dma)(struct fe_tx_dma *txd);
2598 +       int (*switch_init)(struct fe_priv *priv);
2599 +       void (*port_init)(struct fe_priv *priv, struct device_node *port);
2600 +       int (*has_carrier)(struct fe_priv *priv);
2601 +       int (*mdio_init)(struct fe_priv *priv);
2602 +       void (*mdio_cleanup)(struct fe_priv *priv);
2603 +       int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,
2604 +                         u16 val);
2605 +       int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
2606 +       void (*mdio_adjust_link)(struct fe_priv *priv, int port);
2607 +
2608 +       void *swpriv;
2609 +       u32 pdma_glo_cfg;
2610 +       u32 rx_int;
2611 +       u32 tx_int;
2612 +       u32 status_int;
2613 +       u32 checksum_bit;
2614 +};
2615 +
2616 +#define FE_FLAG_PADDING_64B            BIT(0)
2617 +#define FE_FLAG_PADDING_BUG            BIT(1)
2618 +#define FE_FLAG_JUMBO_FRAME            BIT(2)
2619 +#define FE_FLAG_RX_2B_OFFSET           BIT(3)
2620 +#define FE_FLAG_RX_SG_DMA              BIT(4)
2621 +#define FE_FLAG_RX_VLAN_CTAG           BIT(5)
2622 +#define FE_FLAG_NAPI_WEIGHT            BIT(6)
2623 +#define FE_FLAG_CALIBRATE_CLK          BIT(7)
2624 +#define FE_FLAG_HAS_SWITCH             BIT(8)
2625 +
2626 +#define FE_STAT_REG_DECLARE            \
2627 +       _FE(tx_bytes)                   \
2628 +       _FE(tx_packets)                 \
2629 +       _FE(tx_skip)                    \
2630 +       _FE(tx_collisions)              \
2631 +       _FE(rx_bytes)                   \
2632 +       _FE(rx_packets)                 \
2633 +       _FE(rx_overflow)                \
2634 +       _FE(rx_fcs_errors)              \
2635 +       _FE(rx_short_errors)            \
2636 +       _FE(rx_long_errors)             \
2637 +       _FE(rx_checksum_errors)         \
2638 +       _FE(rx_flow_control_packets)
2639 +
2640 +struct fe_hw_stats {
2641 +       /* make sure that stats operations are atomic */
2642 +       spinlock_t stats_lock;
2643 +
2644 +       struct u64_stats_sync syncp;
2645 +#define _FE(x) u64 x;
2646 +       FE_STAT_REG_DECLARE
2647 +#undef _FE
2648 +};
2649 +
2650 +enum fe_tx_flags {
2651 +       FE_TX_FLAGS_SINGLE0     = 0x01,
2652 +       FE_TX_FLAGS_PAGE0       = 0x02,
2653 +       FE_TX_FLAGS_PAGE1       = 0x04,
2654 +};
2655 +
2656 +struct fe_tx_buf {
2657 +       struct sk_buff *skb;
2658 +       u32 flags;
2659 +       DEFINE_DMA_UNMAP_ADDR(dma_addr0);
2660 +       DEFINE_DMA_UNMAP_LEN(dma_len0);
2661 +       DEFINE_DMA_UNMAP_ADDR(dma_addr1);
2662 +       DEFINE_DMA_UNMAP_LEN(dma_len1);
2663 +};
2664 +
2665 +struct fe_tx_ring {
2666 +       struct fe_tx_dma *tx_dma;
2667 +       struct fe_tx_buf *tx_buf;
2668 +       dma_addr_t tx_phys;
2669 +       u16 tx_ring_size;
2670 +       u16 tx_free_idx;
2671 +       u16 tx_next_idx;
2672 +       u16 tx_thresh;
2673 +};
2674 +
2675 +struct fe_rx_ring {
2676 +       struct fe_rx_dma *rx_dma;
2677 +       u8 **rx_data;
2678 +       dma_addr_t rx_phys;
2679 +       u16 rx_ring_size;
2680 +       u16 frag_size;
2681 +       u16 rx_buf_size;
2682 +       u16 rx_calc_idx;
2683 +};
2684 +
2685 +struct fe_priv {
2686 +       /* make sure that register operations are atomic */
2687 +       spinlock_t                      page_lock;
2688 +
2689 +       struct fe_soc_data              *soc;
2690 +       struct net_device               *netdev;
2691 +       struct device_node              *switch_np;
2692 +       u32                             msg_enable;
2693 +       u32                             flags;
2694 +
2695 +       struct device                   *device;
2696 +       unsigned long                   sysclk;
2697 +
2698 +       struct fe_rx_ring               rx_ring;
2699 +       struct napi_struct              rx_napi;
2700 +
2701 +       struct fe_tx_ring               tx_ring;
2702 +
2703 +       struct fe_phy                   *phy;
2704 +       struct mii_bus                  *mii_bus;
2705 +       struct phy_device               *phy_dev;
2706 +       u32                             phy_flags;
2707 +
2708 +       int                             link[8];
2709 +
2710 +       struct fe_hw_stats              *hw_stats;
2711 +       unsigned long                   vlan_map;
2712 +       struct work_struct              pending_work;
2713 +       DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
2714 +};
2715 +
2716 +extern const struct of_device_id of_fe_match[];
2717 +
2718 +void fe_w32(u32 val, unsigned reg);
2719 +u32 fe_r32(unsigned reg);
2720 +
2721 +int fe_set_clock_cycle(struct fe_priv *priv);
2722 +void fe_csum_config(struct fe_priv *priv);
2723 +void fe_stats_update(struct fe_priv *priv);
2724 +void fe_fwd_config(struct fe_priv *priv);
2725 +void fe_reg_w32(u32 val, enum fe_reg reg);
2726 +u32 fe_reg_r32(enum fe_reg reg);
2727 +
2728 +void fe_reset(u32 reset_bits);
2729 +
2730 +static inline void *priv_netdev(struct fe_priv *priv)
2731 +{
2732 +       return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
2733 +}
2734 +
2735 +#endif /* FE_ETH_H */