target/linux/ramips/patches-4.3/0052-pwm-add-mediatek-support.patch

   1 From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:16:50 +0100
   4 Subject: [PATCH 52/53] pwm: add mediatek support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/pwm/Kconfig        |    9 +++
   9  drivers/pwm/Makefile       |    1 +
  10  drivers/pwm/pwm-mediatek.c |  173 ++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 183 insertions(+)
  12  create mode 100644 drivers/pwm/pwm-mediatek.c
  13
  14 --- a/drivers/pwm/Kconfig
  15 +++ b/drivers/pwm/Kconfig
  16 @@ -230,6 +230,15 @@ config PWM_LPSS_PLATFORM
  17           To compile this driver as a module, choose M here: the module
  18           will be called pwm-lpss-platform.
  19
  20 +config PWM_MEDIATEK
  21 +       tristate "Mediatek PWM support"
  22 +       depends on RALINK && OF
  23 +       help
  24 +         Generic PWM framework driver for Mediatek ARM SoC.
  25 +
  26 +         To compile this driver as a module, choose M here: the module
  27 +         will be called pwm-mxs.
  28 +
  29  config PWM_MXS
  30         tristate "Freescale MXS PWM support"
  31         depends on ARCH_MXS && OF
  32 --- a/drivers/pwm/Makefile
  33 +++ b/drivers/pwm/Makefile
  34 @@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_LPC32XX)     += pwm-lpc32xx
  35  obj-$(CONFIG_PWM_LPSS)         += pwm-lpss.o
  36  obj-$(CONFIG_PWM_LPSS_PCI)     += pwm-lpss-pci.o
  37  obj-$(CONFIG_PWM_LPSS_PLATFORM)        += pwm-lpss-platform.o
  38 +obj-$(CONFIG_PWM_MEDIATEK)     += pwm-mediatek.o
  39  obj-$(CONFIG_PWM_MXS)          += pwm-mxs.o
  40  obj-$(CONFIG_PWM_PCA9685)      += pwm-pca9685.o
  41  obj-$(CONFIG_PWM_PUV3)         += pwm-puv3.o
  42 --- /dev/null
  43 +++ b/drivers/pwm/pwm-mediatek.c
  44 @@ -0,0 +1,173 @@
  45 +/*
  46 + * Mediatek Pulse Width Modulator driver
  47 + *
  48 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
  49 + *
  50 + * This file is licensed under the terms of the GNU General Public
  51 + * License version 2. This program is licensed "as is" without any
  52 + * warranty of any kind, whether express or implied.
  53 + */
  54 +
  55 +#include <linux/err.h>
  56 +#include <linux/io.h>
  57 +#include <linux/ioport.h>
  58 +#include <linux/kernel.h>
  59 +#include <linux/module.h>
  60 +#include <linux/of.h>
  61 +#include <linux/platform_device.h>
  62 +#include <linux/pwm.h>
  63 +#include <linux/slab.h>
  64 +#include <linux/types.h>
  65 +
  66 +#define NUM_PWM                4
  67 +
  68 +/* PWM registers and bits definitions */
  69 +#define PWMCON                 0x00
  70 +#define PWMHDUR                        0x04
  71 +#define PWMLDUR                        0x08
  72 +#define PWMGDUR                        0x0c
  73 +#define PWMWAVENUM             0x28
  74 +#define PWMDWIDTH              0x2c
  75 +#define PWMTHRES               0x30
  76 +
  77 +/**
  78 + * struct mtk_pwm_chip - struct representing pwm chip
  79 + *
  80 + * @mmio_base: base address of pwm chip
  81 + * @chip: linux pwm chip representation
  82 + */
  83 +struct mtk_pwm_chip {
  84 +       void __iomem *mmio_base;
  85 +       struct pwm_chip chip;
  86 +};
  87 +
  88 +static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
  89 +{
  90 +       return container_of(chip, struct mtk_pwm_chip, chip);
  91 +}
  92 +
  93 +static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
  94 +                                 unsigned long offset)
  95 +{
  96 +       return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
  97 +}
  98 +
  99 +static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
 100 +                                   unsigned int num, unsigned long offset,
 101 +                                   unsigned long val)
 102 +{
 103 +       iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
 104 +}
 105 +
 106 +static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 107 +                           int duty_ns, int period_ns)
 108 +{
 109 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 110 +       u32 resolution = 100 / 4;
 111 +       u32 clkdiv = 0;
 112 +
 113 +       while (period_ns / resolution  > 8191) {
 114 +               clkdiv++;
 115 +               resolution *= 2;
 116 +       }
 117 +
 118 +       if (clkdiv > 7)
 119 +               return -1;
 120 +
 121 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
 122 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
 123 +       mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
 124 +       return 0;
 125 +}
 126 +
 127 +static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 128 +{
 129 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 130 +       u32 val;
 131 +
 132 +       val = ioread32(pc->mmio_base);
 133 +       val |= BIT(pwm->hwpwm);
 134 +       iowrite32(val, pc->mmio_base);
 135 +
 136 +       return 0;
 137 +}
 138 +
 139 +static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 140 +{
 141 +       struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
 142 +       u32 val;
 143 +
 144 +       val = ioread32(pc->mmio_base);
 145 +       val &= ~BIT(pwm->hwpwm);
 146 +       iowrite32(val, pc->mmio_base);
 147 +}
 148 +
 149 +static const struct pwm_ops mtk_pwm_ops = {
 150 +       .config = mtk_pwm_config,
 151 +       .enable = mtk_pwm_enable,
 152 +       .disable = mtk_pwm_disable,
 153 +       .owner = THIS_MODULE,
 154 +};
 155 +
 156 +static int mtk_pwm_probe(struct platform_device *pdev)
 157 +{
 158 +       struct mtk_pwm_chip *pc;
 159 +       struct resource *r;
 160 +       int ret;
 161 +
 162 +       pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 163 +       if (!pc)
 164 +               return -ENOMEM;
 165 +
 166 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 167 +       pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 168 +       if (IS_ERR(pc->mmio_base))
 169 +               return PTR_ERR(pc->mmio_base);
 170 +
 171 +       platform_set_drvdata(pdev, pc);
 172 +
 173 +       pc->chip.dev = &pdev->dev;
 174 +       pc->chip.ops = &mtk_pwm_ops;
 175 +       pc->chip.base = -1;
 176 +       pc->chip.npwm = NUM_PWM;
 177 +
 178 +       ret = pwmchip_add(&pc->chip);
 179 +       if (ret < 0)
 180 +               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 181 +
 182 +       return ret;
 183 +}
 184 +
 185 +static int mtk_pwm_remove(struct platform_device *pdev)
 186 +{
 187 +       struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
 188 +       int i;
 189 +
 190 +       for (i = 0; i < NUM_PWM; i++)
 191 +               pwm_disable(&pc->chip.pwms[i]);
 192 +
 193 +       return pwmchip_remove(&pc->chip);
 194 +}
 195 +
 196 +static const struct of_device_id mtk_pwm_of_match[] = {
 197 +       { .compatible = "mediatek,mt7628-pwm" },
 198 +       { }
 199 +};
 200 +
 201 +MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
 202 +
 203 +static struct platform_driver mtk_pwm_driver = {
 204 +       .driver = {
 205 +               .name = "mtk-pwm",
 206 +               .owner = THIS_MODULE,
 207 +               .of_match_table = mtk_pwm_of_match,
 208 +       },
 209 +       .probe = mtk_pwm_probe,
 210 +       .remove = mtk_pwm_remove,
 211 +};
 212 +
 213 +module_platform_driver(mtk_pwm_driver);
 214 +
 215 +MODULE_LICENSE("GPL");
 216 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 217 +MODULE_ALIAS("platform:mtk-pwm");