1 From d3c1e72c755cf67427b5d410039a096520d6537f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 7 Dec 2015 17:19:55 +0100
4 Subject: [PATCH 18/53] arch: mips: ralink: reset pci prior to reboot
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/ralink/reset.c | 12 ++++++++++--
9 1 file changed, 10 insertions(+), 2 deletions(-)
11 diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
12 index ee26d45..ee117c4 100644
13 --- a/arch/mips/ralink/reset.c
14 +++ b/arch/mips/ralink/reset.c
19 +#include <linux/delay.h>
20 #include <linux/reset-controller.h>
22 #include <asm/reboot.h>
24 #include <asm/mach-ralink/ralink_regs.h>
27 -#define SYSC_REG_RESET_CTRL 0x034
28 -#define RSTCTL_RESET_SYSTEM BIT(0)
29 +#define SYSC_REG_RESET_CTRL 0x034
31 +#define RSTCTL_RESET_PCI BIT(26)
32 +#define RSTCTL_RESET_SYSTEM BIT(0)
34 static int ralink_assert_device(struct reset_controller_dev *rcdev,
36 @@ -83,6 +86,11 @@ void ralink_rst_init(void)
38 static void ralink_restart(char *command)
40 + if (IS_ENABLED(CONFIG_PCI)) {
41 + rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
46 rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);