target/linux/ramips/patches-3.9/0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch

   1 From 1efe3ce91ab951090ac8db1872f0de32e0a88de8 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:20:03 +0200
   4 Subject: [PATCH] NET: MIPS: add ralink SoC ethernet driver
   5
   6 Add support for Ralink FE and ESW.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
  11  arch/mips/ralink/rt305x.c                          |    1 +
  12  drivers/net/ethernet/Kconfig                       |    1 +
  13  drivers/net/ethernet/Makefile                      |    1 +
  14  drivers/net/ethernet/ralink/Kconfig                |   31 +
  15  drivers/net/ethernet/ralink/Makefile               |   18 +
  16  drivers/net/ethernet/ralink/esw_rt3052.c           | 1463 ++++++++++++++++++++
  17  drivers/net/ethernet/ralink/esw_rt3052.h           |   32 +
  18  drivers/net/ethernet/ralink/gsw_mt7620a.c          | 1027 ++++++++++++++
  19  drivers/net/ethernet/ralink/gsw_mt7620a.h          |   29 +
  20  drivers/net/ethernet/ralink/mdio.c                 |  245 ++++
  21  drivers/net/ethernet/ralink/mdio.h                 |   29 +
  22  drivers/net/ethernet/ralink/mdio_rt2880.c          |  232 ++++
  23  drivers/net/ethernet/ralink/mdio_rt2880.h          |   26 +
  24  drivers/net/ethernet/ralink/ralink_soc_eth.c       |  746 ++++++++++
  25  drivers/net/ethernet/ralink/ralink_soc_eth.h       |  374 +++++
  26  drivers/net/ethernet/ralink/soc_mt7620.c           |  111 ++
  27  drivers/net/ethernet/ralink/soc_rt2880.c           |   51 +
  28  drivers/net/ethernet/ralink/soc_rt305x.c           |  113 ++
  29  drivers/net/ethernet/ralink/soc_rt3883.c           |   60 +
  30  drivers/watchdog/rt2880_wdt.c                      |    9 +-
  31  21 files changed, 4622 insertions(+), 4 deletions(-)
  32  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  33  create mode 100644 drivers/net/ethernet/ralink/Kconfig
  34  create mode 100644 drivers/net/ethernet/ralink/Makefile
  35  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
  36  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
  37  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
  38  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
  39  create mode 100644 drivers/net/ethernet/ralink/mdio.c
  40  create mode 100644 drivers/net/ethernet/ralink/mdio.h
  41  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
  42  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
  43  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
  44  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
  45  create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
  46  create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
  47  create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
  48  create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
  49
  50 --- /dev/null
  51 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  52 @@ -0,0 +1,27 @@
  53 +/*
  54 + *  Ralink RT305x SoC platform device registration
  55 + *
  56 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  57 + *
  58 + *  This program is free software; you can redistribute it and/or modify it
  59 + *  under the terms of the GNU General Public License version 2 as published
  60 + *  by the Free Software Foundation.
  61 + */
  62 +
  63 +#ifndef _RT305X_ESW_PLATFORM_H
  64 +#define _RT305X_ESW_PLATFORM_H
  65 +
  66 +enum {
  67 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
  68 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
  69 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
  70 +};
  71 +
  72 +struct rt305x_esw_platform_data
  73 +{
  74 +       u8 vlan_config;
  75 +       u32 reg_initval_fct2;
  76 +       u32 reg_initval_fpa2;
  77 +};
  78 +
  79 +#endif /* _RT305X_ESW_PLATFORM_H */
  80 --- a/arch/mips/ralink/rt305x.c
  81 +++ b/arch/mips/ralink/rt305x.c
  82 @@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
  83         }
  84
  85         ralink_clk_add("cpu", cpu_rate);
  86 +       ralink_clk_add("sys", sys_rate);
  87         ralink_clk_add("10000b00.spi", sys_rate);
  88         ralink_clk_add("10000100.timer", wdt_rate);
  89         ralink_clk_add("10000120.watchdog", wdt_rate);
  90 --- a/drivers/net/ethernet/Kconfig
  91 +++ b/drivers/net/ethernet/Kconfig
  92 @@ -135,6 +135,7 @@ config ETHOC
  93  source "drivers/net/ethernet/packetengines/Kconfig"
  94  source "drivers/net/ethernet/pasemi/Kconfig"
  95  source "drivers/net/ethernet/qlogic/Kconfig"
  96 +source "drivers/net/ethernet/ralink/Kconfig"
  97  source "drivers/net/ethernet/realtek/Kconfig"
  98  source "drivers/net/ethernet/renesas/Kconfig"
  99  source "drivers/net/ethernet/rdc/Kconfig"
 100 --- a/drivers/net/ethernet/Makefile
 101 +++ b/drivers/net/ethernet/Makefile
 102 @@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
 103  obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
 104  obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
 105  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
 106 +obj-$(CONFIG_NET_RALINK) += ralink/
 107  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
 108  obj-$(CONFIG_SH_ETH) += renesas/
 109  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
 110 --- /dev/null
 111 +++ b/drivers/net/ethernet/ralink/Kconfig
 112 @@ -0,0 +1,31 @@
 113 +config NET_RALINK
 114 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
 115 +       depends on RALINK
 116 +       help
 117 +         This driver supports the ethernet mac inside the ralink wisocs
 118 +
 119 +if NET_RALINK
 120 +
 121 +config NET_RALINK_MDIO
 122 +       def_bool NET_RALINK
 123 +       depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
 124 +       select PHYLIB
 125 +
 126 +config NET_RALINK_MDIO_RT2880
 127 +       def_bool NET_RALINK
 128 +       depends on (SOC_RT288X || SOC_RT3883)
 129 +       select NET_RALINK_MDIO
 130 +
 131 +config NET_RALINK_ESW_RT3052
 132 +       def_bool NET_RALINK
 133 +       depends on SOC_RT305X
 134 +       select PHYLIB
 135 +       select SWCONFIG
 136 +
 137 +config NET_RALINK_GSW_MT7620
 138 +       def_bool NET_RALINK
 139 +       depends on SOC_MT7620
 140 +       select NET_RALINK_MDIO
 141 +       select PHYLIB
 142 +       select SWCONFIG
 143 +endif
 144 --- /dev/null
 145 +++ b/drivers/net/ethernet/ralink/Makefile
 146 @@ -0,0 +1,18 @@
 147 +#
 148 +# Makefile for the Ralink SoCs built-in ethernet macs
 149 +#
 150 +
 151 +ralink-eth-y                                   += ralink_soc_eth.o
 152 +
 153 +ralink-eth-$(CONFIG_NET_RALINK_MDIO)           += mdio.o
 154 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)    += mdio_rt2880.o
 155 +
 156 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052)     += esw_rt3052.o
 157 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620)     += gsw_mt7620a.o
 158 +
 159 +ralink-eth-$(CONFIG_SOC_RT288X)                        += soc_rt2880.o
 160 +ralink-eth-$(CONFIG_SOC_RT305X)                        += soc_rt305x.o
 161 +ralink-eth-$(CONFIG_SOC_RT3883)                        += soc_rt3883.o
 162 +ralink-eth-$(CONFIG_SOC_MT7620)                        += soc_mt7620.o
 163 +
 164 +obj-$(CONFIG_NET_RALINK)                       += ralink-eth.o
 165 --- /dev/null
 166 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
 167 @@ -0,0 +1,1463 @@
 168 +/*
 169 + *   This program is free software; you can redistribute it and/or modify
 170 + *   it under the terms of the GNU General Public License as published by
 171 + *   the Free Software Foundation; version 2 of the License
 172 + *
 173 + *   This program is distributed in the hope that it will be useful,
 174 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 175 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 176 + *   GNU General Public License for more details.
 177 + *
 178 + *   You should have received a copy of the GNU General Public License
 179 + *   along with this program; if not, write to the Free Software
 180 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 181 + *
 182 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
 183 + */
 184 +
 185 +#include <linux/module.h>
 186 +#include <linux/kernel.h>
 187 +#include <linux/types.h>
 188 +#include <linux/dma-mapping.h>
 189 +#include <linux/init.h>
 190 +#include <linux/skbuff.h>
 191 +#include <linux/etherdevice.h>
 192 +#include <linux/ethtool.h>
 193 +#include <linux/platform_device.h>
 194 +#include <linux/of_device.h>
 195 +#include <linux/clk.h>
 196 +#include <linux/of_net.h>
 197 +#include <linux/of_mdio.h>
 198 +
 199 +#include <asm/mach-ralink/ralink_regs.h>
 200 +
 201 +#include "ralink_soc_eth.h"
 202 +
 203 +#include <linux/ioport.h>
 204 +#include <linux/switch.h>
 205 +#include <linux/mii.h>
 206 +
 207 +#include <ralink_regs.h>
 208 +#include <asm/mach-ralink/rt305x.h>
 209 +#include <asm/mach-ralink/rt305x_esw_platform.h>
 210 +
 211 +/*
 212 + * HW limitations for this switch:
 213 + * - No large frame support (PKT_MAX_LEN at most 1536)
 214 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
 215 + *   though this might be possible using the undocumented PPE.
 216 + */
 217 +
 218 +#define RT305X_ESW_REG_ISR             0x00
 219 +#define RT305X_ESW_REG_IMR             0x04
 220 +#define RT305X_ESW_REG_FCT0            0x08
 221 +#define RT305X_ESW_REG_PFC1            0x14
 222 +#define RT305X_ESW_REG_ATS             0x24
 223 +#define RT305X_ESW_REG_ATS0            0x28
 224 +#define RT305X_ESW_REG_ATS1            0x2c
 225 +#define RT305X_ESW_REG_ATS2            0x30
 226 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 227 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 228 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 229 +#define RT305X_ESW_REG_POA             0x80
 230 +#define RT305X_ESW_REG_FPA             0x84
 231 +#define RT305X_ESW_REG_SOCPC           0x8c
 232 +#define RT305X_ESW_REG_POC0            0x90
 233 +#define RT305X_ESW_REG_POC1            0x94
 234 +#define RT305X_ESW_REG_POC2            0x98
 235 +#define RT305X_ESW_REG_SGC             0x9c
 236 +#define RT305X_ESW_REG_STRT            0xa0
 237 +#define RT305X_ESW_REG_PCR0            0xc0
 238 +#define RT305X_ESW_REG_PCR1            0xc4
 239 +#define RT305X_ESW_REG_FPA2            0xc8
 240 +#define RT305X_ESW_REG_FCT2            0xcc
 241 +#define RT305X_ESW_REG_SGC2            0xe4
 242 +#define RT305X_ESW_REG_P0LED           0xa4
 243 +#define RT305X_ESW_REG_P1LED           0xa8
 244 +#define RT305X_ESW_REG_P2LED           0xac
 245 +#define RT305X_ESW_REG_P3LED           0xb0
 246 +#define RT305X_ESW_REG_P4LED           0xb4
 247 +#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
 248 +#define RT305X_ESW_REG_P1PC            0xec
 249 +#define RT305X_ESW_REG_P2PC            0xf0
 250 +#define RT305X_ESW_REG_P3PC            0xf4
 251 +#define RT305X_ESW_REG_P4PC            0xf8
 252 +#define RT305X_ESW_REG_P5PC            0xfc
 253 +
 254 +#define RT305X_ESW_LED_LINK            0
 255 +#define RT305X_ESW_LED_100M            1
 256 +#define RT305X_ESW_LED_DUPLEX          2
 257 +#define RT305X_ESW_LED_ACTIVITY                3
 258 +#define RT305X_ESW_LED_COLLISION       4
 259 +#define RT305X_ESW_LED_LINKACT         5
 260 +#define RT305X_ESW_LED_DUPLCOLL                6
 261 +#define RT305X_ESW_LED_10MACT          7
 262 +#define RT305X_ESW_LED_100MACT         8
 263 +/* Additional led states not in datasheet: */
 264 +#define RT305X_ESW_LED_BLINK           10
 265 +#define RT305X_ESW_LED_ON              12
 266 +
 267 +#define RT305X_ESW_LINK_S              25
 268 +#define RT305X_ESW_DUPLEX_S            9
 269 +#define RT305X_ESW_SPD_S               0
 270 +
 271 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
 272 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
 273 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
 274 +
 275 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
 276 +
 277 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
 278 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 279 +
 280 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
 281 +#define RT305X_ESW_PVIDC_PVID_S                12
 282 +
 283 +#define RT305X_ESW_VLANI_VID_M         0xfff
 284 +#define RT305X_ESW_VLANI_VID_S         12
 285 +
 286 +#define RT305X_ESW_VMSC_MSC_M          0xff
 287 +#define RT305X_ESW_VMSC_MSC_S          8
 288 +
 289 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
 290 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
 291 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
 292 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
 293 +
 294 +#define RT305X_ESW_POC0_EN_BP_S                0
 295 +#define RT305X_ESW_POC0_EN_FC_S                8
 296 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
 297 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
 298 +#define RT305X_ESW_POC0_DIS_PORT_S     23
 299 +
 300 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
 301 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
 302 +#define RT305X_ESW_POC2_ENAGING_S      8
 303 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
 304 +
 305 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
 306 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
 307 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
 308 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
 309 +
 310 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
 311 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
 312 +#define RT305X_ESW_PFC1_EN_TOS_S       24
 313 +
 314 +#define RT305X_ESW_VLAN_NONE           0xfff
 315 +
 316 +#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
 317 +#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
 318 +
 319 +#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
 320 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
 321 +
 322 +#define RT305X_ESW_POA_LINK_MASK       0x1f
 323 +#define RT305X_ESW_POA_LINK_SHIFT      25
 324 +
 325 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
 326 +#define RT305X_ESW_PORT0               0
 327 +#define RT305X_ESW_PORT1               1
 328 +#define RT305X_ESW_PORT2               2
 329 +#define RT305X_ESW_PORT3               3
 330 +#define RT305X_ESW_PORT4               4
 331 +#define RT305X_ESW_PORT5               5
 332 +#define RT305X_ESW_PORT6               6
 333 +
 334 +#define RT305X_ESW_PORTS_NONE          0
 335 +
 336 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
 337 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
 338 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
 339 +
 340 +#define RT305X_ESW_PORTS_INTERNAL                                      \
 341 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 342 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 343 +                BIT(RT305X_ESW_PORT4))
 344 +
 345 +#define RT305X_ESW_PORTS_NOCPU                                         \
 346 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 347 +
 348 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
 349 +
 350 +#define RT305X_ESW_PORTS_ALL                                           \
 351 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 352 +
 353 +#define RT305X_ESW_NUM_VLANS           16
 354 +#define RT305X_ESW_NUM_VIDS            4096
 355 +#define RT305X_ESW_NUM_PORTS           7
 356 +#define RT305X_ESW_NUM_LANWAN          6
 357 +#define RT305X_ESW_NUM_LEDS            5
 358 +
 359 +#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
 360 +#define RT5350_EWS_REG_LED_POLARITY    0x168
 361 +#define RT5350_RESET_EPHY              BIT(24)
 362 +#define SYSC_REG_RESET_CTRL            0x34
 363 +
 364 +enum {
 365 +       /* Global attributes. */
 366 +       RT305X_ESW_ATTR_ENABLE_VLAN,
 367 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 368 +       RT305X_ESW_ATTR_BC_STATUS,
 369 +       RT305X_ESW_ATTR_LED_FREQ,
 370 +       /* Port attributes. */
 371 +       RT305X_ESW_ATTR_PORT_DISABLE,
 372 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
 373 +       RT305X_ESW_ATTR_PORT_UNTAG,
 374 +       RT305X_ESW_ATTR_PORT_LED,
 375 +       RT305X_ESW_ATTR_PORT_LAN,
 376 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
 377 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
 378 +       RT5350_ESW_ATTR_PORT_TR_BAD,
 379 +       RT5350_ESW_ATTR_PORT_TR_GOOD,
 380 +};
 381 +
 382 +struct esw_port {
 383 +       bool    disable;
 384 +       bool    doubletag;
 385 +       bool    untag;
 386 +       u8      led;
 387 +       u16     pvid;
 388 +};
 389 +
 390 +struct esw_vlan {
 391 +       u8      ports;
 392 +       u16     vid;
 393 +};
 394 +
 395 +struct rt305x_esw {
 396 +       struct device           *dev;
 397 +       void __iomem            *base;
 398 +       int                     irq;
 399 +       const struct rt305x_esw_platform_data *pdata;
 400 +       /* Protects against concurrent register rmw operations. */
 401 +       spinlock_t              reg_rw_lock;
 402 +
 403 +       unsigned char           port_map;
 404 +       unsigned int            reg_initval_fct2;
 405 +       unsigned int            reg_initval_fpa2;
 406 +       unsigned int            reg_led_polarity;
 407 +
 408 +
 409 +       struct switch_dev       swdev;
 410 +       bool                    global_vlan_enable;
 411 +       bool                    alt_vlan_disable;
 412 +       int                     bc_storm_protect;
 413 +       int                     led_frequency;
 414 +       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 415 +       struct esw_port ports[RT305X_ESW_NUM_PORTS];
 416 +
 417 +};
 418 +
 419 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
 420 +{
 421 +       __raw_writel(val, esw->base + reg);
 422 +}
 423 +
 424 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
 425 +{
 426 +       return __raw_readl(esw->base + reg);
 427 +}
 428 +
 429 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 430 +                  unsigned long val)
 431 +{
 432 +       unsigned long t;
 433 +
 434 +       t = __raw_readl(esw->base + reg) & ~mask;
 435 +       __raw_writel(t | val, esw->base + reg);
 436 +}
 437 +
 438 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 439 +              unsigned long val)
 440 +{
 441 +       unsigned long flags;
 442 +
 443 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
 444 +       esw_rmw_raw(esw, reg, mask, val);
 445 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 446 +}
 447 +
 448 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 449 +                u32 write_data)
 450 +{
 451 +       unsigned long t_start = jiffies;
 452 +       int ret = 0;
 453 +
 454 +       while (1) {
 455 +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
 456 +                     RT305X_ESW_PCR1_WT_DONE))
 457 +                       break;
 458 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 459 +                       ret = 1;
 460 +                       goto out;
 461 +               }
 462 +       }
 463 +
 464 +       write_data &= 0xffff;
 465 +       esw_w32(esw,
 466 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 467 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 468 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 469 +                     RT305X_ESW_REG_PCR0);
 470 +
 471 +       t_start = jiffies;
 472 +       while (1) {
 473 +               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
 474 +                   RT305X_ESW_PCR1_WT_DONE)
 475 +                       break;
 476 +
 477 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 478 +                       ret = 1;
 479 +                       break;
 480 +               }
 481 +       }
 482 +out:
 483 +       if (ret)
 484 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 485 +       return ret;
 486 +}
 487 +
 488 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 489 +{
 490 +       unsigned s;
 491 +       unsigned val;
 492 +
 493 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 494 +       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 495 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 496 +
 497 +       return val;
 498 +}
 499 +
 500 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 501 +{
 502 +       unsigned s;
 503 +
 504 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 505 +       esw_rmw(esw,
 506 +                      RT305X_ESW_REG_VLANI(vlan / 2),
 507 +                      RT305X_ESW_VLANI_VID_M << s,
 508 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
 509 +}
 510 +
 511 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 512 +{
 513 +       unsigned s, val;
 514 +
 515 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 516 +       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
 517 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 518 +}
 519 +
 520 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 521 +{
 522 +       unsigned s;
 523 +
 524 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 525 +       esw_rmw(esw,
 526 +                      RT305X_ESW_REG_PVIDC(port / 2),
 527 +                      RT305X_ESW_PVIDC_PVID_M << s,
 528 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 529 +}
 530 +
 531 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 532 +{
 533 +       unsigned s, val;
 534 +
 535 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 536 +       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 537 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 538 +
 539 +       return val;
 540 +}
 541 +
 542 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 543 +{
 544 +       unsigned s;
 545 +
 546 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 547 +       esw_rmw(esw,
 548 +                      RT305X_ESW_REG_VMSC(vlan / 4),
 549 +                      RT305X_ESW_VMSC_MSC_M << s,
 550 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
 551 +}
 552 +
 553 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
 554 +{
 555 +       unsigned reg;
 556 +       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
 557 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
 558 +              RT305X_ESW_POC0_DIS_PORT_M;
 559 +}
 560 +
 561 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
 562 +{
 563 +       unsigned old_mask;
 564 +       unsigned enable_mask;
 565 +       unsigned changed;
 566 +       int i;
 567 +
 568 +       old_mask = esw_get_port_disable(esw);
 569 +       changed = old_mask ^ disable_mask;
 570 +       enable_mask = old_mask & disable_mask;
 571 +
 572 +       /* enable before writing to MII */
 573 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 574 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 575 +                       RT305X_ESW_POC0_DIS_PORT_S),
 576 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 577 +
 578 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
 579 +               if (!(changed & (1 << i)))
 580 +                       continue;
 581 +               if (disable_mask & (1 << i)) {
 582 +                       /* disable */
 583 +                       rt305x_mii_write(esw, i, MII_BMCR,
 584 +                                        BMCR_PDOWN);
 585 +               } else {
 586 +                       /* enable */
 587 +                       rt305x_mii_write(esw, i, MII_BMCR,
 588 +                                        BMCR_FULLDPLX |
 589 +                                        BMCR_ANENABLE |
 590 +                                        BMCR_ANRESTART |
 591 +                                        BMCR_SPEED100);
 592 +               }
 593 +       }
 594 +
 595 +       /* disable after writing to MII */
 596 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 597 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 598 +                       RT305X_ESW_POC0_DIS_PORT_S),
 599 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 600 +}
 601 +
 602 +static void esw_set_gsc(struct rt305x_esw *esw)
 603 +{
 604 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 605 +               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
 606 +               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
 607 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 608 +               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
 609 +               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
 610 +}
 611 +
 612 +static int esw_apply_config(struct switch_dev *dev);
 613 +
 614 +static void esw_hw_init(struct rt305x_esw *esw)
 615 +{
 616 +       int i;
 617 +       u8 port_disable = 0;
 618 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 619 +
 620 +       /* vodoo from original driver */
 621 +       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 622 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 623 +       /* Port priority 1 for all ports, vlan enabled. */
 624 +       esw_w32(esw, 0x00005555 |
 625 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 626 +                     RT305X_ESW_REG_PFC1);
 627 +
 628 +       /* Enable Back Pressure, and Flow Control */
 629 +       esw_w32(esw,
 630 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 631 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 632 +                     RT305X_ESW_REG_POC0);
 633 +
 634 +       /* Enable Aging, and VLAN TAG removal */
 635 +       esw_w32(esw,
 636 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 637 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 638 +                     RT305X_ESW_REG_POC2);
 639 +
 640 +       if (esw->reg_initval_fct2)
 641 +               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 642 +       else
 643 +               esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 644 +
 645 +       /*
 646 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
 647 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
 648 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
 649 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 650 +        * ports.
 651 +        */
 652 +       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 653 +
 654 +       /* Setup SoC Port control register */
 655 +       esw_w32(esw,
 656 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
 657 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 658 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 659 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 660 +                     RT305X_ESW_REG_SOCPC);
 661 +
 662 +       if (esw->reg_initval_fpa2)
 663 +               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 664 +       else
 665 +               esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 666 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
 667 +
 668 +       /* Force Link/Activity on ports */
 669 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 670 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 671 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 672 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 673 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 674 +
 675 +       /* Copy disabled port configuration from bootloader setup */
 676 +       port_disable = esw_get_port_disable(esw);
 677 +       for (i = 0; i < 6; i++)
 678 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 679 +
 680 +       if (soc_is_rt3352()) {
 681 +               /* reset EPHY */
 682 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 683 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 684 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 685 +
 686 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 687 +               for (i = 0; i < 5; i++) {
 688 +                       if (esw->ports[i].disable) {
 689 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 690 +                       } else {
 691 +                               rt305x_mii_write(esw, i, MII_BMCR,
 692 +                                        BMCR_FULLDPLX |
 693 +                                        BMCR_ANENABLE |
 694 +                                        BMCR_SPEED100);
 695 +                       }
 696 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 697 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 698 +                       /* TX100/TX10 AD/DA current bias */
 699 +                       rt305x_mii_write(esw, i, 29, 0x7016);
 700 +                       /* TX100 slew rate control */
 701 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 702 +               }
 703 +
 704 +               /* select global register */
 705 +               rt305x_mii_write(esw, 0, 31, 0x0);
 706 +               /* enlarge agcsel threshold 3 and threshold 2 */
 707 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 708 +               /* enlarge agcsel threshold 5 and threshold 4 */
 709 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 710 +               /* enlarge agcsel threshold  */
 711 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 712 +               rt305x_mii_write(esw, 0,12, 0x7eaa);
 713 +               /* longer TP_IDL tail length */
 714 +               rt305x_mii_write(esw, 0, 14, 0x65);
 715 +               /* increased squelch pulse count threshold. */
 716 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 717 +               /* set TX10 signal amplitude threshold to minimum */
 718 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 719 +               /* set squelch amplitude to higher threshold */
 720 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 721 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 722 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 723 +               /* set PLL/Receive bias current are calibrated */
 724 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 725 +               /* change PLL/Receive bias current to internal(RT3350) */
 726 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 727 +               /* change PLL bias current to internal(RT3052_MP3) */
 728 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 729 +               /* select local register */
 730 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 731 +       } else if (soc_is_rt5350()) {
 732 +               /* reset EPHY */
 733 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 734 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 735 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 736 +
 737 +               /* set the led polarity */
 738 +               esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
 739 +
 740 +               /* local registers */
 741 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 742 +               for (i = 0; i < 5; i++) {
 743 +                       if (esw->ports[i].disable) {
 744 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 745 +                       } else {
 746 +                               rt305x_mii_write(esw, i, MII_BMCR,
 747 +                                        BMCR_FULLDPLX |
 748 +                                        BMCR_ANENABLE |
 749 +                                        BMCR_SPEED100);
 750 +                       }
 751 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 752 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 753 +                       /* TX100/TX10 AD/DA current bias */
 754 +                       rt305x_mii_write(esw, i, 29, 0x7015);
 755 +                       /* TX100 slew rate control */
 756 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 757 +               }
 758 +
 759 +               /* global registers */
 760 +               rt305x_mii_write(esw, 0, 31, 0x0);
 761 +               /* enlarge agcsel threshold 3 and threshold 2 */
 762 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 763 +               /* enlarge agcsel threshold 5 and threshold 4 */
 764 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 765 +               /* enlarge agcsel threshold 6 */
 766 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 767 +               rt305x_mii_write(esw, 0, 12, 0x7eaa);
 768 +               /* longer TP_IDL tail length */
 769 +               rt305x_mii_write(esw, 0, 14, 0x65);
 770 +               /* increased squelch pulse count threshold. */
 771 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 772 +               /* set TX10 signal amplitude threshold to minimum */
 773 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 774 +               /* set squelch amplitude to higher threshold */
 775 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 776 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 777 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 778 +               /* set PLL/Receive bias current are calibrated */
 779 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 780 +               /* change PLL/Receive bias current to internal(RT3350) */
 781 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 782 +               /* change PLL bias current to internal(RT3052_MP3) */
 783 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 784 +               /* select local register */
 785 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 786 +       } else {
 787 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 788 +               for (i = 0; i < 5; i++) {
 789 +                       if (esw->ports[i].disable) {
 790 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 791 +                       } else {
 792 +                               rt305x_mii_write(esw, i, MII_BMCR,
 793 +                                        BMCR_FULLDPLX |
 794 +                                        BMCR_ANENABLE |
 795 +                                        BMCR_SPEED100);
 796 +                       }
 797 +                       /* TX10 waveform coefficient */
 798 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 799 +                       /* TX100/TX10 AD/DA current bias */
 800 +                       rt305x_mii_write(esw, i, 29, 0x7058);
 801 +                       /* TX100 slew rate control */
 802 +                       rt305x_mii_write(esw, i, 30, 0x0018);
 803 +               }
 804 +
 805 +               /* PHY IOT */
 806 +               /* select global register */
 807 +               rt305x_mii_write(esw, 0, 31, 0x0);
 808 +               /* tune TP_IDL tail and head waveform */
 809 +               rt305x_mii_write(esw, 0, 22, 0x052f);
 810 +               /* set TX10 signal amplitude threshold to minimum */
 811 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 812 +               /* set squelch amplitude to higher threshold */
 813 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 814 +               /* longer TP_IDL tail length */
 815 +               rt305x_mii_write(esw, 0, 14, 0x65);
 816 +               /* select local register */
 817 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 818 +       }
 819 +
 820 +       if (esw->port_map)
 821 +               port_map = esw->port_map;
 822 +       else
 823 +               port_map = RT305X_ESW_PMAP_LLLLLL;
 824 +
 825 +       /*
 826 +        * Unused HW feature, but still nice to be consistent here...
 827 +        * This is also exported to userspace ('lan' attribute) so it's
 828 +        * conveniently usable to decide which ports go into the wan vlan by
 829 +        * default.
 830 +        */
 831 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 832 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 833 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 834 +
 835 +       /* make the switch leds blink */
 836 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
 837 +               esw->ports[i].led = 0x05;
 838 +
 839 +       /* Apply the empty config. */
 840 +       esw_apply_config(&esw->swdev);
 841 +
 842 +       /* Only unmask the port change interrupt */
 843 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
 844 +}
 845 +
 846 +static irqreturn_t esw_interrupt(int irq, void *_esw)
 847 +{
 848 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
 849 +       u32 status;
 850 +
 851 +       status = esw_r32(esw, RT305X_ESW_REG_ISR);
 852 +       if (status & RT305X_ESW_PORT_ST_CHG) {
 853 +               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
 854 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
 855 +               link &= RT305X_ESW_POA_LINK_MASK;
 856 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
 857 +       }
 858 +       esw_w32(esw, status, RT305X_ESW_REG_ISR);
 859 +
 860 +       return IRQ_HANDLED;
 861 +}
 862 +
 863 +static int esw_apply_config(struct switch_dev *dev)
 864 +{
 865 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 866 +       int i;
 867 +       u8 disable = 0;
 868 +       u8 doubletag = 0;
 869 +       u8 en_vlan = 0;
 870 +       u8 untag = 0;
 871 +
 872 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 873 +               u32 vid, vmsc;
 874 +               if (esw->global_vlan_enable) {
 875 +                       vid = esw->vlans[i].vid;
 876 +                       vmsc = esw->vlans[i].ports;
 877 +               } else {
 878 +                       vid = RT305X_ESW_VLAN_NONE;
 879 +                       vmsc = RT305X_ESW_PORTS_NONE;
 880 +               }
 881 +               esw_set_vlan_id(esw, i, vid);
 882 +               esw_set_vmsc(esw, i, vmsc);
 883 +       }
 884 +
 885 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 886 +               u32 pvid;
 887 +               disable |= esw->ports[i].disable << i;
 888 +               if (esw->global_vlan_enable) {
 889 +                       doubletag |= esw->ports[i].doubletag << i;
 890 +                       en_vlan   |= 1                       << i;
 891 +                       untag     |= esw->ports[i].untag     << i;
 892 +                       pvid       = esw->ports[i].pvid;
 893 +               } else {
 894 +                       int x = esw->alt_vlan_disable ? 0 : 1;
 895 +                       doubletag |= x << i;
 896 +                       en_vlan   |= x << i;
 897 +                       untag     |= x << i;
 898 +                       pvid       = 0;
 899 +               }
 900 +               esw_set_pvid(esw, i, pvid);
 901 +               if (i < RT305X_ESW_NUM_LEDS)
 902 +                       esw_w32(esw, esw->ports[i].led,
 903 +                                     RT305X_ESW_REG_P0LED + 4*i);
 904 +       }
 905 +
 906 +       esw_set_gsc(esw);
 907 +       esw_set_port_disable(esw, disable);
 908 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 909 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 910 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
 911 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 912 +       esw_rmw(esw, RT305X_ESW_REG_PFC1,
 913 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 914 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 915 +       esw_rmw(esw, RT305X_ESW_REG_POC2,
 916 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 917 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
 918 +
 919 +       if (!esw->global_vlan_enable) {
 920 +               /*
 921 +                * Still need to put all ports into vlan 0 or they'll be
 922 +                * isolated.
 923 +                * NOTE: vlan 0 is special, no vlan tag is prepended
 924 +                */
 925 +               esw_set_vlan_id(esw, 0, 0);
 926 +               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 927 +       }
 928 +
 929 +       return 0;
 930 +}
 931 +
 932 +static int esw_reset_switch(struct switch_dev *dev)
 933 +{
 934 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 935 +
 936 +       esw->global_vlan_enable = 0;
 937 +       memset(esw->ports, 0, sizeof(esw->ports));
 938 +       memset(esw->vlans, 0, sizeof(esw->vlans));
 939 +       esw_hw_init(esw);
 940 +
 941 +       return 0;
 942 +}
 943 +
 944 +static int esw_get_vlan_enable(struct switch_dev *dev,
 945 +                          const struct switch_attr *attr,
 946 +                          struct switch_val *val)
 947 +{
 948 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 949 +
 950 +       val->value.i = esw->global_vlan_enable;
 951 +
 952 +       return 0;
 953 +}
 954 +
 955 +static int esw_set_vlan_enable(struct switch_dev *dev,
 956 +                          const struct switch_attr *attr,
 957 +                          struct switch_val *val)
 958 +{
 959 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 960 +
 961 +       esw->global_vlan_enable = val->value.i != 0;
 962 +
 963 +       return 0;
 964 +}
 965 +
 966 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
 967 +                               const struct switch_attr *attr,
 968 +                               struct switch_val *val)
 969 +{
 970 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 971 +
 972 +       val->value.i = esw->alt_vlan_disable;
 973 +
 974 +       return 0;
 975 +}
 976 +
 977 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
 978 +                               const struct switch_attr *attr,
 979 +                               struct switch_val *val)
 980 +{
 981 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 982 +
 983 +       esw->alt_vlan_disable = val->value.i != 0;
 984 +
 985 +       return 0;
 986 +}
 987 +
 988 +static int
 989 +rt305x_esw_set_bc_status(struct switch_dev *dev,
 990 +                       const struct switch_attr *attr,
 991 +                       struct switch_val *val)
 992 +{
 993 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 994 +
 995 +       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
 996 +
 997 +       return 0;
 998 +}
 999 +
1000 +static int
1001 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1002 +                       const struct switch_attr *attr,
1003 +                       struct switch_val *val)
1004 +{
1005 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1006 +
1007 +       val->value.i = esw->bc_storm_protect;
1008 +
1009 +       return 0;
1010 +}
1011 +
1012 +static int
1013 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1014 +                       const struct switch_attr *attr,
1015 +                       struct switch_val *val)
1016 +{
1017 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1018 +
1019 +       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1020 +
1021 +       return 0;
1022 +}
1023 +
1024 +static int
1025 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1026 +                       const struct switch_attr *attr,
1027 +                       struct switch_val *val)
1028 +{
1029 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1030 +
1031 +       val->value.i = esw->led_frequency;
1032 +
1033 +       return 0;
1034 +}
1035 +
1036 +static int esw_get_port_link(struct switch_dev *dev,
1037 +                        int port,
1038 +                        struct switch_port_link *link)
1039 +{
1040 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1041 +       u32 speed, poa;
1042 +
1043 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1044 +               return -EINVAL;
1045 +
1046 +       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1047 +
1048 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1049 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1050 +       if (port < RT305X_ESW_NUM_LEDS) {
1051 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
1052 +       } else {
1053 +               if (port == RT305X_ESW_NUM_PORTS - 1)
1054 +                       poa >>= 1;
1055 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
1056 +       }
1057 +       switch (speed) {
1058 +       case 0:
1059 +               link->speed = SWITCH_PORT_SPEED_10;
1060 +               break;
1061 +       case 1:
1062 +               link->speed = SWITCH_PORT_SPEED_100;
1063 +               break;
1064 +       case 2:
1065 +       case 3: /* forced gige speed can be 2 or 3 */
1066 +               link->speed = SWITCH_PORT_SPEED_1000;
1067 +               break;
1068 +       default:
1069 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1070 +               break;
1071 +       }
1072 +
1073 +       return 0;
1074 +}
1075 +
1076 +static int esw_get_port_bool(struct switch_dev *dev,
1077 +                        const struct switch_attr *attr,
1078 +                        struct switch_val *val)
1079 +{
1080 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1081 +       int idx = val->port_vlan;
1082 +       u32 x, reg, shift;
1083 +
1084 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1085 +               return -EINVAL;
1086 +
1087 +       switch (attr->id) {
1088 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1089 +               reg = RT305X_ESW_REG_POC0;
1090 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
1091 +               break;
1092 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1093 +               reg = RT305X_ESW_REG_SGC2;
1094 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1095 +               break;
1096 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1097 +               reg = RT305X_ESW_REG_POC2;
1098 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
1099 +               break;
1100 +       case RT305X_ESW_ATTR_PORT_LAN:
1101 +               reg = RT305X_ESW_REG_SGC2;
1102 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1103 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1104 +                       return -EINVAL;
1105 +               break;
1106 +       default:
1107 +               return -EINVAL;
1108 +       }
1109 +
1110 +       x = esw_r32(esw, reg);
1111 +       val->value.i = (x >> (idx + shift)) & 1;
1112 +
1113 +       return 0;
1114 +}
1115 +
1116 +static int esw_set_port_bool(struct switch_dev *dev,
1117 +                        const struct switch_attr *attr,
1118 +                        struct switch_val *val)
1119 +{
1120 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1121 +       int idx = val->port_vlan;
1122 +
1123 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1124 +           val->value.i < 0 || val->value.i > 1)
1125 +               return -EINVAL;
1126 +
1127 +       switch (attr->id) {
1128 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1129 +               esw->ports[idx].disable = val->value.i;
1130 +               break;
1131 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1132 +               esw->ports[idx].doubletag = val->value.i;
1133 +               break;
1134 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1135 +               esw->ports[idx].untag = val->value.i;
1136 +               break;
1137 +       default:
1138 +               return -EINVAL;
1139 +       }
1140 +
1141 +       return 0;
1142 +}
1143 +
1144 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1145 +                                const struct switch_attr *attr,
1146 +                                struct switch_val *val)
1147 +{
1148 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1149 +       int idx = val->port_vlan;
1150 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1151 +       u32 reg;
1152 +
1153 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1154 +               return -EINVAL;
1155 +       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1156 +       val->value.i = (reg >> shift) & 0xffff;
1157 +
1158 +       return 0;
1159 +}
1160 +
1161 +static int
1162 +esw_get_port_tr_badgood(struct switch_dev *dev,
1163 +                                const struct switch_attr *attr,
1164 +                                struct switch_val *val)
1165 +{
1166 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1167 +
1168 +       int idx = val->port_vlan;
1169 +       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1170 +       u32 reg;
1171 +
1172 +       if (!soc_is_rt5350())
1173 +               return -EINVAL;
1174 +
1175 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1176 +               return -EINVAL;
1177 +
1178 +       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1179 +       val->value.i = (reg >> shift) & 0xffff;
1180 +
1181 +       return 0;
1182 +}
1183 +
1184 +static int esw_get_port_led(struct switch_dev *dev,
1185 +                       const struct switch_attr *attr,
1186 +                       struct switch_val *val)
1187 +{
1188 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1189 +       int idx = val->port_vlan;
1190 +
1191 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1192 +           idx >= RT305X_ESW_NUM_LEDS)
1193 +               return -EINVAL;
1194 +
1195 +       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1196 +
1197 +       return 0;
1198 +}
1199 +
1200 +static int esw_set_port_led(struct switch_dev *dev,
1201 +                       const struct switch_attr *attr,
1202 +                       struct switch_val *val)
1203 +{
1204 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1205 +       int idx = val->port_vlan;
1206 +
1207 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1208 +               return -EINVAL;
1209 +
1210 +       esw->ports[idx].led = val->value.i;
1211 +
1212 +       return 0;
1213 +}
1214 +
1215 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1216 +{
1217 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1218 +
1219 +       if (port >= RT305X_ESW_NUM_PORTS)
1220 +               return -EINVAL;
1221 +
1222 +       *val = esw_get_pvid(esw, port);
1223 +
1224 +       return 0;
1225 +}
1226 +
1227 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1228 +{
1229 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1230 +
1231 +       if (port >= RT305X_ESW_NUM_PORTS)
1232 +               return -EINVAL;
1233 +
1234 +       esw->ports[port].pvid = val;
1235 +
1236 +       return 0;
1237 +}
1238 +
1239 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1240 +{
1241 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1242 +       u32 vmsc, poc2;
1243 +       int vlan_idx = -1;
1244 +       int i;
1245 +
1246 +       val->len = 0;
1247 +
1248 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1249 +               return -EINVAL;
1250 +
1251 +       /* valid vlan? */
1252 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1253 +               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1254 +                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1255 +                       vlan_idx = i;
1256 +                       break;
1257 +               }
1258 +       }
1259 +
1260 +       if (vlan_idx == -1)
1261 +               return -EINVAL;
1262 +
1263 +       vmsc = esw_get_vmsc(esw, vlan_idx);
1264 +       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1265 +
1266 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1267 +               struct switch_port *p;
1268 +               int port_mask = 1 << i;
1269 +
1270 +               if (!(vmsc & port_mask))
1271 +                       continue;
1272 +
1273 +               p = &val->value.ports[val->len++];
1274 +               p->id = i;
1275 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1276 +                       p->flags = 0;
1277 +               else
1278 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1279 +       }
1280 +
1281 +       return 0;
1282 +}
1283 +
1284 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1285 +{
1286 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1287 +       int ports;
1288 +       int vlan_idx = -1;
1289 +       int i;
1290 +
1291 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1292 +           val->len > RT305X_ESW_NUM_PORTS)
1293 +               return -EINVAL;
1294 +
1295 +       /* one of the already defined vlans? */
1296 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1297 +               if (esw->vlans[i].vid == val->port_vlan &&
1298 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1299 +                       vlan_idx = i;
1300 +                       break;
1301 +               }
1302 +       }
1303 +
1304 +       /* select a free slot */
1305 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1306 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1307 +                       vlan_idx = i;
1308 +       }
1309 +
1310 +       /* bail if all slots are in use */
1311 +       if (vlan_idx == -1)
1312 +               return -EINVAL;
1313 +
1314 +       ports = RT305X_ESW_PORTS_NONE;
1315 +       for (i = 0; i < val->len; i++) {
1316 +               struct switch_port *p = &val->value.ports[i];
1317 +               int port_mask = 1 << p->id;
1318 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1319 +
1320 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1321 +                       return -EINVAL;
1322 +
1323 +               ports |= port_mask;
1324 +               esw->ports[p->id].untag = untagged;
1325 +       }
1326 +       esw->vlans[vlan_idx].ports = ports;
1327 +       if (ports == RT305X_ESW_PORTS_NONE)
1328 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1329 +       else
1330 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1331 +
1332 +       return 0;
1333 +}
1334 +
1335 +static const struct switch_attr esw_global[] = {
1336 +       {
1337 +               .type = SWITCH_TYPE_INT,
1338 +               .name = "enable_vlan",
1339 +               .description = "VLAN mode (1:enabled)",
1340 +               .max = 1,
1341 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1342 +               .get = esw_get_vlan_enable,
1343 +               .set = esw_set_vlan_enable,
1344 +       },
1345 +       {
1346 +               .type = SWITCH_TYPE_INT,
1347 +               .name = "alternate_vlan_disable",
1348 +               .description = "Use en_vlan instead of doubletag to disable"
1349 +                               " VLAN mode",
1350 +               .max = 1,
1351 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1352 +               .get = esw_get_alt_vlan_disable,
1353 +               .set = esw_set_alt_vlan_disable,
1354 +       },
1355 +       {
1356 +               .type = SWITCH_TYPE_INT,
1357 +               .name = "bc_storm_protect",
1358 +               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1359 +               .max = 3,
1360 +               .id = RT305X_ESW_ATTR_BC_STATUS,
1361 +               .get = rt305x_esw_get_bc_status,
1362 +               .set = rt305x_esw_set_bc_status,
1363 +       },
1364 +       {
1365 +               .type = SWITCH_TYPE_INT,
1366 +               .name = "led_frequency",
1367 +               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1368 +               .max = 3,
1369 +               .id = RT305X_ESW_ATTR_LED_FREQ,
1370 +               .get = rt305x_esw_get_led_freq,
1371 +               .set = rt305x_esw_set_led_freq,
1372 +       }
1373 +};
1374 +
1375 +static const struct switch_attr esw_port[] = {
1376 +       {
1377 +               .type = SWITCH_TYPE_INT,
1378 +               .name = "disable",
1379 +               .description = "Port state (1:disabled)",
1380 +               .max = 1,
1381 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1382 +               .get = esw_get_port_bool,
1383 +               .set = esw_set_port_bool,
1384 +       },
1385 +       {
1386 +               .type = SWITCH_TYPE_INT,
1387 +               .name = "doubletag",
1388 +               .description = "Double tagging for incoming vlan packets "
1389 +                               "(1:enabled)",
1390 +               .max = 1,
1391 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1392 +               .get = esw_get_port_bool,
1393 +               .set = esw_set_port_bool,
1394 +       },
1395 +       {
1396 +               .type = SWITCH_TYPE_INT,
1397 +               .name = "untag",
1398 +               .description = "Untag (1:strip outgoing vlan tag)",
1399 +               .max = 1,
1400 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1401 +               .get = esw_get_port_bool,
1402 +               .set = esw_set_port_bool,
1403 +       },
1404 +       {
1405 +               .type = SWITCH_TYPE_INT,
1406 +               .name = "led",
1407 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1408 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1409 +                               " 8:100mact, 10:blink, 11:off, 12:on)",
1410 +               .max = 15,
1411 +               .id = RT305X_ESW_ATTR_PORT_LED,
1412 +               .get = esw_get_port_led,
1413 +               .set = esw_set_port_led,
1414 +       },
1415 +       {
1416 +               .type = SWITCH_TYPE_INT,
1417 +               .name = "lan",
1418 +               .description = "HW port group (0:wan, 1:lan)",
1419 +               .max = 1,
1420 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1421 +               .get = esw_get_port_bool,
1422 +       },
1423 +       {
1424 +               .type = SWITCH_TYPE_INT,
1425 +               .name = "recv_bad",
1426 +               .description = "Receive bad packet counter",
1427 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1428 +               .get = esw_get_port_recv_badgood,
1429 +       },
1430 +       {
1431 +               .type = SWITCH_TYPE_INT,
1432 +               .name = "recv_good",
1433 +               .description = "Receive good packet counter",
1434 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1435 +               .get = esw_get_port_recv_badgood,
1436 +       },
1437 +       {
1438 +               .type = SWITCH_TYPE_INT,
1439 +               .name = "tr_bad",
1440 +
1441 +               .description = "Transmit bad packet counter. rt5350 only",
1442 +               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1443 +               .get = esw_get_port_tr_badgood,
1444 +       },
1445 +       {
1446 +               .type = SWITCH_TYPE_INT,
1447 +               .name = "tr_good",
1448 +
1449 +               .description = "Transmit good packet counter. rt5350 only",
1450 +               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1451 +               .get = esw_get_port_tr_badgood,
1452 +       },
1453 +};
1454 +
1455 +static const struct switch_attr esw_vlan[] = {
1456 +};
1457 +
1458 +static const struct switch_dev_ops esw_ops = {
1459 +       .attr_global = {
1460 +               .attr = esw_global,
1461 +               .n_attr = ARRAY_SIZE(esw_global),
1462 +       },
1463 +       .attr_port = {
1464 +               .attr = esw_port,
1465 +               .n_attr = ARRAY_SIZE(esw_port),
1466 +       },
1467 +       .attr_vlan = {
1468 +               .attr = esw_vlan,
1469 +               .n_attr = ARRAY_SIZE(esw_vlan),
1470 +       },
1471 +       .get_vlan_ports = esw_get_vlan_ports,
1472 +       .set_vlan_ports = esw_set_vlan_ports,
1473 +       .get_port_pvid = esw_get_port_pvid,
1474 +       .set_port_pvid = esw_set_port_pvid,
1475 +       .get_port_link = esw_get_port_link,
1476 +       .apply_config = esw_apply_config,
1477 +       .reset_switch = esw_reset_switch,
1478 +};
1479 +
1480 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1481 +       /* All ports are LAN ports. */
1482 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1483 +       .reg_initval_fct2       = 0x00d6500c,
1484 +       /*
1485 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1486 +        * turbo mii off, rgmi 3.3v off
1487 +        * port5: disabled
1488 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1489 +        */
1490 +       .reg_initval_fpa2       = 0x3f502b28,
1491 +};
1492 +
1493 +static const struct of_device_id ralink_esw_match[] = {
1494 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1495 +       {},
1496 +};
1497 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1498 +
1499 +static int esw_probe(struct platform_device *pdev)
1500 +{
1501 +       struct device_node *np = pdev->dev.of_node;
1502 +       const struct rt305x_esw_platform_data *pdata;
1503 +       const __be32 *port_map, *reg_init;
1504 +       struct rt305x_esw *esw;
1505 +       struct switch_dev *swdev;
1506 +       struct resource *res, *irq;
1507 +       int err;
1508 +
1509 +       pdata = pdev->dev.platform_data;
1510 +       if (!pdata) {
1511 +               const struct of_device_id *match;
1512 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1513 +               if (match)
1514 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1515 +       }
1516 +       if (!pdata)
1517 +               return -EINVAL;
1518 +
1519 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1520 +       if (!res) {
1521 +               dev_err(&pdev->dev, "no memory resource found\n");
1522 +               return -ENOMEM;
1523 +       }
1524 +
1525 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1526 +       if (!irq) {
1527 +               dev_err(&pdev->dev, "no irq resource found\n");
1528 +               return -ENOMEM;
1529 +       }
1530 +
1531 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1532 +       if (!esw) {
1533 +               dev_err(&pdev->dev, "no memory for private data\n");
1534 +               return -ENOMEM;
1535 +       }
1536 +
1537 +       esw->dev = &pdev->dev;
1538 +       esw->irq = irq->start;
1539 +       esw->base = ioremap(res->start, resource_size(res));
1540 +       if (!esw->base) {
1541 +               dev_err(&pdev->dev, "ioremap failed\n");
1542 +               err = -ENOMEM;
1543 +               goto free_esw;
1544 +       }
1545 +
1546 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1547 +        if (port_map)
1548 +               esw->port_map = be32_to_cpu(*port_map);
1549 +
1550 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1551 +        if (reg_init)
1552 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1553 +
1554 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1555 +        if (reg_init)
1556 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1557 +
1558 +       reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1559 +        if (reg_init)
1560 +               esw->reg_led_polarity = be32_to_cpu(*reg_init);
1561 +
1562 +       swdev = &esw->swdev;
1563 +       swdev->of_node = pdev->dev.of_node;
1564 +       swdev->name = "rt305x-esw";
1565 +       swdev->alias = "rt305x";
1566 +       swdev->cpu_port = RT305X_ESW_PORT6;
1567 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1568 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1569 +       swdev->ops = &esw_ops;
1570 +
1571 +       err = register_switch(swdev, NULL);
1572 +       if (err < 0) {
1573 +               dev_err(&pdev->dev, "register_switch failed\n");
1574 +               goto unmap_base;
1575 +       }
1576 +
1577 +       platform_set_drvdata(pdev, esw);
1578 +
1579 +       esw->pdata = pdata;
1580 +       spin_lock_init(&esw->reg_rw_lock);
1581 +
1582 +       esw_hw_init(esw);
1583 +
1584 +       esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1585 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1586 +       request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1587 +
1588 +       return 0;
1589 +
1590 +unmap_base:
1591 +       iounmap(esw->base);
1592 +free_esw:
1593 +       kfree(esw);
1594 +       return err;
1595 +}
1596 +
1597 +static int esw_remove(struct platform_device *pdev)
1598 +{
1599 +       struct rt305x_esw *esw;
1600 +
1601 +       esw = platform_get_drvdata(pdev);
1602 +       if (esw) {
1603 +               unregister_switch(&esw->swdev);
1604 +               platform_set_drvdata(pdev, NULL);
1605 +               iounmap(esw->base);
1606 +               kfree(esw);
1607 +       }
1608 +
1609 +       return 0;
1610 +}
1611 +
1612 +static struct platform_driver esw_driver = {
1613 +       .probe = esw_probe,
1614 +       .remove = esw_remove,
1615 +       .driver = {
1616 +               .name = "rt305x-esw",
1617 +               .owner = THIS_MODULE,
1618 +               .of_match_table = ralink_esw_match,
1619 +       },
1620 +};
1621 +
1622 +int __init rtesw_init(void)
1623 +{
1624 +       return platform_driver_register(&esw_driver);
1625 +}
1626 +
1627 +void rtesw_exit(void)
1628 +{
1629 +       platform_driver_unregister(&esw_driver);
1630 +}
1631 --- /dev/null
1632 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1633 @@ -0,0 +1,32 @@
1634 +/*
1635 + *   This program is free software; you can redistribute it and/or modify
1636 + *   it under the terms of the GNU General Public License as published by
1637 + *   the Free Software Foundation; version 2 of the License
1638 + *
1639 + *   This program is distributed in the hope that it will be useful,
1640 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1641 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1642 + *   GNU General Public License for more details.
1643 + *
1644 + *   You should have received a copy of the GNU General Public License
1645 + *   along with this program; if not, write to the Free Software
1646 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1647 + *
1648 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1649 + */
1650 +
1651 +#ifndef _RALINK_ESW_RT3052_H__
1652 +#define _RALINK_ESW_RT3052_H__
1653 +
1654 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1655 +
1656 +int __init rtesw_init(void);
1657 +void rtesw_exit(void);
1658 +
1659 +#else
1660 +
1661 +static inline int __init rtesw_init(void) { return 0; }
1662 +static inline void rtesw_exit(void) { }
1663 +
1664 +#endif
1665 +#endif
1666 --- /dev/null
1667 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1668 @@ -0,0 +1,1027 @@
1669 +/*
1670 + *   This program is free software; you can redistribute it and/or modify
1671 + *   it under the terms of the GNU General Public License as published by
1672 + *   the Free Software Foundation; version 2 of the License
1673 + *
1674 + *   This program is distributed in the hope that it will be useful,
1675 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1676 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1677 + *   GNU General Public License for more details.
1678 + *
1679 + *   You should have received a copy of the GNU General Public License
1680 + *   along with this program; if not, write to the Free Software
1681 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1682 + *
1683 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1684 + */
1685 +
1686 +#include <linux/module.h>
1687 +#include <linux/kernel.h>
1688 +#include <linux/types.h>
1689 +#include <linux/dma-mapping.h>
1690 +#include <linux/init.h>
1691 +#include <linux/skbuff.h>
1692 +#include <linux/etherdevice.h>
1693 +#include <linux/ethtool.h>
1694 +#include <linux/platform_device.h>
1695 +#include <linux/of_device.h>
1696 +#include <linux/clk.h>
1697 +#include <linux/of_net.h>
1698 +#include <linux/of_mdio.h>
1699 +#include <linux/of_irq.h>
1700 +#include <linux/of_address.h>
1701 +#include <linux/switch.h>
1702 +
1703 +#include <asm/mach-ralink/ralink_regs.h>
1704 +
1705 +#include "ralink_soc_eth.h"
1706 +
1707 +#include <linux/ioport.h>
1708 +#include <linux/switch.h>
1709 +#include <linux/mii.h>
1710 +
1711 +#include <ralink_regs.h>
1712 +#include <asm/mach-ralink/mt7620.h>
1713 +
1714 +#include "ralink_soc_eth.h"
1715 +#include "gsw_mt7620a.h"
1716 +#include "mdio.h"
1717 +
1718 +#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
1719 +
1720 +#define MT7620A_GSW_REG_PIAC   0x7004
1721 +
1722 +#define GSW_NUM_VLANS          16
1723 +#define GSW_NUM_VIDS           4096
1724 +#define GSW_NUM_PORTS          7
1725 +#define GSW_PORT6              6
1726 +
1727 +#define GSW_MDIO_ACCESS                BIT(31)
1728 +#define GSW_MDIO_READ          BIT(19)
1729 +#define GSW_MDIO_WRITE         BIT(18)
1730 +#define GSW_MDIO_START         BIT(16)
1731 +#define GSW_MDIO_ADDR_SHIFT    20
1732 +#define GSW_MDIO_REG_SHIFT     25
1733 +
1734 +#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
1735 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1736 +#define GSW_REG_SMACCR0                0x3fE4
1737 +#define GSW_REG_SMACCR1                0x3fE8
1738 +#define GSW_REG_CKGCR          0x3ff0
1739 +
1740 +#define GSW_REG_IMR            0x7008
1741 +#define GSW_REG_ISR            0x700c
1742 +
1743 +#define SYSC_REG_CFG1          0x14
1744 +
1745 +#define PORT_IRQ_ST_CHG                0x7f
1746 +
1747 +#define GSW_VLAN_VTCR          0x90
1748 +#define GSW_VLAN_VTCR_VID_M    0xfff
1749 +#define GSW_VLAN_ID(_x)                (0x100 + (4 * (_x)))
1750 +#define GSW_VLAN_ID_VID_S      12
1751 +#define GSW_VLAN_ID_VID_M      0xfff
1752 +
1753 +#define GSW_VAWD1              0x94
1754 +#define GSW_VAWD1_VTAG_EN      BIT(28)
1755 +#define GSW_VAWD1_PORTM_S      16
1756 +#define GSW_VAWD1_PORTM_M      0xff
1757 +
1758 +#define GSW_VAWD2              0x98
1759 +#define GSW_VAWD2_PORTT_S      16
1760 +#define GSW_VAWD2_PORTT_M      0xff
1761 +
1762 +#define GSW_VTIM(_x)           (0x100 + (4 * (_x)))
1763 +#define GSW_VTIM_M             0xfff
1764 +#define GSW_VTIM_S             12
1765 +
1766 +#define GSW_REG_PCR(x)         (0x2004 + (x * 0x100))
1767 +#define GSW_REG_PCR_EG_TAG_S   28
1768 +#define GSW_REG_PCR_EG_TAG_M   0x3
1769 +
1770 +#define SYSCFG1                        0x14
1771 +
1772 +#define ESW_PHY_POLLING                0x7000
1773 +
1774 +#define        PMCR_IPG                BIT(18)
1775 +#define        PMCR_MAC_MODE           BIT(16)
1776 +#define        PMCR_FORCE              BIT(15)
1777 +#define        PMCR_TX_EN              BIT(14)
1778 +#define        PMCR_RX_EN              BIT(13)
1779 +#define        PMCR_BACKOFF            BIT(9)
1780 +#define        PMCR_BACKPRES           BIT(8)
1781 +#define        PMCR_RX_FC              BIT(5)
1782 +#define        PMCR_TX_FC              BIT(4)
1783 +#define        PMCR_SPEED(_x)          (_x << 2)
1784 +#define        PMCR_DUPLEX             BIT(1)
1785 +#define        PMCR_LINK               BIT(0)
1786 +
1787 +#define PHY_AN_EN              BIT(31)
1788 +#define PHY_PRE_EN             BIT(30)
1789 +#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
1790 +
1791 +enum {
1792 +       /* Global attributes. */
1793 +       GSW_ATTR_ENABLE_VLAN,
1794 +       /* Port attributes. */
1795 +       GSW_ATTR_PORT_UNTAG,
1796 +};
1797 +
1798 +enum {
1799 +       PORT4_EPHY = 0,
1800 +       PORT4_EXT,
1801 +};
1802 +
1803 +struct gsw_port {
1804 +       bool    disable;
1805 +       bool    untag;
1806 +       u16     pvid;
1807 +};
1808 +
1809 +struct gsw_vlan {
1810 +       u8      ports;
1811 +       u16     vid;
1812 +};
1813 +
1814 +struct mt7620_gsw {
1815 +       struct device           *dev;
1816 +       void __iomem            *base;
1817 +       int                     irq;
1818 +
1819 +       struct switch_dev       swdev;
1820 +       bool                    global_vlan_enable;
1821 +       struct gsw_vlan         vlans[GSW_NUM_VLANS];
1822 +       struct gsw_port         ports[GSW_NUM_PORTS];
1823 +       long unsigned int       autopoll;
1824 +       int                     port4;
1825 +};
1826 +
1827 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1828 +{
1829 +       iowrite32(val, gsw->base + reg);
1830 +}
1831 +
1832 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1833 +{
1834 +       return ioread32(gsw->base + reg);
1835 +}
1836 +
1837 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1838 +{
1839 +       unsigned long t_start = jiffies;
1840 +
1841 +       while (1) {
1842 +               if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1843 +                       return 0;
1844 +               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1845 +                       break;
1846 +               }
1847 +       }
1848 +
1849 +       printk(KERN_ERR "mdio: MDIO timeout\n");
1850 +       return -1;
1851 +}
1852 +
1853 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1854 +                               u32 write_data)
1855 +{
1856 +       if (mt7620_mii_busy_wait(gsw))
1857 +               return -1;
1858 +
1859 +       write_data &= 0xffff;
1860 +
1861 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1862 +               (phy_register << GSW_MDIO_REG_SHIFT) |
1863 +               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1864 +               MT7620A_GSW_REG_PIAC);
1865 +
1866 +       if (mt7620_mii_busy_wait(gsw))
1867 +               return -1;
1868 +
1869 +       return 0;
1870 +}
1871 +
1872 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1873 +{
1874 +       struct fe_priv *priv = bus->priv;
1875 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1876 +
1877 +       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1878 +}
1879 +
1880 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1881 +{
1882 +       struct fe_priv *priv = bus->priv;
1883 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1884 +       u32 d;
1885 +
1886 +       if (mt7620_mii_busy_wait(gsw))
1887 +               return 0xffff;
1888 +
1889 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1890 +               (phy_reg << GSW_MDIO_REG_SHIFT) |
1891 +               (phy_addr << GSW_MDIO_ADDR_SHIFT),
1892 +               MT7620A_GSW_REG_PIAC);
1893 +
1894 +       if (mt7620_mii_busy_wait(gsw))
1895 +               return 0xffff;
1896 +
1897 +       d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1898 +
1899 +       return d;
1900 +}
1901 +
1902 +static unsigned char *fe_speed_str(int speed)
1903 +{
1904 +       switch (speed) {
1905 +       case 2:
1906 +       case SPEED_1000:
1907 +               return "1000";
1908 +       case 1:
1909 +       case SPEED_100:
1910 +               return "100";
1911 +       case 0:
1912 +       case SPEED_10:
1913 +               return "10";
1914 +       }
1915 +
1916 +       return "? ";
1917 +}
1918 +
1919 +int mt7620a_has_carrier(struct fe_priv *priv)
1920 +{
1921 +        struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1922 +       int i;
1923 +
1924 +       for (i = 0; i < GSW_PORT6; i++)
1925 +               if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1926 +                       return 1;
1927 +       return 0;
1928 +}
1929 +
1930 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1931 +{
1932 +       if (!priv->phy)
1933 +               return;
1934 +
1935 +       if (mt7620a_has_carrier(priv))
1936 +               netif_carrier_on(priv->netdev);
1937 +       else
1938 +               netif_carrier_off(priv->netdev);
1939 +}
1940 +
1941 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1942 +{
1943 +       if (priv->link[port])
1944 +               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1945 +                       port, fe_speed_str(priv->phy->speed[port]),
1946 +                       (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1947 +       else
1948 +               netdev_info(priv->netdev, "port %d link down\n", port);
1949 +       mt7620a_handle_carrier(priv);
1950 +}
1951 +
1952 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1953 +{
1954 +       struct fe_priv *priv = (struct fe_priv *) _priv;
1955 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1956 +       u32 status;
1957 +       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1958 +
1959 +       status = gsw_r32(gsw, GSW_REG_ISR);
1960 +       if (status & PORT_IRQ_ST_CHG)
1961 +               for (i = 0; i <= max; i++) {
1962 +                       u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1963 +                       int link = status & 0x1;
1964 +
1965 +                       if (link != priv->link[i]) {
1966 +                               if (link)
1967 +                                       netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1968 +                                                       i, fe_speed_str((status >> 2) & 3),
1969 +                                                       (status & 0x2) ? "Full" : "Half");
1970 +                               else
1971 +                                       netdev_info(priv->netdev, "port %d link down\n", i);
1972 +                       }
1973 +
1974 +                       priv->link[i] = link;
1975 +               }
1976 +       mt7620a_handle_carrier(priv);
1977 +
1978 +       gsw_w32(gsw, status, GSW_REG_ISR);
1979 +
1980 +       return IRQ_HANDLED;
1981 +}
1982 +
1983 +static int mt7620_is_bga(void)
1984 +{
1985 +       u32 bga = rt_sysc_r32(0x0c);
1986 +
1987 +       return (bga >> 16) & 1;
1988 +}
1989 +
1990 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1991 +{
1992 +       int phy;
1993 +       int lsb = -1, msb = 0;
1994 +
1995 +       for_each_set_bit(phy, &gsw->autopoll, 32) {
1996 +               if (lsb < 0)
1997 +                       lsb = phy;
1998 +               msb = phy;
1999 +       }
2000 +
2001 +       gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
2002 +}
2003 +
2004 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
2005 +{
2006 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2007 +       const __be32 *_id = of_get_property(np, "reg", NULL);
2008 +       int phy_mode, size, id;
2009 +       int shift = 12;
2010 +       u32 val, mask = 0;
2011 +       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2012 +
2013 +       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2014 +               if (_id)
2015 +                       pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2016 +               else
2017 +                       pr_err("%s: invalid port id\n", np->name);
2018 +               return;
2019 +       }
2020 +
2021 +       id = be32_to_cpu(*_id);
2022 +
2023 +       if (id == 4)
2024 +               shift = 14;
2025 +
2026 +       priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2027 +       if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2028 +               pr_err("%s: invalid fixed link property\n", np->name);
2029 +               priv->phy->phy_fixed[id] = NULL;
2030 +               return;
2031 +       }
2032 +
2033 +       phy_mode = of_get_phy_mode(np);
2034 +       switch (phy_mode) {
2035 +       case PHY_INTERFACE_MODE_RGMII:
2036 +               mask = 0;
2037 +               break;
2038 +       case PHY_INTERFACE_MODE_MII:
2039 +               mask = 1;
2040 +               break;
2041 +       case PHY_INTERFACE_MODE_RMII:
2042 +               mask = 2;
2043 +               break;
2044 +       default:
2045 +               dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[id]);
2046 +               return;
2047 +       }
2048 +
2049 +       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2050 +       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2051 +               return;
2052 +
2053 +       val = rt_sysc_r32(SYSCFG1);
2054 +       val &= ~(3 << shift);
2055 +       val |= mask << shift;
2056 +       rt_sysc_w32(val, SYSCFG1);
2057 +
2058 +       if (priv->phy->phy_fixed[id]) {
2059 +               const __be32 *link = priv->phy->phy_fixed[id];
2060 +               int tx_fc = be32_to_cpup(link++);
2061 +               int rx_fc = be32_to_cpup(link++);
2062 +               u32 val = 0;
2063 +
2064 +               priv->phy->speed[id] = be32_to_cpup(link++);
2065 +               priv->phy->duplex[id] = be32_to_cpup(link++);
2066 +               priv->link[id] = 1;
2067 +
2068 +               switch (priv->phy->speed[id]) {
2069 +               case SPEED_10:
2070 +                       val = 0;
2071 +                       break;
2072 +               case SPEED_100:
2073 +                       val = 1;
2074 +                       break;
2075 +               case SPEED_1000:
2076 +                       val = 2;
2077 +                       break;
2078 +               default:
2079 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2080 +                       priv->phy->phy_fixed[id] = 0;
2081 +                       return;
2082 +               }
2083 +               val = PMCR_SPEED(val);
2084 +               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2085 +                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2086 +               if (tx_fc)
2087 +                       val |= PMCR_TX_FC;
2088 +               if (rx_fc)
2089 +                       val |= PMCR_RX_FC;
2090 +               if (priv->phy->duplex[id])
2091 +                       val |= PMCR_DUPLEX;
2092 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2093 +               dev_info(priv->device, "using fixed link parameters\n");
2094 +               return;
2095 +       }
2096 +
2097 +       if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2098 +               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2099 +                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
2100 +
2101 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2102 +               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2103 +               gsw->autopoll |= BIT(id);
2104 +               gsw_auto_poll(gsw);
2105 +               return;
2106 +       }
2107 +}
2108 +
2109 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2110 +{
2111 +       u32 is_BGA = mt7620_is_bga();
2112 +
2113 +       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2114 +       gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2115 +
2116 +       /*correct  PHY  setting L3.0 BGA*/
2117 +       _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2118 +
2119 +       _mt7620_mii_write(gsw, 1, 17, 0x7444);
2120 +       if (is_BGA)
2121 +               _mt7620_mii_write(gsw, 1, 19, 0x0114);
2122 +       else
2123 +               _mt7620_mii_write(gsw, 1, 19, 0x0117);
2124 +
2125 +       _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2126 +       _mt7620_mii_write(gsw, 1, 25, 0x6212);
2127 +       _mt7620_mii_write(gsw, 1, 26, 0x0777);
2128 +       _mt7620_mii_write(gsw, 1, 29, 0x4000);
2129 +       _mt7620_mii_write(gsw, 1, 28, 0xc077);
2130 +       _mt7620_mii_write(gsw, 1, 24, 0x0000);
2131 +
2132 +       _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2133 +       _mt7620_mii_write(gsw, 1, 17, 0x4838);
2134 +
2135 +       _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2136 +       if (is_BGA) {
2137 +               _mt7620_mii_write(gsw, 1, 21, 0x0515);
2138 +               _mt7620_mii_write(gsw, 1, 22, 0x0053);
2139 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2140 +               _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2141 +               _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2142 +               _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2143 +       } else {
2144 +               _mt7620_mii_write(gsw, 1, 21, 0x0517);
2145 +               _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2146 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2147 +               _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2148 +               _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2149 +               _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2150 +       }
2151 +       _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2152 +       _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2153 +
2154 +       _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2155 +       _mt7620_mii_write(gsw, 0, 30, 0xa000);
2156 +       _mt7620_mii_write(gsw, 1, 30, 0xa000);
2157 +       _mt7620_mii_write(gsw, 2, 30, 0xa000);
2158 +       _mt7620_mii_write(gsw, 3, 30, 0xa000);
2159 +
2160 +       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2161 +       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2162 +       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2163 +       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2164 +       _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2165 +       _mt7620_mii_write(gsw, 0, 16, 0x1111);
2166 +       _mt7620_mii_write(gsw, 1, 16, 0x1010);
2167 +       _mt7620_mii_write(gsw, 2, 16, 0x1515);
2168 +       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2169 +
2170 +       /* CPU Port6 Force Link 1G, FC ON */
2171 +       gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2172 +       /* Set Port6 CPU Port */
2173 +       gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2174 +
2175 +//     GSW_VAWD2
2176 +
2177 +       /* setup port 4 */
2178 +       if (gsw->port4 == PORT4_EPHY) {
2179 +               u32 val = rt_sysc_r32(SYSCFG1);
2180 +               val |= 3 << 14;
2181 +               rt_sysc_w32(val, SYSCFG1);
2182 +               _mt7620_mii_write(gsw, 4, 30, 0xa000);
2183 +               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2184 +               _mt7620_mii_write(gsw, 4, 16, 0x1313);
2185 +               pr_info("gsw: setting port4 to ephy mode\n");
2186 +       }
2187 +}
2188 +
2189 +static int gsw_reset_switch(struct switch_dev *dev)
2190 +{
2191 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2192 +
2193 +       gsw->global_vlan_enable = 0;
2194 +       memset(gsw->ports, 0, sizeof(gsw->ports));
2195 +       memset(gsw->vlans, 0, sizeof(gsw->vlans));
2196 +       gsw_hw_init(gsw);
2197 +
2198 +       return 0;
2199 +}
2200 +
2201 +static int gsw_get_vlan_enable(struct switch_dev *dev,
2202 +                          const struct switch_attr *attr,
2203 +                          struct switch_val *val)
2204 +{
2205 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2206 +
2207 +       val->value.i = gsw->global_vlan_enable;
2208 +
2209 +       return 0;
2210 +}
2211 +
2212 +static int gsw_set_vlan_enable(struct switch_dev *dev,
2213 +                          const struct switch_attr *attr,
2214 +                          struct switch_val *val)
2215 +{
2216 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2217 +
2218 +       gsw->global_vlan_enable = val->value.i != 0;
2219 +
2220 +       return 0;
2221 +}
2222 +
2223 +static unsigned gsw_get_pvid(struct mt7620_gsw *gsw, unsigned port)
2224 +{
2225 +       unsigned s, val;
2226 +
2227 +       s = GSW_VTIM_S * (port % 2);
2228 +       val = gsw_r32(gsw, GSW_VTIM(port / 2));
2229 +
2230 +       return (val >> s) & GSW_VTIM_M;
2231 +}
2232 +
2233 +static void gsw_set_pvid(struct mt7620_gsw *gsw, unsigned port, unsigned pvid)
2234 +{
2235 +       unsigned s, val;
2236 +
2237 +       s = GSW_VTIM_S * (port % 2);
2238 +       val = gsw_r32(gsw, GSW_VTIM(port / 2));
2239 +       val &= ~(GSW_VTIM_M << s);
2240 +       val |= (pvid && GSW_VTIM_M) << s;
2241 +       gsw_w32(gsw, val, GSW_VTIM(port / 2));
2242 +}
2243 +
2244 +static int gsw_get_port_bool(struct switch_dev *dev,
2245 +                        const struct switch_attr *attr,
2246 +                        struct switch_val *val)
2247 +{
2248 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2249 +       int idx = val->port_vlan;
2250 +
2251 +       if (idx < 0 || idx >= GSW_NUM_PORTS)
2252 +               return -EINVAL;
2253 +
2254 +       switch (attr->id) {
2255 +       case GSW_ATTR_PORT_UNTAG:
2256 +               return gsw->ports[idx].untag;
2257 +       }
2258 +
2259 +       return -EINVAL;
2260 +}
2261 +
2262 +static int gsw_get_port_pvid(struct switch_dev *dev, int port, int *val)
2263 +{
2264 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2265 +
2266 +       if (port >= GSW_NUM_PORTS)
2267 +               return -EINVAL;
2268 +
2269 +       *val = gsw_get_pvid(gsw, port);
2270 +
2271 +       return 0;
2272 +}
2273 +
2274 +static int gsw_set_port_pvid(struct switch_dev *dev, int port, int val)
2275 +{
2276 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2277 +
2278 +       if (port >= GSW_NUM_PORTS)
2279 +               return -EINVAL;
2280 +
2281 +       gsw->ports[port].pvid = val;
2282 +
2283 +       return 0;
2284 +}
2285 +
2286 +static void gsw_set_vtcr(struct switch_dev *dev, u32 vid)
2287 +{
2288 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2289 +       int retry = 1000;
2290 +
2291 +       gsw_w32(gsw, 0x80000000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2292 +       while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2293 +               ;
2294 +}
2295 +
2296 +static void gsw_apply_vtcr(struct switch_dev *dev, u32 vid)
2297 +{
2298 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2299 +       int retry = 1000;
2300 +
2301 +       gsw_w32(gsw, 0x80001000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2302 +       while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2303 +               ;
2304 +}
2305 +
2306 +static unsigned gsw_get_vlan_id(struct mt7620_gsw *gsw, unsigned vlan)
2307 +{
2308 +       unsigned s;
2309 +       unsigned val;
2310 +
2311 +       s = GSW_VLAN_ID_VID_S * (vlan % 2);
2312 +       val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2313 +       val = (val >> s) & GSW_VLAN_ID_VID_M;
2314 +
2315 +       return val;
2316 +}
2317 +
2318 +static void gsw_set_vlan_id(struct mt7620_gsw *gsw, unsigned vlan, unsigned vid)
2319 +{
2320 +       unsigned s;
2321 +       unsigned val;
2322 +
2323 +       s = GSW_VLAN_ID_VID_S * (vlan % 2);
2324 +       val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2325 +       val &= ~(GSW_VLAN_ID_VID_M << s);
2326 +       val |= (vid << s);
2327 +       gsw_w32(gsw, val, GSW_VLAN_ID(vlan / 2));
2328 +}
2329 +
2330 +static void gsw_vlan_tagging_enable(struct mt7620_gsw *gsw, unsigned vlan, unsigned enable)
2331 +{
2332 +       unsigned val;
2333 +
2334 +       val = gsw_r32(gsw, GSW_VAWD1);
2335 +       if (enable)
2336 +               val |= GSW_VAWD1_VTAG_EN;
2337 +       else
2338 +               val &= ~GSW_VAWD1_VTAG_EN;
2339 +       gsw_w32(gsw, val, GSW_VAWD1);
2340 +}
2341 +
2342 +static unsigned gsw_get_port_member(struct mt7620_gsw *gsw, unsigned vlan)
2343 +{
2344 +       unsigned val;
2345 +
2346 +       gsw_set_vtcr(&gsw->swdev, vlan);
2347 +
2348 +       val = gsw_r32(gsw, GSW_VAWD1);
2349 +       val = (val >> GSW_VAWD1_PORTM_S) & GSW_VAWD1_PORTM_M;
2350 +
2351 +       return val;
2352 +}
2353 +
2354 +static void gsw_set_port_member(struct mt7620_gsw *gsw, unsigned vlan, unsigned member)
2355 +{
2356 +       unsigned val;
2357 +
2358 +       val = gsw_r32(gsw, GSW_VAWD1);
2359 +       val = ~(GSW_VAWD1_PORTM_M << GSW_VAWD1_PORTM_S);
2360 +       val |= (member & GSW_VAWD1_PORTM_M) << GSW_VAWD1_PORTM_S;
2361 +        gsw_w32(gsw, val, GSW_VAWD1);
2362 +}
2363 +
2364 +static unsigned gsw_get_port_tag(struct mt7620_gsw *gsw, unsigned port)
2365 +{
2366 +       unsigned val;
2367 +
2368 +       val = gsw_r32(gsw, GSW_REG_PCR(port));
2369 +       val >>= GSW_REG_PCR_EG_TAG_S;
2370 +       val &= GSW_REG_PCR_EG_TAG_M;
2371 +
2372 +       return !!val;
2373 +}
2374 +
2375 +static void gsw_set_port_untag(struct mt7620_gsw *gsw, unsigned port, unsigned untag)
2376 +{
2377 +       unsigned val;
2378 +
2379 +       val = gsw_r32(gsw, GSW_REG_PCR(port));
2380 +       if (!untag)
2381 +               untag = 0x2;
2382 +       else
2383 +               untag = 0;
2384 +       val &= ~(GSW_REG_PCR_EG_TAG_M << GSW_REG_PCR_EG_TAG_S);
2385 +       val |= (untag & GSW_REG_PCR_EG_TAG_M) << GSW_REG_PCR_EG_TAG_S;
2386 +       gsw_w32(gsw, val, GSW_REG_PCR(port));
2387 +}
2388 +
2389 +static int gsw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2390 +{
2391 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2392 +       int vlan_idx = -1;
2393 +       u32 member;
2394 +       int i;
2395 +
2396 +       val->len = 0;
2397 +
2398 +       if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS)
2399 +               return -EINVAL;
2400 +
2401 +       /* valid vlan? */
2402 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2403 +               if (gsw_get_vlan_id(gsw, i) != val->port_vlan)
2404 +                       continue;
2405 +               member = gsw_get_port_member(gsw, i);
2406 +               vlan_idx = i;
2407 +               break;
2408 +       }
2409 +
2410 +       if (vlan_idx == -1)
2411 +               return -EINVAL;
2412 +
2413 +       for (i = 0; i < GSW_NUM_PORTS; i++) {
2414 +               struct switch_port *p;
2415 +               int port_mask = 1 << i;
2416 +
2417 +               if (!(member & port_mask))
2418 +                       continue;
2419 +
2420 +               p = &val->value.ports[val->len++];
2421 +               p->id = i;
2422 +               if (gsw_get_port_tag(gsw, i))
2423 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
2424 +               else
2425 +                       p->flags = 0;
2426 +       }
2427 +
2428 +       return 0;
2429 +}
2430 +
2431 +static int gsw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2432 +{
2433 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2434 +       int ports;
2435 +       int vlan_idx = -1;
2436 +       int i;
2437 +
2438 +       if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS ||
2439 +                       val->len > GSW_NUM_PORTS)
2440 +               return -EINVAL;
2441 +
2442 +       /* one of the already defined vlans? */
2443 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2444 +               if (gsw->vlans[i].vid == val->port_vlan &&
2445 +                   gsw->vlans[i].ports) {
2446 +                       vlan_idx = i;
2447 +                       break;
2448 +               }
2449 +       }
2450 +
2451 +       /* select a free slot */
2452 +       for (i = 0; vlan_idx == -1 && i < GSW_NUM_VLANS; i++) {
2453 +               if (!gsw->vlans[i].ports)
2454 +                       vlan_idx = i;
2455 +       }
2456 +
2457 +       /* bail if all slots are in use */
2458 +       if (vlan_idx == -1)
2459 +               return -EINVAL;
2460 +
2461 +       ports = 0;
2462 +       for (i = 0; i < val->len; i++) {
2463 +               struct switch_port *p = &val->value.ports[i];
2464 +               int port_mask = 1 << p->id;
2465 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
2466 +
2467 +               if (p->id >= GSW_NUM_PORTS)
2468 +                       return -EINVAL;
2469 +
2470 +               ports |= port_mask;
2471 +               gsw->ports[p->id].untag = untagged;
2472 +       }
2473 +       gsw->vlans[vlan_idx].ports = ports;
2474 +       if (!ports)
2475 +               gsw->vlans[vlan_idx].vid = 0xfff;
2476 +       else
2477 +               gsw->vlans[vlan_idx].vid = val->port_vlan;
2478 +
2479 +       return 0;
2480 +}
2481 +
2482 +static int gsw_apply_config(struct switch_dev *dev)
2483 +{
2484 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2485 +       int i;
2486 +
2487 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2488 +               gsw_set_vtcr(&gsw->swdev, i);
2489 +               if (gsw->global_vlan_enable) {
2490 +                       gsw_set_vlan_id(gsw, i, gsw->vlans[i].vid);
2491 +                       gsw_set_port_member(gsw, i, gsw->vlans[i].ports);
2492 +                       gsw_vlan_tagging_enable(gsw, i, 1);
2493 +               } else {
2494 +                       gsw_set_vlan_id(gsw, i, 0xfff);
2495 +                       gsw_set_port_member(gsw, i, 0);
2496 +                       gsw_vlan_tagging_enable(gsw, i, 0);
2497 +               }
2498 +               gsw_apply_vtcr(&gsw->swdev, i);
2499 +       }
2500 +
2501 +       for (i = 0; i < GSW_NUM_PORTS; i++) {
2502 +               if (gsw->global_vlan_enable) {
2503 +                       gsw_set_port_untag(gsw, i, !gsw->ports[i].untag);
2504 +                       gsw_set_pvid(gsw, i, gsw->ports[i].pvid);
2505 +               } else {
2506 +                       gsw_set_port_untag(gsw, i, 0);
2507 +                       gsw_set_pvid(gsw, i, 0);
2508 +               }
2509 +       }
2510 +
2511 +       if (!gsw->global_vlan_enable)
2512 +               gsw_set_vlan_id(gsw, 0, 0);
2513 +
2514 +       return 0;
2515 +}
2516 +
2517 +static int gsw_get_port_link(struct switch_dev *dev,
2518 +                        int port,
2519 +                        struct switch_port_link *link)
2520 +{
2521 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2522 +       u32 status;
2523 +
2524 +       if (port < 0 || port >= GSW_NUM_PORTS)
2525 +               return -EINVAL;
2526 +
2527 +       status = gsw_r32(gsw, GSW_REG_PORT_STATUS(port));
2528 +       link->link = status & 0x1;
2529 +       link->duplex = (status >> 1) & 1;
2530 +
2531 +       switch ((status >> 2) & 0x3) {
2532 +       case 0:
2533 +               link->speed = SWITCH_PORT_SPEED_10;
2534 +               break;
2535 +       case 1:
2536 +               link->speed = SWITCH_PORT_SPEED_100;
2537 +               break;
2538 +       case 2:
2539 +       case 3: // forced gige speed can be 2 or 3
2540 +               link->speed = SWITCH_PORT_SPEED_1000;
2541 +               break;
2542 +       }
2543 +
2544 +       return 0;
2545 +}
2546 +
2547 +static int gsw_set_port_bool(struct switch_dev *dev,
2548 +                        const struct switch_attr *attr,
2549 +                        struct switch_val *val)
2550 +{
2551 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2552 +       int idx = val->port_vlan;
2553 +
2554 +       if (idx < 0 || idx >= GSW_NUM_PORTS ||
2555 +           val->value.i < 0 || val->value.i > 1)
2556 +               return -EINVAL;
2557 +
2558 +       switch (attr->id) {
2559 +       case GSW_ATTR_PORT_UNTAG:
2560 +               gsw->ports[idx].untag = val->value.i;
2561 +               break;
2562 +       default:
2563 +               return -EINVAL;
2564 +       }
2565 +
2566 +       return 0;
2567 +}
2568 +
2569 +static const struct switch_attr gsw_global[] = {
2570 +       {
2571 +               .type = SWITCH_TYPE_INT,
2572 +               .name = "enable_vlan",
2573 +               .description = "VLAN mode (1:enabled)",
2574 +               .max = 1,
2575 +               .id = GSW_ATTR_ENABLE_VLAN,
2576 +               .get = gsw_get_vlan_enable,
2577 +               .set = gsw_set_vlan_enable,
2578 +       },
2579 +};
2580 +
2581 +static const struct switch_attr gsw_port[] = {
2582 +       {
2583 +               .type = SWITCH_TYPE_INT,
2584 +               .name = "untag",
2585 +               .description = "Untag (1:strip outgoing vlan tag)",
2586 +               .max = 1,
2587 +               .id = GSW_ATTR_PORT_UNTAG,
2588 +               .get = gsw_get_port_bool,
2589 +               .set = gsw_set_port_bool,
2590 +       },
2591 +};
2592 +
2593 +static const struct switch_attr gsw_vlan[] = {
2594 +};
2595 +
2596 +static const struct switch_dev_ops gsw_ops = {
2597 +       .attr_global = {
2598 +               .attr = gsw_global,
2599 +               .n_attr = ARRAY_SIZE(gsw_global),
2600 +       },
2601 +       .attr_port = {
2602 +               .attr = gsw_port,
2603 +               .n_attr = ARRAY_SIZE(gsw_port),
2604 +       },
2605 +       .attr_vlan = {
2606 +               .attr = gsw_vlan,
2607 +               .n_attr = ARRAY_SIZE(gsw_vlan),
2608 +       },
2609 +       .get_vlan_ports = gsw_get_vlan_ports,
2610 +       .set_vlan_ports = gsw_set_vlan_ports,
2611 +       .get_port_pvid = gsw_get_port_pvid,
2612 +       .set_port_pvid = gsw_set_port_pvid,
2613 +       .get_port_link = gsw_get_port_link,
2614 +       .apply_config = gsw_apply_config,
2615 +       .reset_switch = gsw_reset_switch,
2616 +};
2617 +
2618 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2619 +{
2620 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2621 +       unsigned long flags;
2622 +
2623 +       spin_lock_irqsave(&priv->page_lock, flags);
2624 +       gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2625 +       gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2626 +               GSW_REG_SMACCR0);
2627 +       spin_unlock_irqrestore(&priv->page_lock, flags);
2628 +}
2629 +
2630 +static struct of_device_id gsw_match[] = {
2631 +       { .compatible = "ralink,mt7620a-gsw" },
2632 +       {}
2633 +};
2634 +
2635 +int mt7620_gsw_probe(struct fe_priv *priv)
2636 +{
2637 +       struct mt7620_gsw *gsw;
2638 +       struct device_node *np;
2639 +       struct switch_dev *swdev;
2640 +       const char *port4 = NULL;
2641 +
2642 +       np = of_find_matching_node(NULL, gsw_match);
2643 +       if (!np) {
2644 +               dev_err(priv->device, "no gsw node found\n");
2645 +               return -EINVAL;
2646 +       }
2647 +       np = of_node_get(np);
2648 +
2649 +       gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2650 +       if (!gsw) {
2651 +               dev_err(priv->device, "no gsw memory for private data\n");
2652 +               return -ENOMEM;
2653 +       }
2654 +
2655 +       gsw->irq = irq_of_parse_and_map(np, 0);
2656 +       if (!gsw->irq) {
2657 +               dev_err(priv->device, "no gsw irq resource found\n");
2658 +               return -ENOMEM;
2659 +       }
2660 +
2661 +       gsw->base = of_iomap(np, 0);
2662 +       if (!gsw->base) {
2663 +               dev_err(priv->device, "gsw ioremap failed\n");
2664 +       }
2665 +
2666 +       gsw->dev = priv->device;
2667 +       priv->soc->swpriv = gsw;
2668 +
2669 +       swdev = &gsw->swdev;
2670 +       swdev->of_node = np;
2671 +       swdev->name = "mt7620a-gsw";
2672 +       swdev->alias = "mt7620x";
2673 +       swdev->cpu_port = GSW_PORT6;
2674 +       swdev->ports = GSW_NUM_PORTS;
2675 +       swdev->vlans = GSW_NUM_VLANS;
2676 +       swdev->ops = &gsw_ops;
2677 +
2678 +       if (register_switch(swdev, NULL))
2679 +               dev_err(priv->device, "register_switch failed\n");
2680 +
2681 +       of_property_read_string(np, "ralink,port4", &port4);
2682 +       if (port4 && !strcmp(port4, "ephy"))
2683 +               gsw->port4 = PORT4_EPHY;
2684 +       else if (port4 && !strcmp(port4, "gmac"))
2685 +               gsw->port4 = PORT4_EXT;
2686 +       else
2687 +               WARN_ON(port4);
2688 +
2689 +       gsw_hw_init(gsw);
2690 +
2691 +       gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2692 +       request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2693 +
2694 +       return 0;
2695 +}
2696 --- /dev/null
2697 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2698 @@ -0,0 +1,29 @@
2699 +/*
2700 + *   This program is free software; you can redistribute it and/or modify
2701 + *   it under the terms of the GNU General Public License as published by
2702 + *   the Free Software Foundation; version 2 of the License
2703 + *
2704 + *   This program is distributed in the hope that it will be useful,
2705 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2706 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2707 + *   GNU General Public License for more details.
2708 + *
2709 + *   You should have received a copy of the GNU General Public License
2710 + *   along with this program; if not, write to the Free Software
2711 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2712 + *
2713 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2714 + */
2715 +
2716 +#ifndef _RALINK_GSW_MT7620_H__
2717 +#define _RALINK_GSW_MT7620_H__
2718 +
2719 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2720 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2721 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2722 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2723 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2724 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2725 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2726 +
2727 +#endif
2728 --- /dev/null
2729 +++ b/drivers/net/ethernet/ralink/mdio.c
2730 @@ -0,0 +1,245 @@
2731 +/*
2732 + *   This program is free software; you can redistribute it and/or modify
2733 + *   it under the terms of the GNU General Public License as published by
2734 + *   the Free Software Foundation; version 2 of the License
2735 + *
2736 + *   This program is distributed in the hope that it will be useful,
2737 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2738 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2739 + *   GNU General Public License for more details.
2740 + *
2741 + *   You should have received a copy of the GNU General Public License
2742 + *   along with this program; if not, write to the Free Software
2743 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2744 + *
2745 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2746 + */
2747 +
2748 +#include <linux/module.h>
2749 +#include <linux/kernel.h>
2750 +#include <linux/types.h>
2751 +#include <linux/dma-mapping.h>
2752 +#include <linux/init.h>
2753 +#include <linux/skbuff.h>
2754 +#include <linux/etherdevice.h>
2755 +#include <linux/ethtool.h>
2756 +#include <linux/platform_device.h>
2757 +#include <linux/phy.h>
2758 +#include <linux/of_device.h>
2759 +#include <linux/clk.h>
2760 +#include <linux/of_net.h>
2761 +#include <linux/of_mdio.h>
2762 +
2763 +#include "ralink_soc_eth.h"
2764 +#include "mdio.h"
2765 +
2766 +static int fe_mdio_reset(struct mii_bus *bus)
2767 +{
2768 +       /* TODO */
2769 +       return 0;
2770 +}
2771 +
2772 +static void fe_phy_link_adjust(struct net_device *dev)
2773 +{
2774 +       struct fe_priv *priv = netdev_priv(dev);
2775 +       unsigned long flags;
2776 +       int i;
2777 +
2778 +       spin_lock_irqsave(&priv->phy->lock, flags);
2779 +       for (i = 0; i < 8; i++) {
2780 +               if (priv->phy->phy_node[i]) {
2781 +                       struct phy_device *phydev = priv->phy->phy[i];
2782 +                       int status_change = 0;
2783 +
2784 +                       if (phydev->link)
2785 +                               if (priv->phy->duplex[i] != phydev->duplex ||
2786 +                                               priv->phy->speed[i] != phydev->speed)
2787 +                                       status_change = 1;
2788 +
2789 +                       if (phydev->link != priv->link[i])
2790 +                               status_change = 1;
2791 +
2792 +                       switch (phydev->speed) {
2793 +                       case SPEED_1000:
2794 +                       case SPEED_100:
2795 +                       case SPEED_10:
2796 +                               priv->link[i] = phydev->link;
2797 +                               priv->phy->duplex[i] = phydev->duplex;
2798 +                               priv->phy->speed[i] = phydev->speed;
2799 +
2800 +                               if (status_change && priv->soc->mdio_adjust_link)
2801 +                                       priv->soc->mdio_adjust_link(priv, i);
2802 +                               break;
2803 +                       }
2804 +               }
2805 +       }
2806 +       spin_unlock_irqrestore(&priv->phy->lock, flags);
2807 +}
2808 +
2809 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2810 +{
2811 +       const __be32 *_port = NULL;
2812 +       struct phy_device *phydev;
2813 +       int phy_mode, port;
2814 +
2815 +       _port = of_get_property(phy_node, "reg", NULL);
2816 +
2817 +       if (!_port || (be32_to_cpu(*_port) >= 8)) {
2818 +               pr_err("%s: invalid port id\n", phy_node->name);
2819 +               return -EINVAL;
2820 +       }
2821 +       port = be32_to_cpu(*_port);
2822 +       phy_mode = of_get_phy_mode(phy_node);
2823 +       if (phy_mode < 0) {
2824 +               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2825 +               priv->phy->phy_node[port] = NULL;
2826 +               return -EINVAL;
2827 +       }
2828 +
2829 +       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2830 +                               0, phy_mode);
2831 +       if (IS_ERR(phydev)) {
2832 +               dev_err(priv->device, "could not connect to PHY\n");
2833 +               priv->phy->phy_node[port] = NULL;
2834 +               return PTR_ERR(phydev);
2835 +       }
2836 +
2837 +       phydev->supported &= PHY_GBIT_FEATURES;
2838 +       phydev->advertising = phydev->supported;
2839 +       phydev->no_auto_carrier_off = 1;
2840 +
2841 +       dev_info(priv->device,
2842 +                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2843 +                port, dev_name(&phydev->dev), phydev->phy_id,
2844 +                phydev->drv->name);
2845 +
2846 +       priv->phy->phy[port] = phydev;
2847 +       priv->link[port] = 0;
2848 +
2849 +       return 0;
2850 +}
2851 +
2852 +static int fe_phy_connect(struct fe_priv *priv)
2853 +{
2854 +       return 0;
2855 +}
2856 +
2857 +static void fe_phy_disconnect(struct fe_priv *priv)
2858 +{
2859 +       unsigned long flags;
2860 +       int i;
2861 +
2862 +       for (i = 0; i < 8; i++)
2863 +               if (priv->phy->phy_fixed[i]) {
2864 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2865 +                       priv->link[i] = 0;
2866 +                       if (priv->soc->mdio_adjust_link)
2867 +                               priv->soc->mdio_adjust_link(priv, i);
2868 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2869 +               } else if (priv->phy->phy[i]) {
2870 +                       phy_disconnect(priv->phy->phy[i]);
2871 +               }
2872 +}
2873 +
2874 +static void fe_phy_start(struct fe_priv *priv)
2875 +{
2876 +       unsigned long flags;
2877 +       int i;
2878 +
2879 +       for (i = 0; i < 8; i++) {
2880 +               if (priv->phy->phy_fixed[i]) {
2881 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2882 +                       priv->link[i] = 1;
2883 +                       if (priv->soc->mdio_adjust_link)
2884 +                               priv->soc->mdio_adjust_link(priv, i);
2885 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2886 +               } else if (priv->phy->phy[i]) {
2887 +                       phy_start(priv->phy->phy[i]);
2888 +               }
2889 +       }
2890 +}
2891 +
2892 +static void fe_phy_stop(struct fe_priv *priv)
2893 +{
2894 +       unsigned long flags;
2895 +       int i;
2896 +
2897 +       for (i = 0; i < 8; i++)
2898 +               if (priv->phy->phy_fixed[i]) {
2899 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2900 +                       priv->link[i] = 0;
2901 +                       if (priv->soc->mdio_adjust_link)
2902 +                               priv->soc->mdio_adjust_link(priv, i);
2903 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2904 +               } else if (priv->phy->phy[i]) {
2905 +                       phy_stop(priv->phy->phy[i]);
2906 +               }
2907 +}
2908 +
2909 +static struct fe_phy phy_ralink = {
2910 +       .connect = fe_phy_connect,
2911 +       .disconnect = fe_phy_disconnect,
2912 +       .start = fe_phy_start,
2913 +       .stop = fe_phy_stop,
2914 +};
2915 +
2916 +int fe_mdio_init(struct fe_priv *priv)
2917 +{
2918 +       struct device_node *mii_np;
2919 +       int err;
2920 +
2921 +       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2922 +               return 0;
2923 +
2924 +       spin_lock_init(&phy_ralink.lock);
2925 +       priv->phy = &phy_ralink;
2926 +
2927 +       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2928 +       if (!mii_np) {
2929 +               dev_err(priv->device, "no %s child node found", "mdio-bus");
2930 +               return -ENODEV;
2931 +       }
2932 +
2933 +       if (!of_device_is_available(mii_np)) {
2934 +               err = 0;
2935 +               goto err_put_node;
2936 +       }
2937 +
2938 +       priv->mii_bus = mdiobus_alloc();
2939 +       if (priv->mii_bus == NULL) {
2940 +               err = -ENOMEM;
2941 +               goto err_put_node;
2942 +       }
2943 +
2944 +       priv->mii_bus->name = "mdio";
2945 +       priv->mii_bus->read = priv->soc->mdio_read;
2946 +       priv->mii_bus->write = priv->soc->mdio_write;
2947 +       priv->mii_bus->reset = fe_mdio_reset;
2948 +       priv->mii_bus->irq = priv->mii_irq;
2949 +       priv->mii_bus->priv = priv;
2950 +       priv->mii_bus->parent = priv->device;
2951 +
2952 +       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2953 +       err = of_mdiobus_register(priv->mii_bus, mii_np);
2954 +       if (err)
2955 +               goto err_free_bus;
2956 +
2957 +       return 0;
2958 +
2959 +err_free_bus:
2960 +       kfree(priv->mii_bus);
2961 +err_put_node:
2962 +       of_node_put(mii_np);
2963 +       priv->mii_bus = NULL;
2964 +       return err;
2965 +}
2966 +
2967 +void fe_mdio_cleanup(struct fe_priv *priv)
2968 +{
2969 +       if (!priv->mii_bus)
2970 +               return;
2971 +
2972 +       mdiobus_unregister(priv->mii_bus);
2973 +       of_node_put(priv->mii_bus->dev.of_node);
2974 +       kfree(priv->mii_bus);
2975 +}
2976 --- /dev/null
2977 +++ b/drivers/net/ethernet/ralink/mdio.h
2978 @@ -0,0 +1,29 @@
2979 +/*
2980 + *   This program is free software; you can redistribute it and/or modify
2981 + *   it under the terms of the GNU General Public License as published by
2982 + *   the Free Software Foundation; version 2 of the License
2983 + *
2984 + *   This program is distributed in the hope that it will be useful,
2985 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2986 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2987 + *   GNU General Public License for more details.
2988 + *
2989 + *   You should have received a copy of the GNU General Public License
2990 + *   along with this program; if not, write to the Free Software
2991 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2992 + *
2993 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2994 + */
2995 +
2996 +#ifndef _RALINK_MDIO_H__
2997 +#define _RALINK_MDIO_H__
2998 +
2999 +#ifdef CONFIG_NET_RALINK_MDIO
3000 +extern int fe_mdio_init(struct fe_priv *priv);
3001 +extern void fe_mdio_cleanup(struct fe_priv *priv);
3002 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
3003 +#else
3004 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
3005 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
3006 +#endif
3007 +#endif
3008 --- /dev/null
3009 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
3010 @@ -0,0 +1,232 @@
3011 +/*
3012 + *   This program is free software; you can redistribute it and/or modify
3013 + *   it under the terms of the GNU General Public License as published by
3014 + *   the Free Software Foundation; version 2 of the License
3015 + *
3016 + *   This program is distributed in the hope that it will be useful,
3017 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3018 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3019 + *   GNU General Public License for more details.
3020 + *
3021 + *   You should have received a copy of the GNU General Public License
3022 + *   along with this program; if not, write to the Free Software
3023 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3024 + *
3025 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3026 + */
3027 +
3028 +#include <linux/module.h>
3029 +#include <linux/kernel.h>
3030 +#include <linux/types.h>
3031 +#include <linux/dma-mapping.h>
3032 +#include <linux/init.h>
3033 +#include <linux/skbuff.h>
3034 +#include <linux/etherdevice.h>
3035 +#include <linux/ethtool.h>
3036 +#include <linux/platform_device.h>
3037 +#include <linux/phy.h>
3038 +#include <linux/of_device.h>
3039 +#include <linux/clk.h>
3040 +#include <linux/of_net.h>
3041 +#include <linux/of_mdio.h>
3042 +
3043 +#include "ralink_soc_eth.h"
3044 +#include "mdio_rt2880.h"
3045 +#include "mdio.h"
3046 +
3047 +#define FE_MDIO_RETRY  1000
3048 +
3049 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
3050 +{
3051 +       switch (priv->phy->speed[0]) {
3052 +       case SPEED_1000:
3053 +               return "1000";
3054 +       case SPEED_100:
3055 +               return "100";
3056 +       case SPEED_10:
3057 +               return "10";
3058 +       }
3059 +
3060 +       return "?";
3061 +}
3062 +
3063 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
3064 +{
3065 +       u32 mdio_cfg;
3066 +
3067 +       if (!priv->link[0]) {
3068 +               netif_carrier_off(priv->netdev);
3069 +               netdev_info(priv->netdev, "link down\n");
3070 +               return;
3071 +       }
3072 +
3073 +       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
3074 +                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
3075 +                  FE_MDIO_CFG_GP1_FRC_EN;
3076 +
3077 +       if (priv->phy->duplex[0] == DUPLEX_FULL)
3078 +               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
3079 +
3080 +       if (priv->phy->tx_fc[0])
3081 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
3082 +
3083 +       if (priv->phy->rx_fc[0])
3084 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
3085 +
3086 +       switch (priv->phy->speed[0]) {
3087 +       case SPEED_10:
3088 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
3089 +               break;
3090 +       case SPEED_100:
3091 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
3092 +               break;
3093 +       case SPEED_1000:
3094 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
3095 +               break;
3096 +       default:
3097 +               BUG();
3098 +       }
3099 +
3100 +       fe_w32(mdio_cfg, FE_MDIO_CFG);
3101 +
3102 +       netif_carrier_on(priv->netdev);
3103 +       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
3104 +                   rt2880_speed_str(priv),
3105 +                   (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
3106 +}
3107 +
3108 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
3109 +{
3110 +       int retries;
3111 +
3112 +       retries = FE_MDIO_RETRY;
3113 +       while (1) {
3114 +               u32 t;
3115 +
3116 +               t = fe_r32(FE_MDIO_ACCESS);
3117 +               if ((t & (0x1 << 31)) == 0)
3118 +                       return 0;
3119 +
3120 +               if (retries-- == 0)
3121 +                       break;
3122 +
3123 +               udelay(1);
3124 +       }
3125 +
3126 +       dev_err(priv->device, "MDIO operation timed out\n");
3127 +       return -ETIMEDOUT;
3128 +}
3129 +
3130 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
3131 +{
3132 +       struct fe_priv *priv = bus->priv;
3133 +       int err;
3134 +       u32 t;
3135 +
3136 +       err = rt2880_mdio_wait_ready(priv);
3137 +       if (err)
3138 +               return 0xffff;
3139 +
3140 +       t = (phy_addr << 24) | (phy_reg << 16);
3141 +       fe_w32(t, FE_MDIO_ACCESS);
3142 +       t |= (1 << 31);
3143 +       fe_w32(t, FE_MDIO_ACCESS);
3144 +
3145 +       err = rt2880_mdio_wait_ready(priv);
3146 +       if (err)
3147 +               return 0xffff;
3148 +
3149 +       pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3150 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3151 +
3152 +       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
3153 +}
3154 +
3155 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
3156 +{
3157 +       struct fe_priv *priv = bus->priv;
3158 +       int err;
3159 +       u32 t;
3160 +
3161 +       pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3162 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3163 +
3164 +       err = rt2880_mdio_wait_ready(priv);
3165 +       if (err)
3166 +               return err;
3167 +
3168 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
3169 +       fe_w32(t, FE_MDIO_ACCESS);
3170 +       t |= (1 << 31);
3171 +       fe_w32(t, FE_MDIO_ACCESS);
3172 +
3173 +       return rt2880_mdio_wait_ready(priv);
3174 +}
3175 +
3176 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
3177 +{
3178 +       const __be32 *id = of_get_property(np, "reg", NULL);
3179 +       const __be32 *link;
3180 +       int size;
3181 +       int phy_mode;
3182 +
3183 +       if (!id || (be32_to_cpu(*id) != 0)) {
3184 +               pr_err("%s: invalid port id\n", np->name);
3185 +               return;
3186 +       }
3187 +
3188 +       priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
3189 +       if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
3190 +               pr_err("%s: invalid fixed link property\n", np->name);
3191 +               priv->phy->phy_fixed[0] = NULL;
3192 +               return;
3193 +       }
3194 +
3195 +       phy_mode = of_get_phy_mode(np);
3196 +       switch (phy_mode) {
3197 +       case PHY_INTERFACE_MODE_RGMII:
3198 +               break;
3199 +       case PHY_INTERFACE_MODE_MII:
3200 +               break;
3201 +       case PHY_INTERFACE_MODE_RMII:
3202 +               break;
3203 +       default:
3204 +               if (!priv->phy->phy_fixed[0])
3205 +                       dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
3206 +               break;
3207 +       }
3208 +
3209 +       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
3210 +       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
3211 +               return;
3212 +
3213 +       if (priv->phy->phy_fixed[0]) {
3214 +               link = priv->phy->phy_fixed[0];
3215 +               priv->phy->speed[0] = be32_to_cpup(link++);
3216 +               priv->phy->duplex[0] = be32_to_cpup(link++);
3217 +               priv->phy->tx_fc[0] = be32_to_cpup(link++);
3218 +               priv->phy->rx_fc[0] = be32_to_cpup(link++);
3219 +
3220 +               priv->link[0] = 1;
3221 +               switch (priv->phy->speed[0]) {
3222 +               case SPEED_10:
3223 +                       break;
3224 +               case SPEED_100:
3225 +                       break;
3226 +               case SPEED_1000:
3227 +                       break;
3228 +               default:
3229 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
3230 +                       priv->phy->phy_fixed[0] = 0;
3231 +                       return;
3232 +               }
3233 +               dev_info(priv->device, "using fixed link parameters\n");
3234 +               rt2880_mdio_link_adjust(priv, 0);
3235 +               return;
3236 +       }
3237 +       if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
3238 +               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
3239 +       }
3240 +
3241 +       return;
3242 +}
3243 --- /dev/null
3244 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
3245 @@ -0,0 +1,26 @@
3246 +/*
3247 + *   This program is free software; you can redistribute it and/or modify
3248 + *   it under the terms of the GNU General Public License as published by
3249 + *   the Free Software Foundation; version 2 of the License
3250 + *
3251 + *   This program is distributed in the hope that it will be useful,
3252 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3253 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3254 + *   GNU General Public License for more details.
3255 + *
3256 + *   You should have received a copy of the GNU General Public License
3257 + *   along with this program; if not, write to the Free Software
3258 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3259 + *
3260 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3261 + */
3262 +
3263 +#ifndef _RALINK_MDIO_RT2880_H__
3264 +#define _RALINK_MDIO_RT2880_H__
3265 +
3266 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
3267 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
3268 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
3269 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
3270 +
3271 +#endif
3272 --- /dev/null
3273 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3274 @@ -0,0 +1,746 @@
3275 +/*
3276 + *   This program is free software; you can redistribute it and/or modify
3277 + *   it under the terms of the GNU General Public License as published by
3278 + *   the Free Software Foundation; version 2 of the License
3279 + *
3280 + *   This program is distributed in the hope that it will be useful,
3281 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3282 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3283 + *   GNU General Public License for more details.
3284 + *
3285 + *   You should have received a copy of the GNU General Public License
3286 + *   along with this program; if not, write to the Free Software
3287 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3288 + *
3289 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3290 + */
3291 +
3292 +#include <linux/module.h>
3293 +#include <linux/kernel.h>
3294 +#include <linux/types.h>
3295 +#include <linux/dma-mapping.h>
3296 +#include <linux/init.h>
3297 +#include <linux/skbuff.h>
3298 +#include <linux/etherdevice.h>
3299 +#include <linux/ethtool.h>
3300 +#include <linux/platform_device.h>
3301 +#include <linux/of_device.h>
3302 +#include <linux/clk.h>
3303 +#include <linux/of_net.h>
3304 +#include <linux/of_mdio.h>
3305 +#include <linux/if_vlan.h>
3306 +
3307 +#include <asm/mach-ralink/ralink_regs.h>
3308 +
3309 +#include "ralink_soc_eth.h"
3310 +#include "esw_rt3052.h"
3311 +#include "mdio.h"
3312 +
3313 +#define TX_TIMEOUT             (20 * HZ / 100)
3314 +#define        MAX_RX_LENGTH           1536
3315 +
3316 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3317 +       [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3318 +       [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3319 +       [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3320 +       [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3321 +       [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3322 +       [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3323 +       [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3324 +       [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3325 +       [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3326 +       [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3327 +       [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3328 +       [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
3329 +};
3330 +
3331 +static const u32 *fe_reg_table = fe_reg_table_default;
3332 +
3333 +static void __iomem *fe_base = 0;
3334 +
3335 +void fe_w32(u32 val, unsigned reg)
3336 +{
3337 +       __raw_writel(val, fe_base + reg);
3338 +}
3339 +
3340 +u32 fe_r32(unsigned reg)
3341 +{
3342 +       return __raw_readl(fe_base + reg);
3343 +}
3344 +
3345 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3346 +{
3347 +       fe_w32(val, fe_reg_table[reg]);
3348 +}
3349 +
3350 +static inline u32 fe_reg_r32(enum fe_reg reg)
3351 +{
3352 +       return fe_r32(fe_reg_table[reg]);
3353 +}
3354 +
3355 +static inline void fe_int_disable(u32 mask)
3356 +{
3357 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3358 +                    FE_REG_FE_INT_ENABLE);
3359 +       /* flush write */
3360 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3361 +}
3362 +
3363 +static inline void fe_int_enable(u32 mask)
3364 +{
3365 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3366 +                    FE_REG_FE_INT_ENABLE);
3367 +       /* flush write */
3368 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3369 +}
3370 +
3371 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3372 +{
3373 +       unsigned long flags;
3374 +
3375 +       spin_lock_irqsave(&priv->page_lock, flags);
3376 +       fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3377 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3378 +                    FE_GDMA1_MAC_ADRL);
3379 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3380 +}
3381 +
3382 +static int fe_set_mac_address(struct net_device *dev, void *p)
3383 +{
3384 +       int ret = eth_mac_addr(dev, p);
3385 +
3386 +       if (!ret) {
3387 +               struct fe_priv *priv = netdev_priv(dev);
3388 +
3389 +               if (priv->soc->set_mac)
3390 +                       priv->soc->set_mac(priv, dev->dev_addr);
3391 +               else
3392 +                       fe_hw_set_macaddr(priv, p);
3393 +       }
3394 +
3395 +       return ret;
3396 +}
3397 +
3398 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3399 +{
3400 +       struct sk_buff *skb;
3401 +
3402 +       skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3403 +       if (!skb)
3404 +               return NULL;
3405 +
3406 +       skb_reserve(skb, NET_IP_ALIGN);
3407 +
3408 +       return skb;
3409 +}
3410 +
3411 +static int fe_alloc_rx(struct fe_priv *priv)
3412 +{
3413 +       int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3414 +       int i;
3415 +
3416 +       priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3417 +                                       &priv->rx_phys, GFP_ATOMIC);
3418 +       if (!priv->rx_dma)
3419 +               return -ENOMEM;
3420 +
3421 +       memset(priv->rx_dma, 0, size);
3422 +
3423 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3424 +               priv->rx_skb[i] = fe_alloc_skb(priv);
3425 +               if (!priv->rx_skb[i])
3426 +                       return -ENOMEM;
3427 +       }
3428 +
3429 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3430 +               dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3431 +                                               priv->rx_skb[i]->data,
3432 +                                               MAX_RX_LENGTH,
3433 +                                               DMA_FROM_DEVICE);
3434 +               priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3435 +
3436 +               if (priv->soc->rx_dma)
3437 +                       priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3438 +               else
3439 +                       priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3440 +       }
3441 +       wmb();
3442 +
3443 +       fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3444 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3445 +       fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3446 +       fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3447 +
3448 +       return 0;
3449 +}
3450 +
3451 +static int fe_alloc_tx(struct fe_priv *priv)
3452 +{
3453 +       int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3454 +       int i;
3455 +
3456 +       priv->tx_free_idx = 0;
3457 +
3458 +       priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3459 +                                       &priv->tx_phys, GFP_ATOMIC);
3460 +       if (!priv->tx_dma)
3461 +               return -ENOMEM;
3462 +
3463 +       memset(priv->tx_dma, 0, size);
3464 +
3465 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3466 +               if (priv->soc->tx_dma) {
3467 +                       priv->soc->tx_dma(priv, i, 0);
3468 +                       continue;
3469 +               }
3470 +
3471 +               priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3472 +               priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3473 +       }
3474 +
3475 +       fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3476 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3477 +       fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3478 +       fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3479 +
3480 +       return 0;
3481 +}
3482 +
3483 +static void fe_free_dma(struct fe_priv *priv)
3484 +{
3485 +       int i;
3486 +
3487 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3488 +               if (priv->rx_skb[i]) {
3489 +                       dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3490 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3491 +                       dev_kfree_skb_any(priv->rx_skb[i]);
3492 +                       priv->rx_skb[i] = NULL;
3493 +               }
3494 +
3495 +               if (priv->tx_skb[i]) {
3496 +                       dev_kfree_skb_any(priv->tx_skb[i]);
3497 +                       priv->tx_skb[i] = NULL;
3498 +               }
3499 +       }
3500 +
3501 +       if (priv->rx_dma) {
3502 +               int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3503 +               dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3504 +                                       priv->rx_phys);
3505 +       }
3506 +
3507 +       if (priv->tx_dma) {
3508 +               int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3509 +               dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3510 +                                       priv->tx_phys);
3511 +       }
3512 +
3513 +       netdev_reset_queue(priv->netdev);
3514 +}
3515 +
3516 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3517 +{
3518 +       struct fe_priv *priv = netdev_priv(dev);
3519 +       dma_addr_t mapped_addr;
3520 +       u32 tx_next;
3521 +       u32 tx;
3522 +
3523 +       if (priv->soc->min_pkt_len) {
3524 +               if (skb->len < priv->soc->min_pkt_len) {
3525 +                       if (skb_padto(skb, priv->soc->min_pkt_len)) {
3526 +                               printk(KERN_ERR
3527 +                                      "fe_eth: skb_padto failed\n");
3528 +                               kfree_skb(skb);
3529 +                               return 0;
3530 +                       }
3531 +                       skb_put(skb, priv->soc->min_pkt_len - skb->len);
3532 +               }
3533 +       }
3534 +
3535 +       dev->trans_start = jiffies;
3536 +       mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3537 +                               skb->len, DMA_TO_DEVICE);
3538 +
3539 +       spin_lock(&priv->page_lock);
3540 +
3541 +       tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3542 +       tx_next = (tx + 1) % NUM_DMA_DESC;
3543 +
3544 +       if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3545 +                       !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3546 +                       !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3547 +       {
3548 +               spin_unlock(&priv->page_lock);
3549 +               dev->stats.tx_dropped++;
3550 +               kfree_skb(skb);
3551 +
3552 +               return NETDEV_TX_OK;
3553 +       }
3554 +
3555 +       priv->tx_skb[tx] = skb;
3556 +       priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3557 +       wmb();
3558 +       if (priv->soc->tx_dma)
3559 +               priv->soc->tx_dma(priv, tx, skb->len);
3560 +       else
3561 +               priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3562 +
3563 +       if (skb->ip_summed == CHECKSUM_PARTIAL)
3564 +               priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3565 +       else
3566 +               priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3567 +
3568 +        if (fe_reg_table[FE_REG_FE_DMA_VID_BASE] && vlan_tx_tag_present(skb))
3569 +               priv->tx_dma[tx].txd4 |= 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
3570 +       else
3571 +               priv->tx_dma[tx].txd4 &= ~0x80;
3572 +
3573 +       dev->stats.tx_packets++;
3574 +       dev->stats.tx_bytes += skb->len;
3575 +
3576 +       fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3577 +       netdev_sent_queue(dev, skb->len);
3578 +
3579 +       spin_unlock(&priv->page_lock);
3580 +
3581 +       return NETDEV_TX_OK;
3582 +}
3583 +
3584 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3585 +{
3586 +       struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3587 +       int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3588 +       int complete = 0;
3589 +       int rx = 0;
3590 +
3591 +       while ((rx < budget) && !complete) {
3592 +               idx = (idx + 1) % NUM_DMA_DESC;
3593 +
3594 +               if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3595 +                       struct sk_buff *new_skb = fe_alloc_skb(priv);
3596 +
3597 +                       if (new_skb) {
3598 +                               int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3599 +                               dma_addr_t dma_addr;
3600 +
3601 +                               dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3602 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3603 +
3604 +                               skb_put(priv->rx_skb[idx], pktlen);
3605 +                               priv->rx_skb[idx]->dev = priv->netdev;
3606 +                               priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3607 +                               if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3608 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3609 +                               else
3610 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3611 +                               priv->netdev->stats.rx_packets++;
3612 +                               priv->netdev->stats.rx_bytes += pktlen;
3613 +                               netif_receive_skb(priv->rx_skb[idx]);
3614 +
3615 +                               priv->rx_skb[idx] = new_skb;
3616 +
3617 +                               dma_addr = dma_map_single(&priv->netdev->dev,
3618 +                                                 new_skb->data,
3619 +                                                 MAX_RX_LENGTH,
3620 +                                                 DMA_FROM_DEVICE);
3621 +                               priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3622 +                               wmb();
3623 +                       } else {
3624 +                               priv->netdev->stats.rx_dropped++;
3625 +                       }
3626 +
3627 +                       if (priv->soc->rx_dma)
3628 +                               priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3629 +                       else
3630 +                               priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3631 +                       fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3632 +
3633 +                       rx++;
3634 +               } else {
3635 +                       complete = 1;
3636 +               }
3637 +       }
3638 +
3639 +       if (complete) {
3640 +               napi_complete(&priv->rx_napi);
3641 +               fe_int_enable(priv->soc->rx_dly_int);
3642 +       }
3643 +
3644 +       return rx;
3645 +}
3646 +
3647 +static void fe_tx_housekeeping(unsigned long ptr)
3648 +{
3649 +       struct net_device *dev = (struct net_device*)ptr;
3650 +       struct fe_priv *priv = netdev_priv(dev);
3651 +       unsigned int bytes_compl = 0;
3652 +       unsigned int pkts_compl = 0;
3653 +
3654 +       spin_lock(&priv->page_lock);
3655 +       while (1) {
3656 +               struct fe_tx_dma *txd;
3657 +
3658 +               txd = &priv->tx_dma[priv->tx_free_idx];
3659 +
3660 +               if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3661 +                       break;
3662 +
3663 +               bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3664 +               pkts_compl++;
3665 +
3666 +               dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3667 +               priv->tx_skb[priv->tx_free_idx] = NULL;
3668 +               priv->tx_free_idx++;
3669 +               if (priv->tx_free_idx >= NUM_DMA_DESC)
3670 +                       priv->tx_free_idx = 0;
3671 +       }
3672 +
3673 +       netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3674 +        spin_unlock(&priv->page_lock);
3675 +
3676 +       fe_int_enable(priv->soc->tx_dly_int);
3677 +}
3678 +
3679 +static void fe_tx_timeout(struct net_device *dev)
3680 +{
3681 +       struct fe_priv *priv = netdev_priv(dev);
3682 +
3683 +        tasklet_schedule(&priv->tx_tasklet);
3684 +       priv->netdev->stats.tx_errors++;
3685 +       netdev_err(dev, "transmit timed out, waking up the queue\n");
3686 +       netif_wake_queue(dev);
3687 +}
3688 +
3689 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3690 +{
3691 +       struct fe_priv *priv = netdev_priv(dev);
3692 +       unsigned int status;
3693 +       unsigned int mask;
3694 +
3695 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3696 +       mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3697 +
3698 +       if (!(status & mask))
3699 +               return IRQ_NONE;
3700 +
3701 +       if (status & priv->soc->rx_dly_int) {
3702 +               fe_int_disable(priv->soc->rx_dly_int);
3703 +               napi_schedule(&priv->rx_napi);
3704 +       }
3705 +
3706 +       if (status & priv->soc->tx_dly_int) {
3707 +               fe_int_disable(priv->soc->tx_dly_int);
3708 +               tasklet_schedule(&priv->tx_tasklet);
3709 +       }
3710 +
3711 +       fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3712 +
3713 +       return IRQ_HANDLED;
3714 +}
3715 +
3716 +static int fe_hw_init(struct net_device *dev)
3717 +{
3718 +       struct fe_priv *priv = netdev_priv(dev);
3719 +       int err, i;
3720 +
3721 +       err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3722 +                               dev_name(priv->device), dev);
3723 +       if (err)
3724 +               return err;
3725 +
3726 +       err = fe_alloc_rx(priv);
3727 +       if (!err)
3728 +               err = fe_alloc_tx(priv);
3729 +       if (err)
3730 +               return err;
3731 +
3732 +       if (priv->soc->set_mac)
3733 +               priv->soc->set_mac(priv, dev->dev_addr);
3734 +       else
3735 +               fe_hw_set_macaddr(priv, dev->dev_addr);
3736 +
3737 +       fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3738 +
3739 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3740 +
3741 +
3742 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3743 +               for (i = 0; i < 16; i += 2)
3744 +                       fe_w32((i + 1) << 16 | i, fe_reg_table[FE_REG_FE_DMA_VID_BASE] + (i * 4));
3745 +
3746 +       tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3747 +
3748 +       if (priv->soc->fwd_config) {
3749 +               priv->soc->fwd_config(priv);
3750 +       } else {
3751 +               unsigned long sysclk = priv->sysclk;
3752 +
3753 +               if (!sysclk) {
3754 +                       netdev_err(dev, "unable to get clock\n");
3755 +                       return -EINVAL;
3756 +               }
3757 +
3758 +               sysclk /= FE_US_CYC_CNT_DIVISOR;
3759 +               sysclk <<= FE_US_CYC_CNT_SHIFT;
3760 +
3761 +               fe_w32((fe_r32(FE_FE_GLO_CFG) &
3762 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3763 +                       FE_FE_GLO_CFG);
3764 +
3765 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3766 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3767 +                       FE_GDMA1_FWD_CFG);
3768 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3769 +                       FE_CDMA_CSG_CFG);
3770 +               fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3771 +       }
3772 +
3773 +       fe_w32(1, FE_FE_RST_GL);
3774 +       fe_w32(0, FE_FE_RST_GL);
3775 +
3776 +       return 0;
3777 +}
3778 +
3779 +static int fe_open(struct net_device *dev)
3780 +{
3781 +       struct fe_priv *priv = netdev_priv(dev);
3782 +       unsigned long flags;
3783 +       u32 val;
3784 +
3785 +       spin_lock_irqsave(&priv->page_lock, flags);
3786 +       napi_enable(&priv->rx_napi);
3787 +
3788 +       val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3789 +       val |= priv->soc->pdma_glo_cfg;
3790 +       fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3791 +
3792 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3793 +
3794 +       if (priv->phy)
3795 +               priv->phy->start(priv);
3796 +
3797 +       if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3798 +               netif_carrier_on(dev);
3799 +
3800 +       netif_start_queue(dev);
3801 +       fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3802 +
3803 +       return 0;
3804 +}
3805 +
3806 +static int fe_stop(struct net_device *dev)
3807 +{
3808 +       struct fe_priv *priv = netdev_priv(dev);
3809 +       unsigned long flags;
3810 +
3811 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3812 +
3813 +       netif_stop_queue(dev);
3814 +
3815 +       if (priv->phy)
3816 +               priv->phy->stop(priv);
3817 +
3818 +       spin_lock_irqsave(&priv->page_lock, flags);
3819 +       napi_disable(&priv->rx_napi);
3820 +
3821 +       fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3822 +                    ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3823 +                    FE_REG_PDMA_GLO_CFG);
3824 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3825 +
3826 +       return 0;
3827 +}
3828 +
3829 +static int __init fe_init(struct net_device *dev)
3830 +{
3831 +       struct fe_priv *priv = netdev_priv(dev);
3832 +       struct device_node *port;
3833 +       int err;
3834 +
3835 +       BUG_ON(!priv->soc->reset_fe);
3836 +       priv->soc->reset_fe();
3837 +
3838 +       if (priv->soc->switch_init)
3839 +               priv->soc->switch_init(priv);
3840 +
3841 +       net_srandom(jiffies);
3842 +       memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3843 +       of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3844 +
3845 +       err = fe_mdio_init(priv);
3846 +       if (err)
3847 +               return err;
3848 +
3849 +       if (priv->phy) {
3850 +               err = priv->phy->connect(priv);
3851 +               if (err)
3852 +                       goto err_mdio_cleanup;
3853 +       }
3854 +
3855 +       if (priv->soc->port_init)
3856 +               for_each_child_of_node(priv->device->of_node, port)
3857 +                       if (of_device_is_compatible(port, "ralink,eth-port"))
3858 +                               priv->soc->port_init(priv, port);
3859 +
3860 +       err = fe_hw_init(dev);
3861 +       if (err)
3862 +               goto err_phy_disconnect;
3863 +
3864 +       return 0;
3865 +
3866 +err_phy_disconnect:
3867 +       if (priv->phy)
3868 +               priv->phy->disconnect(priv);
3869 +err_mdio_cleanup:
3870 +       fe_mdio_cleanup(priv);
3871 +
3872 +       return err;
3873 +}
3874 +
3875 +static void fe_uninit(struct net_device *dev)
3876 +{
3877 +       struct fe_priv *priv = netdev_priv(dev);
3878 +
3879 +       tasklet_kill(&priv->tx_tasklet);
3880 +
3881 +       if (priv->phy)
3882 +               priv->phy->disconnect(priv);
3883 +       fe_mdio_cleanup(priv);
3884 +
3885 +       fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3886 +       free_irq(dev->irq, dev);
3887 +
3888 +       fe_free_dma(priv);
3889 +}
3890 +
3891 +static const struct net_device_ops fe_netdev_ops = {
3892 +       .ndo_init               = fe_init,
3893 +       .ndo_uninit             = fe_uninit,
3894 +       .ndo_open               = fe_open,
3895 +       .ndo_stop               = fe_stop,
3896 +       .ndo_start_xmit         = fe_start_xmit,
3897 +       .ndo_tx_timeout         = fe_tx_timeout,
3898 +       .ndo_set_mac_address    = fe_set_mac_address,
3899 +       .ndo_change_mtu         = eth_change_mtu,
3900 +       .ndo_validate_addr      = eth_validate_addr,
3901 +};
3902 +
3903 +static int fe_probe(struct platform_device *pdev)
3904 +{
3905 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3906 +       const struct of_device_id *match;
3907 +       struct fe_soc_data *soc = NULL;
3908 +       struct net_device *netdev;
3909 +       struct fe_priv *priv;
3910 +       struct clk *sysclk;
3911 +       int err;
3912 +
3913 +       match = of_match_device(of_fe_match, &pdev->dev);
3914 +       soc = (struct fe_soc_data *) match->data;
3915 +       if (soc->reg_table)
3916 +               fe_reg_table = soc->reg_table;
3917 +
3918 +       fe_base = devm_request_and_ioremap(&pdev->dev, res);
3919 +       if (!fe_base)
3920 +               return -ENOMEM;
3921 +
3922 +       netdev = alloc_etherdev(sizeof(struct fe_priv));
3923 +       if (!netdev) {
3924 +               dev_err(&pdev->dev, "alloc_etherdev failed\n");
3925 +               return -ENOMEM;
3926 +       }
3927 +
3928 +       strcpy(netdev->name, "eth%d");
3929 +       netdev->netdev_ops = &fe_netdev_ops;
3930 +       netdev->base_addr = (unsigned long) fe_base;
3931 +       netdev->watchdog_timeo = TX_TIMEOUT;
3932 +       netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3933 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3934 +               netdev->features |= NETIF_F_HW_VLAN_TX;
3935 +
3936 +       netdev->irq = platform_get_irq(pdev, 0);
3937 +       if (netdev->irq < 0) {
3938 +               dev_err(&pdev->dev, "no IRQ resource found\n");
3939 +               kfree(netdev);
3940 +               return -ENXIO;
3941 +       }
3942 +
3943 +       priv = netdev_priv(netdev);
3944 +       memset(priv, 0, sizeof(struct fe_priv));
3945 +       spin_lock_init(&priv->page_lock);
3946 +
3947 +       sysclk = devm_clk_get(&pdev->dev, NULL);
3948 +       if (!IS_ERR(sysclk))
3949 +               priv->sysclk = clk_get_rate(sysclk);
3950 +
3951 +       priv->netdev = netdev;
3952 +       priv->device = &pdev->dev;
3953 +       priv->soc = soc;
3954 +
3955 +       err = register_netdev(netdev);
3956 +       if (err) {
3957 +               dev_err(&pdev->dev, "error bringing up device\n");
3958 +               kfree(netdev);
3959 +               return err;
3960 +       }
3961 +       netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
3962 +
3963 +       platform_set_drvdata(pdev, netdev);
3964 +
3965 +       netdev_info(netdev, "done loading\n");
3966 +
3967 +       return 0;
3968 +}
3969 +
3970 +static int fe_remove(struct platform_device *pdev)
3971 +{
3972 +        struct net_device *dev = platform_get_drvdata(pdev);
3973 +       struct fe_priv *priv = netdev_priv(dev);
3974 +
3975 +       netif_stop_queue(dev);
3976 +       netif_napi_del(&priv->rx_napi);
3977 +
3978 +       unregister_netdev(dev);
3979 +       free_netdev(dev);
3980 +
3981 +       return 0;
3982 +}
3983 +
3984 +static struct platform_driver fe_driver = {
3985 +       .probe = fe_probe,
3986 +       .remove = fe_remove,
3987 +       .driver = {
3988 +               .name = "ralink_soc_eth",
3989 +               .owner = THIS_MODULE,
3990 +               .of_match_table = of_fe_match,
3991 +       },
3992 +};
3993 +
3994 +static int __init init_rtfe(void)
3995 +{
3996 +       int ret;
3997 +
3998 +       ret = rtesw_init();
3999 +       if (ret)
4000 +               return ret;
4001 +
4002 +       ret = platform_driver_register(&fe_driver);
4003 +       if (ret)
4004 +               rtesw_exit();
4005 +
4006 +       return ret;
4007 +}
4008 +
4009 +static void __exit exit_rtfe(void)
4010 +{
4011 +       platform_driver_unregister(&fe_driver);
4012 +       rtesw_exit();
4013 +}
4014 +
4015 +module_init(init_rtfe);
4016 +module_exit(exit_rtfe);
4017 +
4018 +MODULE_LICENSE("GPL");
4019 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4020 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4021 --- /dev/null
4022 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4023 @@ -0,0 +1,374 @@
4024 +/*
4025 + *   This program is free software; you can redistribute it and/or modify
4026 + *   it under the terms of the GNU General Public License as published by
4027 + *   the Free Software Foundation; version 2 of the License
4028 + *
4029 + *   This program is distributed in the hope that it will be useful,
4030 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4031 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4032 + *   GNU General Public License for more details.
4033 + *
4034 + *   You should have received a copy of the GNU General Public License
4035 + *   along with this program; if not, write to the Free Software
4036 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4037 + *
4038 + *   based on Ralink SDK3.3
4039 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4040 + */
4041 +
4042 +#ifndef FE_ETH_H
4043 +#define FE_ETH_H
4044 +
4045 +#include <linux/mii.h>
4046 +#include <linux/interrupt.h>
4047 +#include <linux/netdevice.h>
4048 +#include <linux/dma-mapping.h>
4049 +#include <linux/phy.h>
4050 +
4051 +
4052 +enum fe_reg {
4053 +       FE_REG_PDMA_GLO_CFG = 0,
4054 +       FE_REG_PDMA_RST_CFG,
4055 +       FE_REG_DLY_INT_CFG,
4056 +       FE_REG_TX_BASE_PTR0,
4057 +       FE_REG_TX_MAX_CNT0,
4058 +       FE_REG_TX_CTX_IDX0,
4059 +       FE_REG_RX_BASE_PTR0,
4060 +       FE_REG_RX_MAX_CNT0,
4061 +       FE_REG_RX_CALC_IDX0,
4062 +       FE_REG_FE_INT_ENABLE,
4063 +       FE_REG_FE_INT_STATUS,
4064 +       FE_REG_FE_DMA_VID_BASE,
4065 +       FE_REG_COUNT
4066 +};
4067 +
4068 +#define NUM_DMA_DESC           0x100
4069 +
4070 +#define FE_DELAY_EN_INT                0x80
4071 +#define FE_DELAY_MAX_INT       0x04
4072 +#define FE_DELAY_MAX_TOUT      0x04
4073 +#define FE_DELAY_CHAN          (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4074 +#define FE_DELAY_INIT          ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4075 +#define FE_PSE_FQFC_CFG_INIT   0x80504000
4076 +
4077 +/* interrupt bits */
4078 +#define FE_CNT_PPE_AF          BIT(31)
4079 +#define FE_CNT_GDM_AF          BIT(29)
4080 +#define FE_PSE_P2_FC           BIT(26)
4081 +#define FE_PSE_BUF_DROP                BIT(24)
4082 +#define FE_GDM_OTHER_DROP      BIT(23)
4083 +#define FE_PSE_P1_FC           BIT(22)
4084 +#define FE_PSE_P0_FC           BIT(21)
4085 +#define FE_PSE_FQ_EMPTY                BIT(20)
4086 +#define FE_GE1_STA_CHG         BIT(18)
4087 +#define FE_TX_COHERENT         BIT(17)
4088 +#define FE_RX_COHERENT         BIT(16)
4089 +#define FE_TX_DONE_INT3                BIT(11)
4090 +#define FE_TX_DONE_INT2                BIT(10)
4091 +#define FE_TX_DONE_INT1                BIT(9)
4092 +#define FE_TX_DONE_INT0                BIT(8)
4093 +#define FE_RX_DONE_INT0                BIT(2)
4094 +#define FE_TX_DLY_INT          BIT(1)
4095 +#define FE_RX_DLY_INT          BIT(0)
4096 +
4097 +#define RT5350_RX_DLY_INT      BIT(30)
4098 +#define RT5350_TX_DLY_INT      BIT(28)
4099 +
4100 +/* registers */
4101 +#define FE_FE_OFFSET           0x0000
4102 +#define FE_GDMA_OFFSET         0x0020
4103 +#define FE_PSE_OFFSET          0x0040
4104 +#define FE_GDMA2_OFFSET                0x0060
4105 +#define FE_CDMA_OFFSET         0x0080
4106 +#define FE_DMA_VID0            0x00a8
4107 +#define FE_PDMA_OFFSET         0x0100
4108 +#define FE_PPE_OFFSET          0x0200
4109 +#define FE_CMTABLE_OFFSET      0x0400
4110 +#define FE_POLICYTABLE_OFFSET  0x1000
4111 +
4112 +#define RT5350_PDMA_OFFSET     0x0800
4113 +#define RT5350_SDM_OFFSET      0x0c00
4114 +
4115 +#define FE_MDIO_ACCESS         (FE_FE_OFFSET + 0x00)
4116 +#define FE_MDIO_CFG            (FE_FE_OFFSET + 0x04)
4117 +#define FE_FE_GLO_CFG          (FE_FE_OFFSET + 0x08)
4118 +#define FE_FE_RST_GL           (FE_FE_OFFSET + 0x0C)
4119 +#define FE_FE_INT_STATUS       (FE_FE_OFFSET + 0x10)
4120 +#define FE_FE_INT_ENABLE       (FE_FE_OFFSET + 0x14)
4121 +#define FE_MDIO_CFG2           (FE_FE_OFFSET + 0x18)
4122 +#define FE_FOC_TS_T            (FE_FE_OFFSET + 0x1C)
4123 +
4124 +#define        FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
4125 +#define FE_GDMA1_SCH_CFG       (FE_GDMA_OFFSET + 0x04)
4126 +#define FE_GDMA1_SHPR_CFG      (FE_GDMA_OFFSET + 0x08)
4127 +#define FE_GDMA1_MAC_ADRL      (FE_GDMA_OFFSET + 0x0C)
4128 +#define FE_GDMA1_MAC_ADRH      (FE_GDMA_OFFSET + 0x10)
4129 +
4130 +#define        FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
4131 +#define FE_GDMA2_SCH_CFG       (FE_GDMA2_OFFSET + 0x04)
4132 +#define FE_GDMA2_SHPR_CFG      (FE_GDMA2_OFFSET + 0x08)
4133 +#define FE_GDMA2_MAC_ADRL      (FE_GDMA2_OFFSET + 0x0C)
4134 +#define FE_GDMA2_MAC_ADRH      (FE_GDMA2_OFFSET + 0x10)
4135 +
4136 +#define FE_PSE_FQ_CFG          (FE_PSE_OFFSET + 0x00)
4137 +#define FE_CDMA_FC_CFG         (FE_PSE_OFFSET + 0x04)
4138 +#define FE_GDMA1_FC_CFG                (FE_PSE_OFFSET + 0x08)
4139 +#define FE_GDMA2_FC_CFG                (FE_PSE_OFFSET + 0x0C)
4140 +
4141 +#define FE_CDMA_CSG_CFG                (FE_CDMA_OFFSET + 0x00)
4142 +#define FE_CDMA_SCH_CFG                (FE_CDMA_OFFSET + 0x04)
4143 +
4144 +#define MT7620A_GDMA_OFFSET            0x0600
4145 +#define        MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
4146 +#define MT7620A_FE_GDMA1_SCH_CFG       (MT7620A_GDMA_OFFSET + 0x04)
4147 +#define MT7620A_FE_GDMA1_SHPR_CFG      (MT7620A_GDMA_OFFSET + 0x08)
4148 +#define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
4149 +#define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
4150 +
4151 +#define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
4152 +#define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
4153 +#define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)
4154 +#define RT5350_TX_DTX_IDX0     (RT5350_PDMA_OFFSET + 0x0C)
4155 +#define RT5350_TX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x10)
4156 +#define RT5350_TX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x14)
4157 +#define RT5350_TX_CTX_IDX1     (RT5350_PDMA_OFFSET + 0x18)
4158 +#define RT5350_TX_DTX_IDX1     (RT5350_PDMA_OFFSET + 0x1C)
4159 +#define RT5350_TX_BASE_PTR2    (RT5350_PDMA_OFFSET + 0x20)
4160 +#define RT5350_TX_MAX_CNT2     (RT5350_PDMA_OFFSET + 0x24)
4161 +#define RT5350_TX_CTX_IDX2     (RT5350_PDMA_OFFSET + 0x28)
4162 +#define RT5350_TX_DTX_IDX2     (RT5350_PDMA_OFFSET + 0x2C)
4163 +#define RT5350_TX_BASE_PTR3    (RT5350_PDMA_OFFSET + 0x30)
4164 +#define RT5350_TX_MAX_CNT3     (RT5350_PDMA_OFFSET + 0x34)
4165 +#define RT5350_TX_CTX_IDX3     (RT5350_PDMA_OFFSET + 0x38)
4166 +#define RT5350_TX_DTX_IDX3     (RT5350_PDMA_OFFSET + 0x3C)
4167 +#define RT5350_RX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x100)
4168 +#define RT5350_RX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x104)
4169 +#define RT5350_RX_CALC_IDX0    (RT5350_PDMA_OFFSET + 0x108)
4170 +#define RT5350_RX_DRX_IDX0     (RT5350_PDMA_OFFSET + 0x10C)
4171 +#define RT5350_RX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x110)
4172 +#define RT5350_RX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x114)
4173 +#define RT5350_RX_CALC_IDX1    (RT5350_PDMA_OFFSET + 0x118)
4174 +#define RT5350_RX_DRX_IDX1     (RT5350_PDMA_OFFSET + 0x11C)
4175 +#define RT5350_PDMA_GLO_CFG    (RT5350_PDMA_OFFSET + 0x204)
4176 +#define RT5350_PDMA_RST_CFG    (RT5350_PDMA_OFFSET + 0x208)
4177 +#define RT5350_DLY_INT_CFG     (RT5350_PDMA_OFFSET + 0x20c)
4178 +#define RT5350_FE_INT_STATUS   (RT5350_PDMA_OFFSET + 0x220)
4179 +#define RT5350_FE_INT_ENABLE   (RT5350_PDMA_OFFSET + 0x228)
4180 +#define RT5350_PDMA_SCH_CFG    (RT5350_PDMA_OFFSET + 0x280)
4181 +
4182 +#define FE_PDMA_GLO_CFG                (FE_PDMA_OFFSET + 0x00)
4183 +#define FE_PDMA_RST_CFG                (FE_PDMA_OFFSET + 0x04)
4184 +#define FE_PDMA_SCH_CFG                (FE_PDMA_OFFSET + 0x08)
4185 +#define FE_DLY_INT_CFG         (FE_PDMA_OFFSET + 0x0C)
4186 +#define FE_TX_BASE_PTR0                (FE_PDMA_OFFSET + 0x10)
4187 +#define FE_TX_MAX_CNT0         (FE_PDMA_OFFSET + 0x14)
4188 +#define FE_TX_CTX_IDX0         (FE_PDMA_OFFSET + 0x18)
4189 +#define FE_TX_DTX_IDX0         (FE_PDMA_OFFSET + 0x1C)
4190 +#define FE_TX_BASE_PTR1                (FE_PDMA_OFFSET + 0x20)
4191 +#define FE_TX_MAX_CNT1         (FE_PDMA_OFFSET + 0x24)
4192 +#define FE_TX_CTX_IDX1         (FE_PDMA_OFFSET + 0x28)
4193 +#define FE_TX_DTX_IDX1         (FE_PDMA_OFFSET + 0x2C)
4194 +#define FE_RX_BASE_PTR0                (FE_PDMA_OFFSET + 0x30)
4195 +#define FE_RX_MAX_CNT0         (FE_PDMA_OFFSET + 0x34)
4196 +#define FE_RX_CALC_IDX0                (FE_PDMA_OFFSET + 0x38)
4197 +#define FE_RX_DRX_IDX0         (FE_PDMA_OFFSET + 0x3C)
4198 +#define FE_TX_BASE_PTR2                (FE_PDMA_OFFSET + 0x40)
4199 +#define FE_TX_MAX_CNT2         (FE_PDMA_OFFSET + 0x44)
4200 +#define FE_TX_CTX_IDX2         (FE_PDMA_OFFSET + 0x48)
4201 +#define FE_TX_DTX_IDX2         (FE_PDMA_OFFSET + 0x4C)
4202 +#define FE_TX_BASE_PTR3                (FE_PDMA_OFFSET + 0x50)
4203 +#define FE_TX_MAX_CNT3         (FE_PDMA_OFFSET + 0x54)
4204 +#define FE_TX_CTX_IDX3         (FE_PDMA_OFFSET + 0x58)
4205 +#define FE_TX_DTX_IDX3         (FE_PDMA_OFFSET + 0x5C)
4206 +#define FE_RX_BASE_PTR1                (FE_PDMA_OFFSET + 0x60)
4207 +#define FE_RX_MAX_CNT1         (FE_PDMA_OFFSET + 0x64)
4208 +#define FE_RX_CALC_IDX1                (FE_PDMA_OFFSET + 0x68)
4209 +#define FE_RX_DRX_IDX1         (FE_PDMA_OFFSET + 0x6C)
4210 +
4211 +#define RT5350_SDM_CFG         (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
4212 +#define RT5350_SDM_RRING       (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
4213 +#define RT5350_SDM_TRING       (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
4214 +#define RT5350_SDM_MAC_ADRL    (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
4215 +#define RT5350_SDM_MAC_ADRH    (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
4216 +#define RT5350_SDM_TPCNT       (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4217 +#define RT5350_SDM_TBCNT       (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4218 +#define RT5350_SDM_RPCNT       (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4219 +#define RT5350_SDM_RBCNT       (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4220 +#define RT5350_SDM_CS_ERR      (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4221 +
4222 +#define RT5350_SDM_ICS_EN      BIT(16)
4223 +#define RT5350_SDM_TCS_EN      BIT(17)
4224 +#define RT5350_SDM_UCS_EN      BIT(18)
4225 +
4226 +
4227 +/* MDIO_CFG register bits */
4228 +#define FE_MDIO_CFG_AUTO_POLL_EN       BIT(29)
4229 +#define FE_MDIO_CFG_GP1_BP_EN          BIT(16)
4230 +#define FE_MDIO_CFG_GP1_FRC_EN         BIT(15)
4231 +#define FE_MDIO_CFG_GP1_SPEED_10       (0 << 13)
4232 +#define FE_MDIO_CFG_GP1_SPEED_100      (1 << 13)
4233 +#define FE_MDIO_CFG_GP1_SPEED_1000     (2 << 13)
4234 +#define FE_MDIO_CFG_GP1_DUPLEX         BIT(12)
4235 +#define FE_MDIO_CFG_GP1_FC_TX          BIT(11)
4236 +#define FE_MDIO_CFG_GP1_FC_RX          BIT(10)
4237 +#define FE_MDIO_CFG_GP1_LNK_DWN                BIT(9)
4238 +#define FE_MDIO_CFG_GP1_AN_FAIL                BIT(8)
4239 +#define FE_MDIO_CFG_MDC_CLK_DIV_1      (0 << 6)
4240 +#define FE_MDIO_CFG_MDC_CLK_DIV_2      (1 << 6)
4241 +#define FE_MDIO_CFG_MDC_CLK_DIV_4      (2 << 6)
4242 +#define FE_MDIO_CFG_MDC_CLK_DIV_8      (3 << 6)
4243 +#define FE_MDIO_CFG_TURBO_MII_FREQ     BIT(5)
4244 +#define FE_MDIO_CFG_TURBO_MII_MODE     BIT(4)
4245 +#define FE_MDIO_CFG_RX_CLK_SKEW_0      (0 << 2)
4246 +#define FE_MDIO_CFG_RX_CLK_SKEW_200    (1 << 2)
4247 +#define FE_MDIO_CFG_RX_CLK_SKEW_400    (2 << 2)
4248 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV    (3 << 2)
4249 +#define FE_MDIO_CFG_TX_CLK_SKEW_0      0
4250 +#define FE_MDIO_CFG_TX_CLK_SKEW_200    1
4251 +#define FE_MDIO_CFG_TX_CLK_SKEW_400    2
4252 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV    3
4253 +
4254 +/* uni-cast port */
4255 +#define FE_GDM1_ICS_EN         BIT(22)
4256 +#define FE_GDM1_TCS_EN         BIT(21)
4257 +#define FE_GDM1_UCS_EN         BIT(20)
4258 +#define FE_GDM1_JMB_EN         BIT(19)
4259 +#define FE_GDM1_STRPCRC                BIT(16)
4260 +#define FE_GDM1_UFRC_P_CPU     (0 << 12)
4261 +#define FE_GDM1_UFRC_P_GDMA1   (1 << 12)
4262 +#define FE_GDM1_UFRC_P_PPE     (6 << 12)
4263 +
4264 +/* checksums */
4265 +#define FE_ICS_GEN_EN          BIT(2)
4266 +#define FE_UCS_GEN_EN          BIT(1)
4267 +#define FE_TCS_GEN_EN          BIT(0)
4268 +
4269 +/* dma ring */
4270 +#define FE_PST_DRX_IDX0                BIT(16)
4271 +#define FE_PST_DTX_IDX3                BIT(3)
4272 +#define FE_PST_DTX_IDX2                BIT(2)
4273 +#define FE_PST_DTX_IDX1                BIT(1)
4274 +#define FE_PST_DTX_IDX0                BIT(0)
4275 +
4276 +#define FE_TX_WB_DDONE         BIT(6)
4277 +#define FE_RX_DMA_BUSY         BIT(3)
4278 +#define FE_TX_DMA_BUSY         BIT(1)
4279 +#define FE_RX_DMA_EN           BIT(2)
4280 +#define FE_TX_DMA_EN           BIT(0)
4281 +
4282 +#define FE_PDMA_SIZE_4DWORDS   (0 << 4)
4283 +#define FE_PDMA_SIZE_8DWORDS   (1 << 4)
4284 +#define FE_PDMA_SIZE_16DWORDS  (2 << 4)
4285 +
4286 +#define FE_US_CYC_CNT_MASK     0xff
4287 +#define FE_US_CYC_CNT_SHIFT    0x8
4288 +#define FE_US_CYC_CNT_DIVISOR  1000000
4289 +
4290 +#define RX_DMA_PLEN0(_x)       (((_x) >> 16) & 0x3fff)
4291 +#define RX_DMA_LSO             BIT(30)
4292 +#define RX_DMA_DONE            BIT(31)
4293 +#define RX_DMA_L4VALID         BIT(30)
4294 +
4295 +struct fe_rx_dma {
4296 +       unsigned int rxd1;
4297 +       unsigned int rxd2;
4298 +       unsigned int rxd3;
4299 +       unsigned int rxd4;
4300 +} __packed __aligned(4);
4301 +
4302 +#define TX_DMA_PLEN0_MASK      ((0x3fff) << 16)
4303 +#define TX_DMA_PLEN0(_x)       (((_x) & 0x3fff) << 16)
4304 +#define TX_DMA_LSO             BIT(30)
4305 +#define TX_DMA_DONE            BIT(31)
4306 +#define TX_DMA_QN(_x)          ((_x) << 16)
4307 +#define TX_DMA_PN(_x)          ((_x) << 24)
4308 +#define TX_DMA_QN_MASK         TX_DMA_QN(0x7)
4309 +#define TX_DMA_PN_MASK         TX_DMA_PN(0x7)
4310 +#define TX_DMA_CHKSUM          (0x7 << 29)
4311 +
4312 +struct fe_tx_dma {
4313 +       unsigned int txd1;
4314 +       unsigned int txd2;
4315 +       unsigned int txd3;
4316 +       unsigned int txd4;
4317 +} __packed __aligned(4);
4318 +
4319 +struct fe_priv;
4320 +
4321 +struct fe_phy {
4322 +       struct phy_device       *phy[8];
4323 +       struct device_node      *phy_node[8];
4324 +       const __be32            *phy_fixed[8];
4325 +       int                     duplex[8];
4326 +       int                     speed[8];
4327 +       int                     tx_fc[8];
4328 +       int                     rx_fc[8];
4329 +       spinlock_t              lock;
4330 +
4331 +       int (*connect)(struct fe_priv *priv);
4332 +       void (*disconnect)(struct fe_priv *priv);
4333 +       void (*start)(struct fe_priv *priv);
4334 +       void (*stop)(struct fe_priv *priv);
4335 +};
4336 +
4337 +struct fe_soc_data
4338 +{
4339 +       unsigned char mac[6];
4340 +       const u32 *reg_table;
4341 +
4342 +       void (*reset_fe)(void);
4343 +       void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4344 +       void (*fwd_config)(struct fe_priv *priv);
4345 +       void (*tx_dma)(struct fe_priv *priv, int idx, int len);
4346 +       void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4347 +       int (*switch_init)(struct fe_priv *priv);
4348 +       void (*port_init)(struct fe_priv *priv, struct device_node *port);
4349 +       int (*has_carrier)(struct fe_priv *priv);
4350 +       int (*mdio_init)(struct fe_priv *priv);
4351 +       void (*mdio_cleanup)(struct fe_priv *priv);
4352 +       int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4353 +       int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4354 +       void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4355 +
4356 +       void *swpriv;
4357 +       u32 pdma_glo_cfg;
4358 +       u32 rx_dly_int;
4359 +       u32 tx_dly_int;
4360 +       u32 checksum_bit;
4361 +
4362 +       int min_pkt_len;
4363 +};
4364 +
4365 +struct fe_priv
4366 +{
4367 +       spinlock_t                      page_lock;
4368 +
4369 +       struct fe_soc_data              *soc;
4370 +       struct net_device               *netdev;
4371 +       struct device                   *device;
4372 +       unsigned long                   sysclk;
4373 +
4374 +       struct fe_rx_dma                *rx_dma;
4375 +        struct napi_struct             rx_napi;
4376 +       struct sk_buff                  *rx_skb[NUM_DMA_DESC];
4377 +       dma_addr_t                      rx_phys;
4378 +
4379 +       struct fe_tx_dma                *tx_dma;
4380 +       struct tasklet_struct           tx_tasklet;
4381 +       struct sk_buff                  *tx_skb[NUM_DMA_DESC];
4382 +       dma_addr_t                      tx_phys;
4383 +       unsigned int                    tx_free_idx;
4384 +
4385 +       struct fe_phy                   *phy;
4386 +       struct mii_bus                  *mii_bus;
4387 +       int                             mii_irq[PHY_MAX_ADDR];
4388 +
4389 +       int                             link[8];
4390 +};
4391 +
4392 +extern const struct of_device_id of_fe_match[];
4393 +
4394 +void fe_w32(u32 val, unsigned reg);
4395 +u32 fe_r32(unsigned reg);
4396 +
4397 +#endif /* FE_ETH_H */
4398 --- /dev/null
4399 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
4400 @@ -0,0 +1,111 @@
4401 +/*
4402 + *   This program is free software; you can redistribute it and/or modify
4403 + *   it under the terms of the GNU General Public License as published by
4404 + *   the Free Software Foundation; version 2 of the License
4405 + *
4406 + *   This program is distributed in the hope that it will be useful,
4407 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4408 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4409 + *   GNU General Public License for more details.
4410 + *
4411 + *   You should have received a copy of the GNU General Public License
4412 + *   along with this program; if not, write to the Free Software
4413 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4414 + *
4415 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4416 + */
4417 +
4418 +#include <linux/module.h>
4419 +#include <linux/platform_device.h>
4420 +
4421 +#include <asm/mach-ralink/ralink_regs.h>
4422 +
4423 +#include "ralink_soc_eth.h"
4424 +#include "gsw_mt7620a.h"
4425 +
4426 +#define MT7620A_CDMA_CSG_CFG   0x400
4427 +#define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
4428 +#define MT7620A_DMA_2B_OFFSET  BIT(31)
4429 +#define MT7620A_RESET_FE       BIT(21)
4430 +#define MT7620A_RESET_ESW      BIT(23)
4431 +#define MT7620_L4_VALID                BIT(23)
4432 +
4433 +#define SYSC_REG_RESET_CTRL     0x34
4434 +#define MAX_RX_LENGTH           1536
4435 +
4436 +#define CDMA_ICS_EN            BIT(2)
4437 +#define CDMA_UCS_EN            BIT(1)
4438 +#define CDMA_TCS_EN            BIT(0)
4439 +
4440 +#define GDMA_ICS_EN            BIT(22)
4441 +#define GDMA_TCS_EN            BIT(21)
4442 +#define GDMA_UCS_EN            BIT(20)
4443 +
4444 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4445 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4446 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4447 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4448 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4449 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4450 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4451 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4452 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4453 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4454 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4455 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4456 +       [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4457 +};
4458 +
4459 +static void mt7620_fe_reset(void)
4460 +{
4461 +       rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4462 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4463 +}
4464 +
4465 +static void mt7620_fwd_config(struct fe_priv *priv)
4466 +{
4467 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4468 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4469 +       fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4470 +}
4471 +
4472 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len)
4473 +{
4474 +       if (len)
4475 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4476 +       else
4477 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4478 +}
4479 +
4480 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4481 +{
4482 +       priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4483 +}
4484 +
4485 +static struct fe_soc_data mt7620_data = {
4486 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4487 +       .reset_fe = mt7620_fe_reset,
4488 +       .set_mac = mt7620_set_mac,
4489 +       .fwd_config = mt7620_fwd_config,
4490 +       .tx_dma = mt7620_tx_dma,
4491 +       .rx_dma = mt7620_rx_dma,
4492 +       .switch_init = mt7620_gsw_probe,
4493 +       .port_init = mt7620_port_init,
4494 +       .min_pkt_len = 0,
4495 +       .reg_table = rt5350_reg_table,
4496 +       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4497 +       .rx_dly_int = RT5350_RX_DLY_INT,
4498 +       .tx_dly_int = RT5350_TX_DLY_INT,
4499 +       .checksum_bit = MT7620_L4_VALID,
4500 +       .has_carrier = mt7620a_has_carrier,
4501 +       .mdio_read = mt7620_mdio_read,
4502 +       .mdio_write = mt7620_mdio_write,
4503 +       .mdio_adjust_link = mt7620_mdio_link_adjust,
4504 +};
4505 +
4506 +const struct of_device_id of_fe_match[] = {
4507 +       { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4508 +       {},
4509 +};
4510 +
4511 +MODULE_DEVICE_TABLE(of, of_fe_match);
4512 --- /dev/null
4513 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4514 @@ -0,0 +1,51 @@
4515 +/*
4516 + *   This program is free software; you can redistribute it and/or modify
4517 + *   it under the terms of the GNU General Public License as published by
4518 + *   the Free Software Foundation; version 2 of the License
4519 + *
4520 + *   This program is distributed in the hope that it will be useful,
4521 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4522 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4523 + *   GNU General Public License for more details.
4524 + *
4525 + *   You should have received a copy of the GNU General Public License
4526 + *   along with this program; if not, write to the Free Software
4527 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4528 + *
4529 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4530 + */
4531 +
4532 +#include <linux/module.h>
4533 +
4534 +#include <asm/mach-ralink/ralink_regs.h>
4535 +
4536 +#include "ralink_soc_eth.h"
4537 +#include "mdio_rt2880.h"
4538 +
4539 +#define SYSC_REG_RESET_CTRL            0x034
4540 +#define RT2880_RESET_FE                        BIT(18)
4541 +
4542 +void rt2880_fe_reset(void)
4543 +{
4544 +       rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4545 +}
4546 +
4547 +struct fe_soc_data rt2880_data = {
4548 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4549 +       .reset_fe = rt2880_fe_reset,
4550 +       .min_pkt_len = 64,
4551 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4552 +       .checksum_bit = RX_DMA_L4VALID,
4553 +       .rx_dly_int = FE_RX_DLY_INT,
4554 +       .tx_dly_int = FE_TX_DLY_INT,
4555 +       .mdio_read = rt2880_mdio_read,
4556 +       .mdio_write = rt2880_mdio_write,
4557 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
4558 +};
4559 +
4560 +const struct of_device_id of_fe_match[] = {
4561 +       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4562 +       {},
4563 +};
4564 +
4565 +MODULE_DEVICE_TABLE(of, of_fe_match);
4566 --- /dev/null
4567 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4568 @@ -0,0 +1,113 @@
4569 +/*
4570 + *   This program is free software; you can redistribute it and/or modify
4571 + *   it under the terms of the GNU General Public License as published by
4572 + *   the Free Software Foundation; version 2 of the License
4573 + *
4574 + *   This program is distributed in the hope that it will be useful,
4575 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4576 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4577 + *   GNU General Public License for more details.
4578 + *
4579 + *   You should have received a copy of the GNU General Public License
4580 + *   along with this program; if not, write to the Free Software
4581 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4582 + *
4583 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4584 + */
4585 +
4586 +#include <linux/module.h>
4587 +
4588 +#include <asm/mach-ralink/ralink_regs.h>
4589 +
4590 +#include "ralink_soc_eth.h"
4591 +
4592 +#define RT305X_RESET_FE         BIT(21)
4593 +#define RT305X_RESET_ESW        BIT(23)
4594 +#define SYSC_REG_RESET_CTRL     0x034
4595 +
4596 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4597 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4598 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4599 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4600 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4601 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4602 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4603 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4604 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4605 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4606 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4607 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4608 +       [FE_REG_FE_DMA_VID_BASE] = 0,
4609 +};
4610 +
4611 +static void rt305x_fe_reset(void)
4612 +{
4613 +       rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4614 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4615 +}
4616 +
4617 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4618 +{
4619 +       unsigned long flags;
4620 +
4621 +       spin_lock_irqsave(&priv->page_lock, flags);
4622 +       fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4623 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4624 +               RT5350_SDM_MAC_ADRL);
4625 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4626 +}
4627 +
4628 +static void rt5350_fwd_config(struct fe_priv *priv)
4629 +{
4630 +       unsigned long sysclk = priv->sysclk;
4631 +
4632 +       if (sysclk) {
4633 +               sysclk /= FE_US_CYC_CNT_DIVISOR;
4634 +               sysclk <<= FE_US_CYC_CNT_SHIFT;
4635 +
4636 +               fe_w32((fe_r32(FE_FE_GLO_CFG) &
4637 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4638 +                       FE_FE_GLO_CFG);
4639 +       }
4640 +
4641 +       fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4642 +       fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4643 +               RT5350_SDM_CFG);
4644 +}
4645 +
4646 +static void rt5350_fe_reset(void)
4647 +{
4648 +       rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4649 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4650 +}
4651 +
4652 +static struct fe_soc_data rt3050_data = {
4653 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4654 +       .reset_fe = rt305x_fe_reset,
4655 +       .min_pkt_len = 64,
4656 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4657 +       .checksum_bit = RX_DMA_L4VALID,
4658 +       .rx_dly_int = FE_RX_DLY_INT,
4659 +       .tx_dly_int = FE_TX_DLY_INT,
4660 +};
4661 +
4662 +static struct fe_soc_data rt5350_data = {
4663 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4664 +       .reg_table = rt5350_reg_table,
4665 +       .reset_fe = rt5350_fe_reset,
4666 +       .set_mac = rt5350_set_mac,
4667 +       .fwd_config = rt5350_fwd_config,
4668 +       .min_pkt_len = 64,
4669 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4670 +       .checksum_bit = RX_DMA_L4VALID,
4671 +       .rx_dly_int = RT5350_RX_DLY_INT,
4672 +       .tx_dly_int = RT5350_TX_DLY_INT,
4673 +};
4674 +
4675 +const struct of_device_id of_fe_match[] = {
4676 +       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4677 +       { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4678 +       {},
4679 +};
4680 +
4681 +MODULE_DEVICE_TABLE(of, of_fe_match);
4682 --- /dev/null
4683 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
4684 @@ -0,0 +1,60 @@
4685 +/*
4686 + *   This program is free software; you can redistribute it and/or modify
4687 + *   it under the terms of the GNU General Public License as published by
4688 + *   the Free Software Foundation; version 2 of the License
4689 + *
4690 + *   This program is distributed in the hope that it will be useful,
4691 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4692 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4693 + *   GNU General Public License for more details.
4694 + *
4695 + *   You should have received a copy of the GNU General Public License
4696 + *   along with this program; if not, write to the Free Software
4697 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4698 + *
4699 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4700 + */
4701 +
4702 +#include <linux/module.h>
4703 +
4704 +#include <asm/mach-ralink/ralink_regs.h>
4705 +
4706 +#include "ralink_soc_eth.h"
4707 +#include "mdio_rt2880.h"
4708 +
4709 +#define RT3883_SYSC_REG_RSTCTRL                0x34
4710 +#define RT3883_RSTCTRL_FE              BIT(21)
4711 +
4712 +static void rt3883_fe_reset(void)
4713 +{
4714 +       u32 t;
4715 +
4716 +       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
4717 +       t |= RT3883_RSTCTRL_FE;
4718 +       rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
4719 +
4720 +       t &= ~RT3883_RSTCTRL_FE;
4721 +       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
4722 +}
4723 +
4724 +static struct fe_soc_data rt3883_data = {
4725 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4726 +       .reset_fe = rt3883_fe_reset,
4727 +       .min_pkt_len = 64,
4728 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4729 +       .rx_dly_int = FE_RX_DLY_INT,
4730 +       .tx_dly_int = FE_TX_DLY_INT,
4731 +       .checksum_bit = RX_DMA_L4VALID,
4732 +       .mdio_read = rt2880_mdio_read,
4733 +       .mdio_write = rt2880_mdio_write,
4734 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
4735 +       .port_init = rt2880_port_init,
4736 +};
4737 +
4738 +const struct of_device_id of_fe_match[] = {
4739 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
4740 +       {},
4741 +};
4742 +
4743 +MODULE_DEVICE_TABLE(of, of_fe_match);
4744 +