target/linux/ramips/patches-3.9/0130-MIPS-ralink-add-support-for-periodic-timer-irq.patch

   1 From f8496dd6c8fbcfd159390c31791fe2a86e48acb9 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 23 Mar 2013 19:44:41 +0100
   4 Subject: [PATCH 130/164] MIPS: ralink: add support for periodic timer irq
   5
   6 Adds a driver for the periodic timer found on Ralink SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/ralink/Makefile |    2 +-
  11  arch/mips/ralink/timer.c  |  192 +++++++++++++++++++++++++++++++++++++++++++++
  12  2 files changed, 193 insertions(+), 1 deletion(-)
  13  create mode 100644 arch/mips/ralink/timer.c
  14
  15 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
  16 index 341b4de..cae7d88 100644
  17 --- a/arch/mips/ralink/Makefile
  18 +++ b/arch/mips/ralink/Makefile
  19 @@ -6,7 +6,7 @@
  20  # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  21  # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  22
  23 -obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
  24 +obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
  25
  26  obj-$(CONFIG_SOC_RT288X) += rt288x.o
  27  obj-$(CONFIG_SOC_RT305X) += rt305x.o
  28 diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
  29 new file mode 100644
  30 index 0000000..0a6856c
  31 --- /dev/null
  32 +++ b/arch/mips/ralink/timer.c
  33 @@ -0,0 +1,192 @@
  34 +/*
  35 + * This program is free software; you can redistribute it and/or modify it
  36 + * under the terms of the GNU General Public License version 2 as published
  37 + * by the Free Software Foundation.
  38 + *
  39 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  40 +*/
  41 +
  42 +#include <linux/module.h>
  43 +#include <linux/platform_device.h>
  44 +#include <linux/interrupt.h>
  45 +#include <linux/timer.h>
  46 +#include <linux/of_gpio.h>
  47 +#include <linux/clk.h>
  48 +
  49 +#include <asm/mach-ralink/ralink_regs.h>
  50 +
  51 +#define TIMER_REG_TMRSTAT              0x00
  52 +#define TIMER_REG_TMR0LOAD             0x10
  53 +#define TIMER_REG_TMR0CTL              0x18
  54 +
  55 +#define TMRSTAT_TMR0INT                        BIT(0)
  56 +
  57 +#define TMR0CTL_ENABLE                 BIT(7)
  58 +#define TMR0CTL_MODE_PERIODIC          BIT(4)
  59 +#define TMR0CTL_PRESCALER              1
  60 +#define TMR0CTL_PRESCALE_VAL           (0xf - TMR0CTL_PRESCALER)
  61 +#define TMR0CTL_PRESCALE_DIV           (65536 / BIT(TMR0CTL_PRESCALER))
  62 +
  63 +struct rt_timer {
  64 +       struct device   *dev;
  65 +       void __iomem    *membase;
  66 +       int             irq;
  67 +       unsigned long   timer_freq;
  68 +       unsigned long   timer_div;
  69 +};
  70 +
  71 +static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
  72 +{
  73 +       __raw_writel(val, rt->membase + reg);
  74 +}
  75 +
  76 +static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
  77 +{
  78 +       return __raw_readl(rt->membase + reg);
  79 +}
  80 +
  81 +static irqreturn_t rt_timer_irq(int irq, void *_rt)
  82 +{
  83 +       struct rt_timer *rt =  (struct rt_timer *) _rt;
  84 +
  85 +       rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
  86 +       rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
  87 +
  88 +       return IRQ_HANDLED;
  89 +}
  90 +
  91 +
  92 +static int rt_timer_request(struct rt_timer *rt)
  93 +{
  94 +       int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
  95 +                                               dev_name(rt->dev), rt);
  96 +       if (err) {
  97 +               dev_err(rt->dev, "failed to request irq\n");
  98 +       } else {
  99 +               u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
 100 +               rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
 101 +       }
 102 +       return err;
 103 +}
 104 +
 105 +static void rt_timer_free(struct rt_timer *rt)
 106 +{
 107 +       free_irq(rt->irq, rt);
 108 +}
 109 +
 110 +static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
 111 +{
 112 +       if (rt->timer_freq < divisor)
 113 +               rt->timer_div = rt->timer_freq;
 114 +       else
 115 +               rt->timer_div = divisor;
 116 +
 117 +       rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
 118 +
 119 +       return 0;
 120 +}
 121 +
 122 +static int rt_timer_enable(struct rt_timer *rt)
 123 +{
 124 +       u32 t;
 125 +
 126 +       rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
 127 +
 128 +       t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
 129 +       t |= TMR0CTL_ENABLE;
 130 +       rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
 131 +
 132 +       return 0;
 133 +}
 134 +
 135 +static void rt_timer_disable(struct rt_timer *rt)
 136 +{
 137 +       u32 t;
 138 +
 139 +       t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
 140 +       t &= ~TMR0CTL_ENABLE;
 141 +       rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
 142 +}
 143 +
 144 +static int rt_timer_probe(struct platform_device *pdev)
 145 +{
 146 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 147 +       struct rt_timer *rt;
 148 +       struct clk *clk;
 149 +
 150 +       if (!res) {
 151 +               dev_err(&pdev->dev, "no memory resource found\n");
 152 +               return -EINVAL;
 153 +       }
 154 +
 155 +       rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
 156 +       if (!rt) {
 157 +               dev_err(&pdev->dev, "failed to allocate memory\n");
 158 +               return -ENOMEM;
 159 +       }
 160 +
 161 +       rt->irq = platform_get_irq(pdev, 0);
 162 +       if (!rt->irq) {
 163 +               dev_err(&pdev->dev, "failed to load irq\n");
 164 +               return -ENOENT;
 165 +       }
 166 +
 167 +       rt->membase = devm_request_and_ioremap(&pdev->dev, res);
 168 +       if (!rt->membase) {
 169 +               dev_err(&pdev->dev, "failed to ioremap\n");
 170 +               return -ENOMEM;
 171 +       }
 172 +
 173 +       clk = devm_clk_get(&pdev->dev, NULL);
 174 +       if (IS_ERR(clk)) {
 175 +               dev_err(&pdev->dev, "failed get clock rate\n");
 176 +               return PTR_ERR(clk);
 177 +       }
 178 +
 179 +       rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
 180 +       if (!rt->timer_freq)
 181 +               return -EINVAL;
 182 +
 183 +       rt->dev = &pdev->dev;
 184 +       platform_set_drvdata(pdev, rt);
 185 +
 186 +       rt_timer_request(rt);
 187 +       rt_timer_config(rt, 2);
 188 +       rt_timer_enable(rt);
 189 +
 190 +       dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
 191 +
 192 +       return 0;
 193 +}
 194 +
 195 +static int rt_timer_remove(struct platform_device *pdev)
 196 +{
 197 +       struct rt_timer *rt = platform_get_drvdata(pdev);
 198 +
 199 +       rt_timer_disable(rt);
 200 +       rt_timer_free(rt);
 201 +
 202 +       return 0;
 203 +}
 204 +
 205 +static const struct of_device_id rt_timer_match[] = {
 206 +       { .compatible = "ralink,rt2880-timer" },
 207 +       {},
 208 +};
 209 +MODULE_DEVICE_TABLE(of, rt_timer_match);
 210 +
 211 +static struct platform_driver rt_timer_driver = {
 212 +       .probe = rt_timer_probe,
 213 +       .remove = rt_timer_remove,
 214 +       .driver = {
 215 +               .name           = "rt-timer",
 216 +               .owner          = THIS_MODULE,
 217 +               .of_match_table = rt_timer_match
 218 +       },
 219 +};
 220 +
 221 +module_platform_driver(rt_timer_driver);
 222 +
 223 +MODULE_DESCRIPTION("Ralink RT2880 timer");
 224 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
 225 +MODULE_LICENSE("GPL");
 226 --
 227 1.7.10.4
 228