target/linux/ramips/patches-3.9/0102-MIPS-ralink-add-RT3352-register-defines.patch

   1 From 48cf6bc7019d418e18831214731a55ec7320abb3 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 19:01:49 +0100
   4 Subject: [PATCH 102/164] MIPS: ralink: add RT3352 register defines
   5
   6 Add a few missing defines that are needed to make USB and clock detection work
   7 on the RT3352.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Acked-by: Gabor Juhos <juhosg@openwrt.org>
  11 Patchwork: http://patchwork.linux-mips.org/patch/5166/
  12 ---
  13  arch/mips/include/asm/mach-ralink/rt305x.h |   13 +++++++++++++
  14  1 file changed, 13 insertions(+)
  15
  16 diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
  17 index 7d344f2..e36c3c5 100644
  18 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
  19 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
  20 @@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
  21  #define RT305X_GPIO_MODE_SDRAM         BIT(8)
  22  #define RT305X_GPIO_MODE_RGMII         BIT(9)
  23
  24 +#define RT3352_SYSC_REG_SYSCFG0                0x010
  25 +#define RT3352_SYSC_REG_SYSCFG1         0x014
  26 +#define RT3352_SYSC_REG_CLKCFG1         0x030
  27 +#define RT3352_SYSC_REG_RSTCTRL         0x034
  28 +#define RT3352_SYSC_REG_USB_PS          0x05c
  29 +
  30 +#define RT3352_CLKCFG0_XTAL_SEL                BIT(20)
  31 +#define RT3352_CLKCFG1_UPHY0_CLK_EN    BIT(18)
  32 +#define RT3352_CLKCFG1_UPHY1_CLK_EN    BIT(20)
  33 +#define RT3352_RSTCTRL_UHST            BIT(22)
  34 +#define RT3352_RSTCTRL_UDEV            BIT(25)
  35 +#define RT3352_SYSCFG1_USB0_HOST_MODE  BIT(10)
  36 +
  37  #endif
  38 --
  39 1.7.10.4
  40