target/linux/ramips/patches-3.8/0136-NET-MIPS-add-ralink-SoC-ethernet-driver.patch

   1 From 34fc7d26c01ba594be347aefcc31f55b36c06a72 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:20:03 +0200
   4 Subject: [PATCH 136/137] NET: MIPS: add ralink SoC ethernet driver
   5
   6 Add support for Ralink FE and ESW.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
  11  arch/mips/ralink/rt305x.c                          |    1 +
  12  drivers/net/ethernet/Kconfig                       |    1 +
  13  drivers/net/ethernet/Makefile                      |    1 +
  14  drivers/net/ethernet/ramips/Kconfig                |   18 +
  15  drivers/net/ethernet/ramips/Makefile               |    9 +
  16  drivers/net/ethernet/ramips/ramips_debugfs.c       |  127 ++
  17  drivers/net/ethernet/ramips/ramips_esw.c           | 1221 +++++++++++++++++++
  18  drivers/net/ethernet/ramips/ramips_eth.h           |  375 ++++++
  19  drivers/net/ethernet/ramips/ramips_main.c          | 1281 ++++++++++++++++++++
  20  10 files changed, 3061 insertions(+)
  21  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  22  create mode 100644 drivers/net/ethernet/ramips/Kconfig
  23  create mode 100644 drivers/net/ethernet/ramips/Makefile
  24  create mode 100644 drivers/net/ethernet/ramips/ramips_debugfs.c
  25  create mode 100644 drivers/net/ethernet/ramips/ramips_esw.c
  26  create mode 100644 drivers/net/ethernet/ramips/ramips_eth.h
  27  create mode 100644 drivers/net/ethernet/ramips/ramips_main.c
  28
  29 --- /dev/null
  30 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  31 @@ -0,0 +1,27 @@
  32 +/*
  33 + *  Ralink RT305x SoC platform device registration
  34 + *
  35 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  36 + *
  37 + *  This program is free software; you can redistribute it and/or modify it
  38 + *  under the terms of the GNU General Public License version 2 as published
  39 + *  by the Free Software Foundation.
  40 + */
  41 +
  42 +#ifndef _RT305X_ESW_PLATFORM_H
  43 +#define _RT305X_ESW_PLATFORM_H
  44 +
  45 +enum {
  46 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
  47 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
  48 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
  49 +};
  50 +
  51 +struct rt305x_esw_platform_data
  52 +{
  53 +       u8 vlan_config;
  54 +       u32 reg_initval_fct2;
  55 +       u32 reg_initval_fpa2;
  56 +};
  57 +
  58 +#endif /* _RT305X_ESW_PLATFORM_H */
  59 --- a/arch/mips/ralink/rt305x.c
  60 +++ b/arch/mips/ralink/rt305x.c
  61 @@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
  62         }
  63
  64         ralink_clk_add("cpu", cpu_rate);
  65 +       ralink_clk_add("sys", sys_rate);
  66         ralink_clk_add("10000b00.spi", sys_rate);
  67         ralink_clk_add("10000100.timer", wdt_rate);
  68         ralink_clk_add("10000120.watchdog", wdt_rate);
  69 --- a/drivers/net/ethernet/Kconfig
  70 +++ b/drivers/net/ethernet/Kconfig
  71 @@ -136,6 +136,7 @@ source "drivers/net/ethernet/packetengin
  72  source "drivers/net/ethernet/pasemi/Kconfig"
  73  source "drivers/net/ethernet/qlogic/Kconfig"
  74  source "drivers/net/ethernet/racal/Kconfig"
  75 +source "drivers/net/ethernet/ramips/Kconfig"
  76  source "drivers/net/ethernet/realtek/Kconfig"
  77  source "drivers/net/ethernet/renesas/Kconfig"
  78  source "drivers/net/ethernet/rdc/Kconfig"
  79 --- a/drivers/net/ethernet/Makefile
  80 +++ b/drivers/net/ethernet/Makefile
  81 @@ -54,6 +54,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packe
  82  obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
  83  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
  84  obj-$(CONFIG_NET_VENDOR_RACAL) += racal/
  85 +obj-$(CONFIG_NET_RAMIPS) += ramips/
  86  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
  87  obj-$(CONFIG_SH_ETH) += renesas/
  88  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
  89 --- /dev/null
  90 +++ b/drivers/net/ethernet/ramips/Kconfig
  91 @@ -0,0 +1,18 @@
  92 +config NET_RAMIPS
  93 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883 ethernet driver"
  94 +       depends on RALINK
  95 +       select PHYLIB if (SOC_RT288X || SOC_RT3883)
  96 +       select SWCONFIG if SOC_RT305X
  97 +       help
  98 +         This driver supports the etehrnet mac inside the ralink wisocs
  99 +
 100 +if NET_RAMIPS
 101 +
 102 +config NET_RAMIPS_DEBUG
 103 +       bool "Enable debug messages in the Ralink ethernet driver"
 104 +
 105 +config NET_RAMIPS_DEBUG_FS
 106 +       bool "Enable debugfs support for the Ralink ethernet driver"
 107 +       depends on DEBUG_FS
 108 +
 109 +endif
 110 --- /dev/null
 111 +++ b/drivers/net/ethernet/ramips/Makefile
 112 @@ -0,0 +1,9 @@
 113 +#
 114 +# Makefile for the Ramips SoCs built-in ethernet macs
 115 +#
 116 +
 117 +ramips-y       += ramips_main.o
 118 +
 119 +ramips-$(CONFIG_NET_RAMIPS_DEBUG_FS)   += ramips_debugfs.o
 120 +
 121 +obj-$(CONFIG_NET_RAMIPS)       += ramips.o
 122 --- /dev/null
 123 +++ b/drivers/net/ethernet/ramips/ramips_debugfs.c
 124 @@ -0,0 +1,127 @@
 125 +/*
 126 + *  Ralink SoC ethernet driver debugfs code
 127 + *
 128 + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
 129 + *
 130 + *  This program is free software; you can redistribute it and/or modify it
 131 + *  under the terms of the GNU General Public License version 2 as published
 132 + *  by the Free Software Foundation.
 133 + */
 134 +
 135 +#include <linux/debugfs.h>
 136 +#include <linux/module.h>
 137 +#include <linux/phy.h>
 138 +
 139 +#include "ramips_eth.h"
 140 +
 141 +static struct dentry *raeth_debugfs_root;
 142 +
 143 +static int raeth_debugfs_generic_open(struct inode *inode, struct file *file)
 144 +{
 145 +       file->private_data = inode->i_private;
 146 +       return 0;
 147 +}
 148 +
 149 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status)
 150 +{
 151 +       re->debug.int_stats.total += !!status;
 152 +
 153 +       re->debug.int_stats.rx_delayed += !!(status & RAMIPS_RX_DLY_INT);
 154 +       re->debug.int_stats.rx_done0 += !!(status & RAMIPS_RX_DONE_INT0);
 155 +       re->debug.int_stats.rx_coherent += !!(status & RAMIPS_RX_COHERENT);
 156 +
 157 +       re->debug.int_stats.tx_delayed += !!(status & RAMIPS_TX_DLY_INT);
 158 +       re->debug.int_stats.tx_done0 += !!(status & RAMIPS_TX_DONE_INT0);
 159 +       re->debug.int_stats.tx_done1 += !!(status & RAMIPS_TX_DONE_INT1);
 160 +       re->debug.int_stats.tx_done2 += !!(status & RAMIPS_TX_DONE_INT2);
 161 +       re->debug.int_stats.tx_done3 += !!(status & RAMIPS_TX_DONE_INT3);
 162 +       re->debug.int_stats.tx_coherent += !!(status & RAMIPS_TX_COHERENT);
 163 +
 164 +       re->debug.int_stats.pse_fq_empty += !!(status & RAMIPS_PSE_FQ_EMPTY);
 165 +       re->debug.int_stats.pse_p0_fc += !!(status & RAMIPS_PSE_P0_FC);
 166 +       re->debug.int_stats.pse_p1_fc += !!(status & RAMIPS_PSE_P1_FC);
 167 +       re->debug.int_stats.pse_p2_fc += !!(status & RAMIPS_PSE_P2_FC);
 168 +       re->debug.int_stats.pse_buf_drop += !!(status & RAMIPS_PSE_BUF_DROP);
 169 +}
 170 +
 171 +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
 172 +                                  size_t count, loff_t *ppos)
 173 +{
 174 +#define PR_INT_STAT(_label, _field)                                    \
 175 +       len += snprintf(buf + len, sizeof(buf) - len,                   \
 176 +               "%-18s: %10lu\n", _label, re->debug.int_stats._field);
 177 +
 178 +       struct raeth_priv *re = file->private_data;
 179 +       char buf[512];
 180 +       unsigned int len = 0;
 181 +       unsigned long flags;
 182 +
 183 +       spin_lock_irqsave(&re->page_lock, flags);
 184 +
 185 +       PR_INT_STAT("RX Delayed", rx_delayed);
 186 +       PR_INT_STAT("RX Done 0", rx_done0);
 187 +       PR_INT_STAT("RX Coherent", rx_coherent);
 188 +
 189 +       PR_INT_STAT("TX Delayed", tx_delayed);
 190 +       PR_INT_STAT("TX Done 0", tx_done0);
 191 +       PR_INT_STAT("TX Done 1", tx_done1);
 192 +       PR_INT_STAT("TX Done 2", tx_done2);
 193 +       PR_INT_STAT("TX Done 3", tx_done3);
 194 +       PR_INT_STAT("TX Coherent", tx_coherent);
 195 +
 196 +       PR_INT_STAT("PSE FQ empty", pse_fq_empty);
 197 +       PR_INT_STAT("CDMA Flow control", pse_p0_fc);
 198 +       PR_INT_STAT("GDMA1 Flow control", pse_p1_fc);
 199 +       PR_INT_STAT("GDMA2 Flow control", pse_p2_fc);
 200 +       PR_INT_STAT("PSE discard", pse_buf_drop);
 201 +
 202 +       len += snprintf(buf + len, sizeof(buf) - len, "\n");
 203 +       PR_INT_STAT("Total", total);
 204 +
 205 +       spin_unlock_irqrestore(&re->page_lock, flags);
 206 +
 207 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 208 +#undef PR_INT_STAT
 209 +}
 210 +
 211 +static const struct file_operations raeth_fops_int_stats = {
 212 +       .open   = raeth_debugfs_generic_open,
 213 +       .read   = read_file_int_stats,
 214 +       .owner  = THIS_MODULE
 215 +};
 216 +
 217 +void raeth_debugfs_exit(struct raeth_priv *re)
 218 +{
 219 +       debugfs_remove_recursive(re->debug.debugfs_dir);
 220 +}
 221 +
 222 +int raeth_debugfs_init(struct raeth_priv *re)
 223 +{
 224 +       re->debug.debugfs_dir = debugfs_create_dir(re->netdev->name,
 225 +                                                  raeth_debugfs_root);
 226 +       if (!re->debug.debugfs_dir)
 227 +               return -ENOMEM;
 228 +
 229 +       debugfs_create_file("int_stats", S_IRUGO, re->debug.debugfs_dir,
 230 +                           re, &raeth_fops_int_stats);
 231 +
 232 +       return 0;
 233 +}
 234 +
 235 +int raeth_debugfs_root_init(void)
 236 +{
 237 +       if (raeth_debugfs_root)
 238 +               return -EBUSY;
 239 +
 240 +       raeth_debugfs_root = debugfs_create_dir("raeth", NULL);
 241 +       if (!raeth_debugfs_root)
 242 +               return -ENOENT;
 243 +
 244 +       return 0;
 245 +}
 246 +
 247 +void raeth_debugfs_root_exit(void)
 248 +{
 249 +       debugfs_remove(raeth_debugfs_root);
 250 +       raeth_debugfs_root = NULL;
 251 +}
 252 --- /dev/null
 253 +++ b/drivers/net/ethernet/ramips/ramips_esw.c
 254 @@ -0,0 +1,1221 @@
 255 +#include <linux/ioport.h>
 256 +#include <linux/switch.h>
 257 +#include <linux/mii.h>
 258 +
 259 +#include <ralink_regs.h>
 260 +#include <rt305x.h>
 261 +#include <rt305x_esw_platform.h>
 262 +
 263 +/*
 264 + * HW limitations for this switch:
 265 + * - No large frame support (PKT_MAX_LEN at most 1536)
 266 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
 267 + *   though this might be possible using the undocumented PPE.
 268 + */
 269 +
 270 +#define RT305X_ESW_REG_ISR             0x00
 271 +#define RT305X_ESW_REG_IMR             0x04
 272 +#define RT305X_ESW_REG_FCT0            0x08
 273 +#define RT305X_ESW_REG_PFC1            0x14
 274 +#define RT305X_ESW_REG_ATS             0x24
 275 +#define RT305X_ESW_REG_ATS0            0x28
 276 +#define RT305X_ESW_REG_ATS1            0x2c
 277 +#define RT305X_ESW_REG_ATS2            0x30
 278 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 279 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 280 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 281 +#define RT305X_ESW_REG_POA             0x80
 282 +#define RT305X_ESW_REG_FPA             0x84
 283 +#define RT305X_ESW_REG_SOCPC           0x8c
 284 +#define RT305X_ESW_REG_POC0            0x90
 285 +#define RT305X_ESW_REG_POC1            0x94
 286 +#define RT305X_ESW_REG_POC2            0x98
 287 +#define RT305X_ESW_REG_SGC             0x9c
 288 +#define RT305X_ESW_REG_STRT            0xa0
 289 +#define RT305X_ESW_REG_PCR0            0xc0
 290 +#define RT305X_ESW_REG_PCR1            0xc4
 291 +#define RT305X_ESW_REG_FPA2            0xc8
 292 +#define RT305X_ESW_REG_FCT2            0xcc
 293 +#define RT305X_ESW_REG_SGC2            0xe4
 294 +#define RT305X_ESW_REG_P0LED           0xa4
 295 +#define RT305X_ESW_REG_P1LED           0xa8
 296 +#define RT305X_ESW_REG_P2LED           0xac
 297 +#define RT305X_ESW_REG_P3LED           0xb0
 298 +#define RT305X_ESW_REG_P4LED           0xb4
 299 +#define RT305X_ESW_REG_P0PC            0xe8
 300 +#define RT305X_ESW_REG_P1PC            0xec
 301 +#define RT305X_ESW_REG_P2PC            0xf0
 302 +#define RT305X_ESW_REG_P3PC            0xf4
 303 +#define RT305X_ESW_REG_P4PC            0xf8
 304 +#define RT305X_ESW_REG_P5PC            0xfc
 305 +
 306 +#define RT305X_ESW_LED_LINK            0
 307 +#define RT305X_ESW_LED_100M            1
 308 +#define RT305X_ESW_LED_DUPLEX          2
 309 +#define RT305X_ESW_LED_ACTIVITY                3
 310 +#define RT305X_ESW_LED_COLLISION       4
 311 +#define RT305X_ESW_LED_LINKACT         5
 312 +#define RT305X_ESW_LED_DUPLCOLL                6
 313 +#define RT305X_ESW_LED_10MACT          7
 314 +#define RT305X_ESW_LED_100MACT         8
 315 +/* Additional led states not in datasheet: */
 316 +#define RT305X_ESW_LED_BLINK           10
 317 +#define RT305X_ESW_LED_ON              12
 318 +
 319 +#define RT305X_ESW_LINK_S              25
 320 +#define RT305X_ESW_DUPLEX_S            9
 321 +#define RT305X_ESW_SPD_S               0
 322 +
 323 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
 324 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
 325 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
 326 +
 327 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
 328 +
 329 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
 330 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 331 +
 332 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
 333 +#define RT305X_ESW_PVIDC_PVID_S                12
 334 +
 335 +#define RT305X_ESW_VLANI_VID_M         0xfff
 336 +#define RT305X_ESW_VLANI_VID_S         12
 337 +
 338 +#define RT305X_ESW_VMSC_MSC_M          0xff
 339 +#define RT305X_ESW_VMSC_MSC_S          8
 340 +
 341 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
 342 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
 343 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
 344 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
 345 +
 346 +#define RT305X_ESW_POC0_EN_BP_S                0
 347 +#define RT305X_ESW_POC0_EN_FC_S                8
 348 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
 349 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
 350 +#define RT305X_ESW_POC0_DIS_PORT_S     23
 351 +
 352 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
 353 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
 354 +#define RT305X_ESW_POC2_ENAGING_S      8
 355 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
 356 +
 357 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
 358 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
 359 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
 360 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
 361 +
 362 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
 363 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
 364 +#define RT305X_ESW_PFC1_EN_TOS_S       24
 365 +
 366 +#define RT305X_ESW_VLAN_NONE           0xfff
 367 +
 368 +#define RT305X_ESW_POA_LINK_MASK       0x1f
 369 +#define RT305X_ESW_POA_LINK_SHIFT      25
 370 +
 371 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
 372 +#define RT305X_ESW_PORT0               0
 373 +#define RT305X_ESW_PORT1               1
 374 +#define RT305X_ESW_PORT2               2
 375 +#define RT305X_ESW_PORT3               3
 376 +#define RT305X_ESW_PORT4               4
 377 +#define RT305X_ESW_PORT5               5
 378 +#define RT305X_ESW_PORT6               6
 379 +
 380 +#define RT305X_ESW_PORTS_NONE          0
 381 +
 382 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
 383 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
 384 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
 385 +
 386 +#define RT305X_ESW_PORTS_INTERNAL                                      \
 387 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 388 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 389 +                BIT(RT305X_ESW_PORT4))
 390 +
 391 +#define RT305X_ESW_PORTS_NOCPU                                         \
 392 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 393 +
 394 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
 395 +
 396 +#define RT305X_ESW_PORTS_ALL                                           \
 397 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 398 +
 399 +#define RT305X_ESW_NUM_VLANS           16
 400 +#define RT305X_ESW_NUM_VIDS            4096
 401 +#define RT305X_ESW_NUM_PORTS           7
 402 +#define RT305X_ESW_NUM_LANWAN          6
 403 +#define RT305X_ESW_NUM_LEDS            5
 404 +
 405 +enum {
 406 +       /* Global attributes. */
 407 +       RT305X_ESW_ATTR_ENABLE_VLAN,
 408 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 409 +       /* Port attributes. */
 410 +       RT305X_ESW_ATTR_PORT_DISABLE,
 411 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
 412 +       RT305X_ESW_ATTR_PORT_UNTAG,
 413 +       RT305X_ESW_ATTR_PORT_LED,
 414 +       RT305X_ESW_ATTR_PORT_LAN,
 415 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
 416 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
 417 +};
 418 +
 419 +struct rt305x_esw_port {
 420 +       bool    disable;
 421 +       bool    doubletag;
 422 +       bool    untag;
 423 +       u8      led;
 424 +       u16     pvid;
 425 +};
 426 +
 427 +struct rt305x_esw_vlan {
 428 +       u8      ports;
 429 +       u16     vid;
 430 +};
 431 +
 432 +struct rt305x_esw {
 433 +       struct device           *dev;
 434 +       void __iomem            *base;
 435 +       int                     irq;
 436 +       const struct rt305x_esw_platform_data *pdata;
 437 +       /* Protects against concurrent register rmw operations. */
 438 +       spinlock_t              reg_rw_lock;
 439 +
 440 +       unsigned char           port_map;
 441 +       unsigned int            reg_initval_fct2;
 442 +       unsigned int            reg_initval_fpa2;
 443 +
 444 +
 445 +       struct switch_dev       swdev;
 446 +       bool                    global_vlan_enable;
 447 +       bool                    alt_vlan_disable;
 448 +       struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 449 +       struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS];
 450 +
 451 +};
 452 +
 453 +static inline void
 454 +rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
 455 +{
 456 +       __raw_writel(val, esw->base + reg);
 457 +}
 458 +
 459 +static inline u32
 460 +rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
 461 +{
 462 +       return __raw_readl(esw->base + reg);
 463 +}
 464 +
 465 +static inline void
 466 +rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 467 +                  unsigned long val)
 468 +{
 469 +       unsigned long t;
 470 +
 471 +       t = __raw_readl(esw->base + reg) & ~mask;
 472 +       __raw_writel(t | val, esw->base + reg);
 473 +}
 474 +
 475 +static void
 476 +rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 477 +              unsigned long val)
 478 +{
 479 +       unsigned long flags;
 480 +
 481 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
 482 +       rt305x_esw_rmw_raw(esw, reg, mask, val);
 483 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 484 +}
 485 +
 486 +static u32
 487 +rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 488 +                u32 write_data)
 489 +{
 490 +       unsigned long t_start = jiffies;
 491 +       int ret = 0;
 492 +
 493 +       while (1) {
 494 +               if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 495 +                     RT305X_ESW_PCR1_WT_DONE))
 496 +                       break;
 497 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 498 +                       ret = 1;
 499 +                       goto out;
 500 +               }
 501 +       }
 502 +
 503 +       write_data &= 0xffff;
 504 +       rt305x_esw_wr(esw,
 505 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 506 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 507 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 508 +                     RT305X_ESW_REG_PCR0);
 509 +
 510 +       t_start = jiffies;
 511 +       while (1) {
 512 +               if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 513 +                   RT305X_ESW_PCR1_WT_DONE)
 514 +                       break;
 515 +
 516 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 517 +                       ret = 1;
 518 +                       break;
 519 +               }
 520 +       }
 521 +out:
 522 +       if (ret)
 523 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 524 +       return ret;
 525 +}
 526 +
 527 +static unsigned
 528 +rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 529 +{
 530 +       unsigned s;
 531 +       unsigned val;
 532 +
 533 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 534 +       val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 535 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 536 +
 537 +       return val;
 538 +}
 539 +
 540 +static void
 541 +rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 542 +{
 543 +       unsigned s;
 544 +
 545 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 546 +       rt305x_esw_rmw(esw,
 547 +                      RT305X_ESW_REG_VLANI(vlan / 2),
 548 +                      RT305X_ESW_VLANI_VID_M << s,
 549 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
 550 +}
 551 +
 552 +static unsigned
 553 +rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 554 +{
 555 +       unsigned s, val;
 556 +
 557 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 558 +       val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2));
 559 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 560 +}
 561 +
 562 +static void
 563 +rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 564 +{
 565 +       unsigned s;
 566 +
 567 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 568 +       rt305x_esw_rmw(esw,
 569 +                      RT305X_ESW_REG_PVIDC(port / 2),
 570 +                      RT305X_ESW_PVIDC_PVID_M << s,
 571 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 572 +}
 573 +
 574 +static unsigned
 575 +rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 576 +{
 577 +       unsigned s, val;
 578 +
 579 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 580 +       val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 581 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 582 +
 583 +       return val;
 584 +}
 585 +
 586 +static void
 587 +rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 588 +{
 589 +       unsigned s;
 590 +
 591 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 592 +       rt305x_esw_rmw(esw,
 593 +                      RT305X_ESW_REG_VMSC(vlan / 4),
 594 +                      RT305X_ESW_VMSC_MSC_M << s,
 595 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
 596 +}
 597 +
 598 +static unsigned
 599 +rt305x_esw_get_port_disable(struct rt305x_esw *esw)
 600 +{
 601 +       unsigned reg;
 602 +       reg = rt305x_esw_rr(esw, RT305X_ESW_REG_POC0);
 603 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
 604 +              RT305X_ESW_POC0_DIS_PORT_M;
 605 +}
 606 +
 607 +static void
 608 +rt305x_esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
 609 +{
 610 +       unsigned old_mask;
 611 +       unsigned enable_mask;
 612 +       unsigned changed;
 613 +       int i;
 614 +
 615 +       old_mask = rt305x_esw_get_port_disable(esw);
 616 +       changed = old_mask ^ disable_mask;
 617 +       enable_mask = old_mask & disable_mask;
 618 +
 619 +       /* enable before writing to MII */
 620 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
 621 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 622 +                       RT305X_ESW_POC0_DIS_PORT_S),
 623 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 624 +
 625 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
 626 +               if (!(changed & (1 << i)))
 627 +                       continue;
 628 +               if (disable_mask & (1 << i)) {
 629 +                       /* disable */
 630 +                       rt305x_mii_write(esw, i, MII_BMCR,
 631 +                                        BMCR_PDOWN);
 632 +               } else {
 633 +                       /* enable */
 634 +                       rt305x_mii_write(esw, i, MII_BMCR,
 635 +                                        BMCR_FULLDPLX |
 636 +                                        BMCR_ANENABLE |
 637 +                                        BMCR_ANRESTART |
 638 +                                        BMCR_SPEED100);
 639 +               }
 640 +       }
 641 +
 642 +       /* disable after writing to MII */
 643 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
 644 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 645 +                       RT305X_ESW_POC0_DIS_PORT_S),
 646 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 647 +}
 648 +
 649 +static int
 650 +rt305x_esw_apply_config(struct switch_dev *dev);
 651 +
 652 +static void
 653 +rt305x_esw_hw_init(struct rt305x_esw *esw)
 654 +{
 655 +       int i;
 656 +       u8 port_disable = 0;
 657 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 658 +
 659 +       /* vodoo from original driver */
 660 +       rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 661 +       rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 662 +       /* Port priority 1 for all ports, vlan enabled. */
 663 +       rt305x_esw_wr(esw, 0x00005555 |
 664 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 665 +                     RT305X_ESW_REG_PFC1);
 666 +
 667 +       /* Enable Back Pressure, and Flow Control */
 668 +       rt305x_esw_wr(esw,
 669 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 670 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 671 +                     RT305X_ESW_REG_POC0);
 672 +
 673 +       /* Enable Aging, and VLAN TAG removal */
 674 +       rt305x_esw_wr(esw,
 675 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 676 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 677 +                     RT305X_ESW_REG_POC2);
 678 +
 679 +       if (esw->reg_initval_fct2)
 680 +               rt305x_esw_wr(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 681 +       else
 682 +               rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 683 +
 684 +       /*
 685 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
 686 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
 687 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
 688 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 689 +        * ports.
 690 +        */
 691 +       rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 692 +
 693 +       /* Setup SoC Port control register */
 694 +       rt305x_esw_wr(esw,
 695 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
 696 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 697 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 698 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 699 +                     RT305X_ESW_REG_SOCPC);
 700 +
 701 +       if (esw->reg_initval_fpa2)
 702 +               rt305x_esw_wr(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 703 +       else
 704 +               rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 705 +       rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
 706 +
 707 +       /* Force Link/Activity on ports */
 708 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 709 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 710 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 711 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 712 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 713 +
 714 +       /* Copy disabled port configuration from bootloader setup */
 715 +       port_disable = rt305x_esw_get_port_disable(esw);
 716 +       for (i = 0; i < 6; i++)
 717 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 718 +
 719 +       rt305x_mii_write(esw, 0, 31, 0x8000);
 720 +       for (i = 0; i < 5; i++) {
 721 +               if (esw->ports[i].disable) {
 722 +                       rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 723 +               } else {
 724 +                       rt305x_mii_write(esw, i, MII_BMCR,
 725 +                                        BMCR_FULLDPLX |
 726 +                                        BMCR_ANENABLE |
 727 +                                        BMCR_SPEED100);
 728 +               }
 729 +               /* TX10 waveform coefficient */
 730 +               rt305x_mii_write(esw, i, 26, 0x1601);
 731 +               /* TX100/TX10 AD/DA current bias */
 732 +               rt305x_mii_write(esw, i, 29, 0x7058);
 733 +               /* TX100 slew rate control */
 734 +               rt305x_mii_write(esw, i, 30, 0x0018);
 735 +       }
 736 +
 737 +       /* PHY IOT */
 738 +       /* select global register */
 739 +       rt305x_mii_write(esw, 0, 31, 0x0);
 740 +       /* tune TP_IDL tail and head waveform */
 741 +       rt305x_mii_write(esw, 0, 22, 0x052f);
 742 +       /* set TX10 signal amplitude threshold to minimum */
 743 +       rt305x_mii_write(esw, 0, 17, 0x0fe0);
 744 +       /* set squelch amplitude to higher threshold */
 745 +       rt305x_mii_write(esw, 0, 18, 0x40ba);
 746 +       /* longer TP_IDL tail length */
 747 +       rt305x_mii_write(esw, 0, 14, 0x65);
 748 +       /* select local register */
 749 +       rt305x_mii_write(esw, 0, 31, 0x8000);
 750 +
 751 +       if (esw->port_map)
 752 +               port_map = esw->port_map;
 753 +       else
 754 +               port_map = RT305X_ESW_PMAP_LLLLLL;
 755 +
 756 +       /*
 757 +        * Unused HW feature, but still nice to be consistent here...
 758 +        * This is also exported to userspace ('lan' attribute) so it's
 759 +        * conveniently usable to decide which ports go into the wan vlan by
 760 +        * default.
 761 +        */
 762 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
 763 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 764 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 765 +
 766 +       /* make the switch leds blink */
 767 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
 768 +               esw->ports[i].led = 0x05;
 769 +
 770 +       /* Apply the empty config. */
 771 +       rt305x_esw_apply_config(&esw->swdev);
 772 +}
 773 +
 774 +static irqreturn_t
 775 +rt305x_esw_interrupt(int irq, void *_esw)
 776 +{
 777 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
 778 +       u32 status;
 779 +
 780 +       status = rt305x_esw_rr(esw, RT305X_ESW_REG_ISR);
 781 +       if (status & RT305X_ESW_PORT_ST_CHG) {
 782 +               u32 link = rt305x_esw_rr(esw, RT305X_ESW_REG_POA);
 783 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
 784 +               link &= RT305X_ESW_POA_LINK_MASK;
 785 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
 786 +       }
 787 +       rt305x_esw_wr(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
 788 +
 789 +       return IRQ_HANDLED;
 790 +}
 791 +
 792 +static void
 793 +rt305x_esw_request_irq(struct rt305x_esw *esw)
 794 +{
 795 +       /* Only unmask the port change interrupt */
 796 +       rt305x_esw_wr(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
 797 +
 798 +       /* request the irq handler */
 799 +       request_irq(esw->irq, rt305x_esw_interrupt, 0, "esw", esw);
 800 +}
 801 +
 802 +static int
 803 +rt305x_esw_apply_config(struct switch_dev *dev)
 804 +{
 805 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 806 +       int i;
 807 +       u8 disable = 0;
 808 +       u8 doubletag = 0;
 809 +       u8 en_vlan = 0;
 810 +       u8 untag = 0;
 811 +
 812 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 813 +               u32 vid, vmsc;
 814 +               if (esw->global_vlan_enable) {
 815 +                       vid = esw->vlans[i].vid;
 816 +                       vmsc = esw->vlans[i].ports;
 817 +               } else {
 818 +                       vid = RT305X_ESW_VLAN_NONE;
 819 +                       vmsc = RT305X_ESW_PORTS_NONE;
 820 +               }
 821 +               rt305x_esw_set_vlan_id(esw, i, vid);
 822 +               rt305x_esw_set_vmsc(esw, i, vmsc);
 823 +       }
 824 +
 825 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 826 +               u32 pvid;
 827 +               disable |= esw->ports[i].disable << i;
 828 +               if (esw->global_vlan_enable) {
 829 +                       doubletag |= esw->ports[i].doubletag << i;
 830 +                       en_vlan   |= 1                       << i;
 831 +                       untag     |= esw->ports[i].untag     << i;
 832 +                       pvid       = esw->ports[i].pvid;
 833 +               } else {
 834 +                       int x = esw->alt_vlan_disable ? 0 : 1;
 835 +                       doubletag |= x << i;
 836 +                       en_vlan   |= x << i;
 837 +                       untag     |= x << i;
 838 +                       pvid       = 0;
 839 +               }
 840 +               rt305x_esw_set_pvid(esw, i, pvid);
 841 +               if (i < RT305X_ESW_NUM_LEDS)
 842 +                       rt305x_esw_wr(esw, esw->ports[i].led,
 843 +                                     RT305X_ESW_REG_P0LED + 4*i);
 844 +       }
 845 +
 846 +       rt305x_esw_set_port_disable(esw, disable);
 847 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
 848 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 849 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
 850 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 851 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
 852 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 853 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 854 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2,
 855 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 856 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
 857 +
 858 +       if (!esw->global_vlan_enable) {
 859 +               /*
 860 +                * Still need to put all ports into vlan 0 or they'll be
 861 +                * isolated.
 862 +                * NOTE: vlan 0 is special, no vlan tag is prepended
 863 +                */
 864 +               rt305x_esw_set_vlan_id(esw, 0, 0);
 865 +               rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 866 +       }
 867 +
 868 +       return 0;
 869 +}
 870 +
 871 +static int
 872 +rt305x_esw_reset_switch(struct switch_dev *dev)
 873 +{
 874 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 875 +       esw->global_vlan_enable = 0;
 876 +       memset(esw->ports, 0, sizeof(esw->ports));
 877 +       memset(esw->vlans, 0, sizeof(esw->vlans));
 878 +       rt305x_esw_hw_init(esw);
 879 +
 880 +       return 0;
 881 +}
 882 +
 883 +static int
 884 +rt305x_esw_get_vlan_enable(struct switch_dev *dev,
 885 +                          const struct switch_attr *attr,
 886 +                          struct switch_val *val)
 887 +{
 888 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 889 +
 890 +       val->value.i = esw->global_vlan_enable;
 891 +
 892 +       return 0;
 893 +}
 894 +
 895 +static int
 896 +rt305x_esw_set_vlan_enable(struct switch_dev *dev,
 897 +                          const struct switch_attr *attr,
 898 +                          struct switch_val *val)
 899 +{
 900 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 901 +
 902 +       esw->global_vlan_enable = val->value.i != 0;
 903 +
 904 +       return 0;
 905 +}
 906 +
 907 +static int
 908 +rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev,
 909 +                               const struct switch_attr *attr,
 910 +                               struct switch_val *val)
 911 +{
 912 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 913 +
 914 +       val->value.i = esw->alt_vlan_disable;
 915 +
 916 +       return 0;
 917 +}
 918 +
 919 +static int
 920 +rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev,
 921 +                               const struct switch_attr *attr,
 922 +                               struct switch_val *val)
 923 +{
 924 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 925 +
 926 +       esw->alt_vlan_disable = val->value.i != 0;
 927 +
 928 +       return 0;
 929 +}
 930 +
 931 +static int
 932 +rt305x_esw_get_port_link(struct switch_dev *dev,
 933 +                        int port,
 934 +                        struct switch_port_link *link)
 935 +{
 936 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 937 +       u32 speed, poa;
 938 +
 939 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
 940 +               return -EINVAL;
 941 +
 942 +       poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port;
 943 +
 944 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
 945 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
 946 +       if (port < RT305X_ESW_NUM_LEDS) {
 947 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
 948 +       } else {
 949 +               if (port == RT305X_ESW_NUM_PORTS - 1)
 950 +                       poa >>= 1;
 951 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
 952 +       }
 953 +       switch (speed) {
 954 +       case 0:
 955 +               link->speed = SWITCH_PORT_SPEED_10;
 956 +               break;
 957 +       case 1:
 958 +               link->speed = SWITCH_PORT_SPEED_100;
 959 +               break;
 960 +       case 2:
 961 +       case 3: /* forced gige speed can be 2 or 3 */
 962 +               link->speed = SWITCH_PORT_SPEED_1000;
 963 +               break;
 964 +       default:
 965 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 966 +               break;
 967 +       }
 968 +
 969 +       return 0;
 970 +}
 971 +
 972 +static int
 973 +rt305x_esw_get_port_bool(struct switch_dev *dev,
 974 +                        const struct switch_attr *attr,
 975 +                        struct switch_val *val)
 976 +{
 977 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 978 +       int idx = val->port_vlan;
 979 +       u32 x, reg, shift;
 980 +
 981 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
 982 +               return -EINVAL;
 983 +
 984 +       switch (attr->id) {
 985 +       case RT305X_ESW_ATTR_PORT_DISABLE:
 986 +               reg = RT305X_ESW_REG_POC0;
 987 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
 988 +               break;
 989 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
 990 +               reg = RT305X_ESW_REG_SGC2;
 991 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
 992 +               break;
 993 +       case RT305X_ESW_ATTR_PORT_UNTAG:
 994 +               reg = RT305X_ESW_REG_POC2;
 995 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
 996 +               break;
 997 +       case RT305X_ESW_ATTR_PORT_LAN:
 998 +               reg = RT305X_ESW_REG_SGC2;
 999 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1000 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1001 +                       return -EINVAL;
1002 +               break;
1003 +       default:
1004 +               return -EINVAL;
1005 +       }
1006 +
1007 +       x = rt305x_esw_rr(esw, reg);
1008 +       val->value.i = (x >> (idx + shift)) & 1;
1009 +
1010 +       return 0;
1011 +}
1012 +
1013 +static int
1014 +rt305x_esw_set_port_bool(struct switch_dev *dev,
1015 +                        const struct switch_attr *attr,
1016 +                        struct switch_val *val)
1017 +{
1018 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1019 +       int idx = val->port_vlan;
1020 +
1021 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1022 +           val->value.i < 0 || val->value.i > 1)
1023 +               return -EINVAL;
1024 +
1025 +       switch (attr->id) {
1026 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1027 +               esw->ports[idx].disable = val->value.i;
1028 +               break;
1029 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1030 +               esw->ports[idx].doubletag = val->value.i;
1031 +               break;
1032 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1033 +               esw->ports[idx].untag = val->value.i;
1034 +               break;
1035 +       default:
1036 +               return -EINVAL;
1037 +       }
1038 +
1039 +       return 0;
1040 +}
1041 +
1042 +static int
1043 +rt305x_esw_get_port_recv_badgood(struct switch_dev *dev,
1044 +                                const struct switch_attr *attr,
1045 +                                struct switch_val *val)
1046 +{
1047 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1048 +       int idx = val->port_vlan;
1049 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1050 +       u32 reg;
1051 +
1052 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1053 +               return -EINVAL;
1054 +
1055 +       reg = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx);
1056 +       val->value.i = (reg >> shift) & 0xffff;
1057 +
1058 +       return 0;
1059 +}
1060 +
1061 +static int
1062 +rt305x_esw_get_port_led(struct switch_dev *dev,
1063 +                       const struct switch_attr *attr,
1064 +                       struct switch_val *val)
1065 +{
1066 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1067 +       int idx = val->port_vlan;
1068 +
1069 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1070 +           idx >= RT305X_ESW_NUM_LEDS)
1071 +               return -EINVAL;
1072 +
1073 +       val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx);
1074 +
1075 +       return 0;
1076 +}
1077 +
1078 +static int
1079 +rt305x_esw_set_port_led(struct switch_dev *dev,
1080 +                       const struct switch_attr *attr,
1081 +                       struct switch_val *val)
1082 +{
1083 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1084 +       int idx = val->port_vlan;
1085 +
1086 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1087 +               return -EINVAL;
1088 +
1089 +       esw->ports[idx].led = val->value.i;
1090 +
1091 +       return 0;
1092 +}
1093 +
1094 +static int
1095 +rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1096 +{
1097 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1098 +
1099 +       if (port >= RT305X_ESW_NUM_PORTS)
1100 +               return -EINVAL;
1101 +
1102 +       *val = rt305x_esw_get_pvid(esw, port);
1103 +
1104 +       return 0;
1105 +}
1106 +
1107 +static int
1108 +rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1109 +{
1110 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1111 +
1112 +       if (port >= RT305X_ESW_NUM_PORTS)
1113 +               return -EINVAL;
1114 +
1115 +       esw->ports[port].pvid = val;
1116 +
1117 +       return 0;
1118 +}
1119 +
1120 +static int
1121 +rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1122 +{
1123 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1124 +       u32 vmsc, poc2;
1125 +       int vlan_idx = -1;
1126 +       int i;
1127 +
1128 +       val->len = 0;
1129 +
1130 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1131 +               return -EINVAL;
1132 +
1133 +       /* valid vlan? */
1134 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1135 +               if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan &&
1136 +                   rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1137 +                       vlan_idx = i;
1138 +                       break;
1139 +               }
1140 +       }
1141 +
1142 +       if (vlan_idx == -1)
1143 +               return -EINVAL;
1144 +
1145 +       vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
1146 +       poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2);
1147 +
1148 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1149 +               struct switch_port *p;
1150 +               int port_mask = 1 << i;
1151 +
1152 +               if (!(vmsc & port_mask))
1153 +                       continue;
1154 +
1155 +               p = &val->value.ports[val->len++];
1156 +               p->id = i;
1157 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1158 +                       p->flags = 0;
1159 +               else
1160 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1161 +       }
1162 +
1163 +       return 0;
1164 +}
1165 +
1166 +static int
1167 +rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1168 +{
1169 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1170 +       int ports;
1171 +       int vlan_idx = -1;
1172 +       int i;
1173 +
1174 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1175 +           val->len > RT305X_ESW_NUM_PORTS)
1176 +               return -EINVAL;
1177 +
1178 +       /* one of the already defined vlans? */
1179 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1180 +               if (esw->vlans[i].vid == val->port_vlan &&
1181 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1182 +                       vlan_idx = i;
1183 +                       break;
1184 +               }
1185 +       }
1186 +
1187 +       /* select a free slot */
1188 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1189 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1190 +                       vlan_idx = i;
1191 +       }
1192 +
1193 +       /* bail if all slots are in use */
1194 +       if (vlan_idx == -1)
1195 +               return -EINVAL;
1196 +
1197 +       ports = RT305X_ESW_PORTS_NONE;
1198 +       for (i = 0; i < val->len; i++) {
1199 +               struct switch_port *p = &val->value.ports[i];
1200 +               int port_mask = 1 << p->id;
1201 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1202 +
1203 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1204 +                       return -EINVAL;
1205 +
1206 +               ports |= port_mask;
1207 +               esw->ports[p->id].untag = untagged;
1208 +       }
1209 +       esw->vlans[vlan_idx].ports = ports;
1210 +       if (ports == RT305X_ESW_PORTS_NONE)
1211 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1212 +       else
1213 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1214 +
1215 +       return 0;
1216 +}
1217 +
1218 +static const struct switch_attr rt305x_esw_global[] = {
1219 +       {
1220 +               .type = SWITCH_TYPE_INT,
1221 +               .name = "enable_vlan",
1222 +               .description = "VLAN mode (1:enabled)",
1223 +               .max = 1,
1224 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1225 +               .get = rt305x_esw_get_vlan_enable,
1226 +               .set = rt305x_esw_set_vlan_enable,
1227 +       },
1228 +       {
1229 +               .type = SWITCH_TYPE_INT,
1230 +               .name = "alternate_vlan_disable",
1231 +               .description = "Use en_vlan instead of doubletag to disable"
1232 +                               " VLAN mode",
1233 +               .max = 1,
1234 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1235 +               .get = rt305x_esw_get_alt_vlan_disable,
1236 +               .set = rt305x_esw_set_alt_vlan_disable,
1237 +       },
1238 +};
1239 +
1240 +static const struct switch_attr rt305x_esw_port[] = {
1241 +       {
1242 +               .type = SWITCH_TYPE_INT,
1243 +               .name = "disable",
1244 +               .description = "Port state (1:disabled)",
1245 +               .max = 1,
1246 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1247 +               .get = rt305x_esw_get_port_bool,
1248 +               .set = rt305x_esw_set_port_bool,
1249 +       },
1250 +       {
1251 +               .type = SWITCH_TYPE_INT,
1252 +               .name = "doubletag",
1253 +               .description = "Double tagging for incoming vlan packets "
1254 +                               "(1:enabled)",
1255 +               .max = 1,
1256 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1257 +               .get = rt305x_esw_get_port_bool,
1258 +               .set = rt305x_esw_set_port_bool,
1259 +       },
1260 +       {
1261 +               .type = SWITCH_TYPE_INT,
1262 +               .name = "untag",
1263 +               .description = "Untag (1:strip outgoing vlan tag)",
1264 +               .max = 1,
1265 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1266 +               .get = rt305x_esw_get_port_bool,
1267 +               .set = rt305x_esw_set_port_bool,
1268 +       },
1269 +       {
1270 +               .type = SWITCH_TYPE_INT,
1271 +               .name = "led",
1272 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1273 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1274 +                               " 8:100mact, 10:blink, 12:on)",
1275 +               .max = 15,
1276 +               .id = RT305X_ESW_ATTR_PORT_LED,
1277 +               .get = rt305x_esw_get_port_led,
1278 +               .set = rt305x_esw_set_port_led,
1279 +       },
1280 +       {
1281 +               .type = SWITCH_TYPE_INT,
1282 +               .name = "lan",
1283 +               .description = "HW port group (0:wan, 1:lan)",
1284 +               .max = 1,
1285 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1286 +               .get = rt305x_esw_get_port_bool,
1287 +       },
1288 +       {
1289 +               .type = SWITCH_TYPE_INT,
1290 +               .name = "recv_bad",
1291 +               .description = "Receive bad packet counter",
1292 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1293 +               .get = rt305x_esw_get_port_recv_badgood,
1294 +       },
1295 +       {
1296 +               .type = SWITCH_TYPE_INT,
1297 +               .name = "recv_good",
1298 +               .description = "Receive good packet counter",
1299 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1300 +               .get = rt305x_esw_get_port_recv_badgood,
1301 +       },
1302 +};
1303 +
1304 +static const struct switch_attr rt305x_esw_vlan[] = {
1305 +};
1306 +
1307 +static const struct switch_dev_ops rt305x_esw_ops = {
1308 +       .attr_global = {
1309 +               .attr = rt305x_esw_global,
1310 +               .n_attr = ARRAY_SIZE(rt305x_esw_global),
1311 +       },
1312 +       .attr_port = {
1313 +               .attr = rt305x_esw_port,
1314 +               .n_attr = ARRAY_SIZE(rt305x_esw_port),
1315 +       },
1316 +       .attr_vlan = {
1317 +               .attr = rt305x_esw_vlan,
1318 +               .n_attr = ARRAY_SIZE(rt305x_esw_vlan),
1319 +       },
1320 +       .get_vlan_ports = rt305x_esw_get_vlan_ports,
1321 +       .set_vlan_ports = rt305x_esw_set_vlan_ports,
1322 +       .get_port_pvid = rt305x_esw_get_port_pvid,
1323 +       .set_port_pvid = rt305x_esw_set_port_pvid,
1324 +       .get_port_link = rt305x_esw_get_port_link,
1325 +       .apply_config = rt305x_esw_apply_config,
1326 +       .reset_switch = rt305x_esw_reset_switch,
1327 +};
1328 +
1329 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1330 +       /* All ports are LAN ports. */
1331 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1332 +       .reg_initval_fct2       = 0x00d6500c,
1333 +       /*
1334 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1335 +        * turbo mii off, rgmi 3.3v off
1336 +        * port5: disabled
1337 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1338 +        */
1339 +       .reg_initval_fpa2       = 0x3f502b28,
1340 +};
1341 +
1342 +static const struct of_device_id ralink_esw_match[] = {
1343 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1344 +       {},
1345 +};
1346 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1347 +
1348 +static int
1349 +rt305x_esw_probe(struct platform_device *pdev)
1350 +{
1351 +       struct device_node *np = pdev->dev.of_node;
1352 +       const struct rt305x_esw_platform_data *pdata;
1353 +       const __be32 *port_map, *reg_init;
1354 +       struct rt305x_esw *esw;
1355 +       struct switch_dev *swdev;
1356 +       struct resource *res, *irq;
1357 +       int err;
1358 +
1359 +       pdata = pdev->dev.platform_data;
1360 +       if (!pdata) {
1361 +               const struct of_device_id *match;
1362 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1363 +               if (match)
1364 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1365 +       }
1366 +       if (!pdata)
1367 +               return -EINVAL;
1368 +
1369 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370 +       if (!res) {
1371 +               dev_err(&pdev->dev, "no memory resource found\n");
1372 +               return -ENOMEM;
1373 +       }
1374 +
1375 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1376 +       if (!irq) {
1377 +               dev_err(&pdev->dev, "no irq resource found\n");
1378 +               return -ENOMEM;
1379 +       }
1380 +
1381 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1382 +       if (!esw) {
1383 +               dev_err(&pdev->dev, "no memory for private data\n");
1384 +               return -ENOMEM;
1385 +       }
1386 +
1387 +       esw->dev = &pdev->dev;
1388 +       esw->irq = irq->start;
1389 +       esw->base = ioremap(res->start, resource_size(res));
1390 +       if (!esw->base) {
1391 +               dev_err(&pdev->dev, "ioremap failed\n");
1392 +               err = -ENOMEM;
1393 +               goto free_esw;
1394 +       }
1395 +
1396 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1397 +        if (port_map)
1398 +               esw->port_map = be32_to_cpu(*port_map);
1399 +
1400 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1401 +        if (reg_init)
1402 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1403 +
1404 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1405 +        if (reg_init)
1406 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1407 +
1408 +       swdev = &esw->swdev;
1409 +       swdev->of_node = pdev->dev.of_node;
1410 +       swdev->name = "rt305x-esw";
1411 +       swdev->alias = "rt305x";
1412 +       swdev->cpu_port = RT305X_ESW_PORT6;
1413 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1414 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1415 +       swdev->ops = &rt305x_esw_ops;
1416 +
1417 +       err = register_switch(swdev, NULL);
1418 +       if (err < 0) {
1419 +               dev_err(&pdev->dev, "register_switch failed\n");
1420 +               goto unmap_base;
1421 +       }
1422 +
1423 +       platform_set_drvdata(pdev, esw);
1424 +
1425 +       esw->pdata = pdata;
1426 +       spin_lock_init(&esw->reg_rw_lock);
1427 +       rt305x_esw_hw_init(esw);
1428 +       rt305x_esw_request_irq(esw);
1429 +
1430 +       return 0;
1431 +
1432 +unmap_base:
1433 +       iounmap(esw->base);
1434 +free_esw:
1435 +       kfree(esw);
1436 +       return err;
1437 +}
1438 +
1439 +static int
1440 +rt305x_esw_remove(struct platform_device *pdev)
1441 +{
1442 +       struct rt305x_esw *esw;
1443 +
1444 +       esw = platform_get_drvdata(pdev);
1445 +       if (esw) {
1446 +               unregister_switch(&esw->swdev);
1447 +               platform_set_drvdata(pdev, NULL);
1448 +               iounmap(esw->base);
1449 +               kfree(esw);
1450 +       }
1451 +
1452 +       return 0;
1453 +}
1454 +
1455 +static struct platform_driver rt305x_esw_driver = {
1456 +       .probe = rt305x_esw_probe,
1457 +       .remove = rt305x_esw_remove,
1458 +       .driver = {
1459 +               .name = "rt305x-esw",
1460 +               .owner = THIS_MODULE,
1461 +               .of_match_table = ralink_esw_match,
1462 +       },
1463 +};
1464 +
1465 +static int __init
1466 +rt305x_esw_init(void)
1467 +{
1468 +       return platform_driver_register(&rt305x_esw_driver);
1469 +}
1470 +
1471 +static void
1472 +rt305x_esw_exit(void)
1473 +{
1474 +       platform_driver_unregister(&rt305x_esw_driver);
1475 +}
1476 --- /dev/null
1477 +++ b/drivers/net/ethernet/ramips/ramips_eth.h
1478 @@ -0,0 +1,375 @@
1479 +/*
1480 + *   This program is free software; you can redistribute it and/or modify
1481 + *   it under the terms of the GNU General Public License as published by
1482 + *   the Free Software Foundation; version 2 of the License
1483 + *
1484 + *   This program is distributed in the hope that it will be useful,
1485 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1486 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1487 + *   GNU General Public License for more details.
1488 + *
1489 + *   You should have received a copy of the GNU General Public License
1490 + *   along with this program; if not, write to the Free Software
1491 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1492 + *
1493 + *   based on Ralink SDK3.3
1494 + *   Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1495 + */
1496 +
1497 +#ifndef RAMIPS_ETH_H
1498 +#define RAMIPS_ETH_H
1499 +
1500 +#include <linux/mii.h>
1501 +#include <linux/interrupt.h>
1502 +#include <linux/netdevice.h>
1503 +#include <linux/dma-mapping.h>
1504 +
1505 +#define NUM_RX_DESC     256
1506 +#define NUM_TX_DESC     256
1507 +
1508 +#define RAMIPS_DELAY_EN_INT            0x80
1509 +#define RAMIPS_DELAY_MAX_INT           0x04
1510 +#define RAMIPS_DELAY_MAX_TOUT          0x04
1511 +#define RAMIPS_DELAY_CHAN              (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT)
1512 +#define RAMIPS_DELAY_INIT              ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN)
1513 +#define RAMIPS_PSE_FQFC_CFG_INIT       0x80504000
1514 +
1515 +/* interrupt bits */
1516 +#define RAMIPS_CNT_PPE_AF              BIT(31)
1517 +#define RAMIPS_CNT_GDM_AF              BIT(29)
1518 +#define RAMIPS_PSE_P2_FC               BIT(26)
1519 +#define RAMIPS_PSE_BUF_DROP            BIT(24)
1520 +#define RAMIPS_GDM_OTHER_DROP          BIT(23)
1521 +#define RAMIPS_PSE_P1_FC               BIT(22)
1522 +#define RAMIPS_PSE_P0_FC               BIT(21)
1523 +#define RAMIPS_PSE_FQ_EMPTY            BIT(20)
1524 +#define RAMIPS_GE1_STA_CHG             BIT(18)
1525 +#define RAMIPS_TX_COHERENT             BIT(17)
1526 +#define RAMIPS_RX_COHERENT             BIT(16)
1527 +#define RAMIPS_TX_DONE_INT3            BIT(11)
1528 +#define RAMIPS_TX_DONE_INT2            BIT(10)
1529 +#define RAMIPS_TX_DONE_INT1            BIT(9)
1530 +#define RAMIPS_TX_DONE_INT0            BIT(8)
1531 +#define RAMIPS_RX_DONE_INT0            BIT(2)
1532 +#define RAMIPS_TX_DLY_INT              BIT(1)
1533 +#define RAMIPS_RX_DLY_INT              BIT(0)
1534 +
1535 +#define RT5350_RX_DLY_INT              BIT(30)
1536 +#define RT5350_TX_DLY_INT              BIT(28)
1537 +
1538 +/* registers */
1539 +#define RAMIPS_FE_OFFSET               0x0000
1540 +#define RAMIPS_GDMA_OFFSET             0x0020
1541 +#define RAMIPS_PSE_OFFSET              0x0040
1542 +#define RAMIPS_GDMA2_OFFSET            0x0060
1543 +#define RAMIPS_CDMA_OFFSET             0x0080
1544 +#define RAMIPS_PDMA_OFFSET             0x0100
1545 +#define RAMIPS_PPE_OFFSET              0x0200
1546 +#define RAMIPS_CMTABLE_OFFSET          0x0400
1547 +#define RAMIPS_POLICYTABLE_OFFSET      0x1000
1548 +
1549 +#define RT5350_PDMA_OFFSET             0x0800
1550 +#define RT5350_SDM_OFFSET              0x0c00
1551 +
1552 +#define RAMIPS_MDIO_ACCESS             (RAMIPS_FE_OFFSET + 0x00)
1553 +#define RAMIPS_MDIO_CFG                        (RAMIPS_FE_OFFSET + 0x04)
1554 +#define RAMIPS_FE_GLO_CFG              (RAMIPS_FE_OFFSET + 0x08)
1555 +#define RAMIPS_FE_RST_GL               (RAMIPS_FE_OFFSET + 0x0C)
1556 +#define RAMIPS_FE_INT_STATUS           (RAMIPS_FE_OFFSET + 0x10)
1557 +#define RAMIPS_FE_INT_ENABLE           (RAMIPS_FE_OFFSET + 0x14)
1558 +#define RAMIPS_MDIO_CFG2               (RAMIPS_FE_OFFSET + 0x18)
1559 +#define RAMIPS_FOC_TS_T                        (RAMIPS_FE_OFFSET + 0x1C)
1560 +
1561 +#define        RAMIPS_GDMA1_FWD_CFG            (RAMIPS_GDMA_OFFSET + 0x00)
1562 +#define RAMIPS_GDMA1_SCH_CFG           (RAMIPS_GDMA_OFFSET + 0x04)
1563 +#define RAMIPS_GDMA1_SHPR_CFG          (RAMIPS_GDMA_OFFSET + 0x08)
1564 +#define RAMIPS_GDMA1_MAC_ADRL          (RAMIPS_GDMA_OFFSET + 0x0C)
1565 +#define RAMIPS_GDMA1_MAC_ADRH          (RAMIPS_GDMA_OFFSET + 0x10)
1566 +
1567 +#define        RAMIPS_GDMA2_FWD_CFG            (RAMIPS_GDMA2_OFFSET + 0x00)
1568 +#define RAMIPS_GDMA2_SCH_CFG           (RAMIPS_GDMA2_OFFSET + 0x04)
1569 +#define RAMIPS_GDMA2_SHPR_CFG          (RAMIPS_GDMA2_OFFSET + 0x08)
1570 +#define RAMIPS_GDMA2_MAC_ADRL          (RAMIPS_GDMA2_OFFSET + 0x0C)
1571 +#define RAMIPS_GDMA2_MAC_ADRH          (RAMIPS_GDMA2_OFFSET + 0x10)
1572 +
1573 +#define RAMIPS_PSE_FQ_CFG              (RAMIPS_PSE_OFFSET + 0x00)
1574 +#define RAMIPS_CDMA_FC_CFG             (RAMIPS_PSE_OFFSET + 0x04)
1575 +#define RAMIPS_GDMA1_FC_CFG            (RAMIPS_PSE_OFFSET + 0x08)
1576 +#define RAMIPS_GDMA2_FC_CFG            (RAMIPS_PSE_OFFSET + 0x0C)
1577 +
1578 +#define RAMIPS_CDMA_CSG_CFG            (RAMIPS_CDMA_OFFSET + 0x00)
1579 +#define RAMIPS_CDMA_SCH_CFG            (RAMIPS_CDMA_OFFSET + 0x04)
1580 +
1581 +#define RT5350_TX_BASE_PTR0            (RT5350_PDMA_OFFSET + 0x00)
1582 +#define RT5350_TX_MAX_CNT0             (RT5350_PDMA_OFFSET + 0x04)
1583 +#define RT5350_TX_CTX_IDX0             (RT5350_PDMA_OFFSET + 0x08)
1584 +#define RT5350_TX_DTX_IDX0             (RT5350_PDMA_OFFSET + 0x0C)
1585 +#define RT5350_TX_BASE_PTR1            (RT5350_PDMA_OFFSET + 0x10)
1586 +#define RT5350_TX_MAX_CNT1             (RT5350_PDMA_OFFSET + 0x14)
1587 +#define RT5350_TX_CTX_IDX1             (RT5350_PDMA_OFFSET + 0x18)
1588 +#define RT5350_TX_DTX_IDX1             (RT5350_PDMA_OFFSET + 0x1C)
1589 +#define RT5350_TX_BASE_PTR2            (RT5350_PDMA_OFFSET + 0x20)
1590 +#define RT5350_TX_MAX_CNT2             (RT5350_PDMA_OFFSET + 0x24)
1591 +#define RT5350_TX_CTX_IDX2             (RT5350_PDMA_OFFSET + 0x28)
1592 +#define RT5350_TX_DTX_IDX2             (RT5350_PDMA_OFFSET + 0x2C)
1593 +#define RT5350_TX_BASE_PTR3            (RT5350_PDMA_OFFSET + 0x30)
1594 +#define RT5350_TX_MAX_CNT3             (RT5350_PDMA_OFFSET + 0x34)
1595 +#define RT5350_TX_CTX_IDX3             (RT5350_PDMA_OFFSET + 0x38)
1596 +#define RT5350_TX_DTX_IDX3             (RT5350_PDMA_OFFSET + 0x3C)
1597 +#define RT5350_RX_BASE_PTR0            (RT5350_PDMA_OFFSET + 0x100)
1598 +#define RT5350_RX_MAX_CNT0             (RT5350_PDMA_OFFSET + 0x104)
1599 +#define RT5350_RX_CALC_IDX0            (RT5350_PDMA_OFFSET + 0x108)
1600 +#define RT5350_RX_DRX_IDX0             (RT5350_PDMA_OFFSET + 0x10C)
1601 +#define RT5350_RX_BASE_PTR1            (RT5350_PDMA_OFFSET + 0x110)
1602 +#define RT5350_RX_MAX_CNT1             (RT5350_PDMA_OFFSET + 0x114)
1603 +#define RT5350_RX_CALC_IDX1            (RT5350_PDMA_OFFSET + 0x118)
1604 +#define RT5350_RX_DRX_IDX1             (RT5350_PDMA_OFFSET + 0x11C)
1605 +#define RT5350_PDMA_GLO_CFG            (RT5350_PDMA_OFFSET + 0x204)
1606 +#define RT5350_PDMA_RST_CFG            (RT5350_PDMA_OFFSET + 0x208)
1607 +#define RT5350_DLY_INT_CFG             (RT5350_PDMA_OFFSET + 0x20c)
1608 +#define RT5350_FE_INT_STATUS           (RT5350_PDMA_OFFSET + 0x220)
1609 +#define RT5350_FE_INT_ENABLE           (RT5350_PDMA_OFFSET + 0x228)
1610 +#define RT5350_PDMA_SCH_CFG            (RT5350_PDMA_OFFSET + 0x280)
1611 +
1612 +
1613 +#define RAMIPS_PDMA_GLO_CFG            (RAMIPS_PDMA_OFFSET + 0x00)
1614 +#define RAMIPS_PDMA_RST_CFG            (RAMIPS_PDMA_OFFSET + 0x04)
1615 +#define RAMIPS_PDMA_SCH_CFG            (RAMIPS_PDMA_OFFSET + 0x08)
1616 +#define RAMIPS_DLY_INT_CFG             (RAMIPS_PDMA_OFFSET + 0x0C)
1617 +#define RAMIPS_TX_BASE_PTR0            (RAMIPS_PDMA_OFFSET + 0x10)
1618 +#define RAMIPS_TX_MAX_CNT0             (RAMIPS_PDMA_OFFSET + 0x14)
1619 +#define RAMIPS_TX_CTX_IDX0             (RAMIPS_PDMA_OFFSET + 0x18)
1620 +#define RAMIPS_TX_DTX_IDX0             (RAMIPS_PDMA_OFFSET + 0x1C)
1621 +#define RAMIPS_TX_BASE_PTR1            (RAMIPS_PDMA_OFFSET + 0x20)
1622 +#define RAMIPS_TX_MAX_CNT1             (RAMIPS_PDMA_OFFSET + 0x24)
1623 +#define RAMIPS_TX_CTX_IDX1             (RAMIPS_PDMA_OFFSET + 0x28)
1624 +#define RAMIPS_TX_DTX_IDX1             (RAMIPS_PDMA_OFFSET + 0x2C)
1625 +#define RAMIPS_RX_BASE_PTR0            (RAMIPS_PDMA_OFFSET + 0x30)
1626 +#define RAMIPS_RX_MAX_CNT0             (RAMIPS_PDMA_OFFSET + 0x34)
1627 +#define RAMIPS_RX_CALC_IDX0            (RAMIPS_PDMA_OFFSET + 0x38)
1628 +#define RAMIPS_RX_DRX_IDX0             (RAMIPS_PDMA_OFFSET + 0x3C)
1629 +#define RAMIPS_TX_BASE_PTR2            (RAMIPS_PDMA_OFFSET + 0x40)
1630 +#define RAMIPS_TX_MAX_CNT2             (RAMIPS_PDMA_OFFSET + 0x44)
1631 +#define RAMIPS_TX_CTX_IDX2             (RAMIPS_PDMA_OFFSET + 0x48)
1632 +#define RAMIPS_TX_DTX_IDX2             (RAMIPS_PDMA_OFFSET + 0x4C)
1633 +#define RAMIPS_TX_BASE_PTR3            (RAMIPS_PDMA_OFFSET + 0x50)
1634 +#define RAMIPS_TX_MAX_CNT3             (RAMIPS_PDMA_OFFSET + 0x54)
1635 +#define RAMIPS_TX_CTX_IDX3             (RAMIPS_PDMA_OFFSET + 0x58)
1636 +#define RAMIPS_TX_DTX_IDX3             (RAMIPS_PDMA_OFFSET + 0x5C)
1637 +#define RAMIPS_RX_BASE_PTR1            (RAMIPS_PDMA_OFFSET + 0x60)
1638 +#define RAMIPS_RX_MAX_CNT1             (RAMIPS_PDMA_OFFSET + 0x64)
1639 +#define RAMIPS_RX_CALC_IDX1            (RAMIPS_PDMA_OFFSET + 0x68)
1640 +#define RAMIPS_RX_DRX_IDX1             (RAMIPS_PDMA_OFFSET + 0x6C)
1641 +
1642 +#define RT5350_SDM_CFG                 (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
1643 +#define RT5350_SDM_RRING               (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
1644 +#define RT5350_SDM_TRING               (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
1645 +#define RT5350_SDM_MAC_ADRL            (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
1646 +#define RT5350_SDM_MAC_ADRH            (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
1647 +#define RT5350_SDM_TPCNT               (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
1648 +#define RT5350_SDM_TBCNT               (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
1649 +#define RT5350_SDM_RPCNT               (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
1650 +#define RT5350_SDM_RBCNT               (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
1651 +#define RT5350_SDM_CS_ERR              (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
1652 +
1653 +#define RT5350_SDM_ICS_EN              BIT(16)
1654 +#define RT5350_SDM_TCS_EN              BIT(17)
1655 +#define RT5350_SDM_UCS_EN              BIT(18)
1656 +
1657 +
1658 +/* MDIO_CFG register bits */
1659 +#define RAMIPS_MDIO_CFG_AUTO_POLL_EN   BIT(29)
1660 +#define RAMIPS_MDIO_CFG_GP1_BP_EN      BIT(16)
1661 +#define RAMIPS_MDIO_CFG_GP1_FRC_EN     BIT(15)
1662 +#define RAMIPS_MDIO_CFG_GP1_SPEED_10   (0 << 13)
1663 +#define RAMIPS_MDIO_CFG_GP1_SPEED_100  (1 << 13)
1664 +#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
1665 +#define RAMIPS_MDIO_CFG_GP1_DUPLEX     BIT(12)
1666 +#define RAMIPS_MDIO_CFG_GP1_FC_TX      BIT(11)
1667 +#define RAMIPS_MDIO_CFG_GP1_FC_RX      BIT(10)
1668 +#define RAMIPS_MDIO_CFG_GP1_LNK_DWN    BIT(9)
1669 +#define RAMIPS_MDIO_CFG_GP1_AN_FAIL    BIT(8)
1670 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1  (0 << 6)
1671 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2  (1 << 6)
1672 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4  (2 << 6)
1673 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8  (3 << 6)
1674 +#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
1675 +#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
1676 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0  (0 << 2)
1677 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200        (1 << 2)
1678 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400        (2 << 2)
1679 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV        (3 << 2)
1680 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0  0
1681 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200        1
1682 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400        2
1683 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV        3
1684 +
1685 +/* uni-cast port */
1686 +#define RAMIPS_GDM1_ICS_EN             BIT(22)
1687 +#define RAMIPS_GDM1_TCS_EN             BIT(21)
1688 +#define RAMIPS_GDM1_UCS_EN             BIT(20)
1689 +#define RAMIPS_GDM1_JMB_EN             BIT(19)
1690 +#define RAMIPS_GDM1_STRPCRC            BIT(16)
1691 +#define RAMIPS_GDM1_UFRC_P_CPU         (0 << 12)
1692 +#define RAMIPS_GDM1_UFRC_P_GDMA1       (1 << 12)
1693 +#define RAMIPS_GDM1_UFRC_P_PPE         (6 << 12)
1694 +
1695 +/* checksums */
1696 +#define RAMIPS_ICS_GEN_EN              BIT(2)
1697 +#define RAMIPS_UCS_GEN_EN              BIT(1)
1698 +#define RAMIPS_TCS_GEN_EN              BIT(0)
1699 +
1700 +/* dma ring */
1701 +#define RAMIPS_PST_DRX_IDX0            BIT(16)
1702 +#define RAMIPS_PST_DTX_IDX3            BIT(3)
1703 +#define RAMIPS_PST_DTX_IDX2            BIT(2)
1704 +#define RAMIPS_PST_DTX_IDX1            BIT(1)
1705 +#define RAMIPS_PST_DTX_IDX0            BIT(0)
1706 +
1707 +#define RAMIPS_TX_WB_DDONE             BIT(6)
1708 +#define RAMIPS_RX_DMA_BUSY             BIT(3)
1709 +#define RAMIPS_TX_DMA_BUSY             BIT(1)
1710 +#define RAMIPS_RX_DMA_EN               BIT(2)
1711 +#define RAMIPS_TX_DMA_EN               BIT(0)
1712 +
1713 +#define RAMIPS_PDMA_SIZE_4DWORDS       (0 << 4)
1714 +#define RAMIPS_PDMA_SIZE_8DWORDS       (1 << 4)
1715 +#define RAMIPS_PDMA_SIZE_16DWORDS      (2 << 4)
1716 +
1717 +#define RAMIPS_US_CYC_CNT_MASK         0xff
1718 +#define RAMIPS_US_CYC_CNT_SHIFT                0x8
1719 +#define RAMIPS_US_CYC_CNT_DIVISOR      1000000
1720 +
1721 +#define RX_DMA_PLEN0(_x)               (((_x) >> 16) & 0x3fff)
1722 +#define RX_DMA_LSO                     BIT(30)
1723 +#define RX_DMA_DONE                    BIT(31)
1724 +
1725 +struct ramips_rx_dma {
1726 +       unsigned int rxd1;
1727 +       unsigned int rxd2;
1728 +       unsigned int rxd3;
1729 +       unsigned int rxd4;
1730 +} __packed __aligned(4);
1731 +
1732 +#define TX_DMA_PLEN0_MASK              ((0x3fff) << 16)
1733 +#define TX_DMA_PLEN0(_x)               (((_x) & 0x3fff) << 16)
1734 +#define TX_DMA_LSO                     BIT(30)
1735 +#define TX_DMA_DONE                    BIT(31)
1736 +#define TX_DMA_QN(_x)                  ((_x) << 16)
1737 +#define TX_DMA_PN(_x)                  ((_x) << 24)
1738 +#define TX_DMA_QN_MASK                 TX_DMA_QN(0x7)
1739 +#define TX_DMA_PN_MASK                 TX_DMA_PN(0x7)
1740 +
1741 +struct ramips_tx_dma {
1742 +       unsigned int txd1;
1743 +       unsigned int txd2;
1744 +       unsigned int txd3;
1745 +       unsigned int txd4;
1746 +} __packed __aligned(4);
1747 +
1748 +struct raeth_tx_info {
1749 +       struct ramips_tx_dma    *tx_desc;
1750 +       struct sk_buff          *tx_skb;
1751 +};
1752 +
1753 +struct raeth_rx_info {
1754 +       struct ramips_rx_dma    *rx_desc;
1755 +       struct sk_buff          *rx_skb;
1756 +       dma_addr_t              rx_dma;
1757 +       unsigned int            pad;
1758 +};
1759 +
1760 +struct raeth_int_stats {
1761 +       unsigned long           rx_delayed;
1762 +       unsigned long           tx_delayed;
1763 +       unsigned long           rx_done0;
1764 +       unsigned long           tx_done0;
1765 +       unsigned long           tx_done1;
1766 +       unsigned long           tx_done2;
1767 +       unsigned long           tx_done3;
1768 +       unsigned long           rx_coherent;
1769 +       unsigned long           tx_coherent;
1770 +
1771 +       unsigned long           pse_fq_empty;
1772 +       unsigned long           pse_p0_fc;
1773 +       unsigned long           pse_p1_fc;
1774 +       unsigned long           pse_p2_fc;
1775 +       unsigned long           pse_buf_drop;
1776 +
1777 +       unsigned long           total;
1778 +};
1779 +
1780 +struct raeth_debug {
1781 +       struct dentry           *debugfs_dir;
1782 +
1783 +       struct raeth_int_stats  int_stats;
1784 +};
1785 +
1786 +struct raeth_priv
1787 +{
1788 +       struct device_node      *of_node;
1789 +
1790 +       struct raeth_rx_info    *rx_info;
1791 +       dma_addr_t              rx_desc_dma;
1792 +       struct tasklet_struct   rx_tasklet;
1793 +       struct ramips_rx_dma    *rx;
1794 +
1795 +       struct raeth_tx_info    *tx_info;
1796 +       dma_addr_t              tx_desc_dma;
1797 +       struct tasklet_struct   tx_housekeeping_tasklet;
1798 +       struct ramips_tx_dma    *tx;
1799 +
1800 +       unsigned int            skb_free_idx;
1801 +
1802 +       spinlock_t              page_lock;
1803 +       struct net_device       *netdev;
1804 +       struct device           *parent;
1805 +
1806 +       int                     link;
1807 +       int                     speed;
1808 +       int                     duplex;
1809 +       int                     tx_fc;
1810 +       int                     rx_fc;
1811 +
1812 +       struct mii_bus          *mii_bus;
1813 +       int                     mii_irq[PHY_MAX_ADDR];
1814 +       struct phy_device       *phy_dev;
1815 +       spinlock_t              phy_lock;
1816 +       unsigned long           sys_freq;
1817 +
1818 +       unsigned char           mac[6];
1819 +       void                    (*reset_fe)(void);
1820 +       int                     min_pkt_len;
1821 +
1822 +       u32                     phy_mask;
1823 +       phy_interface_t         phy_if_mode;
1824 +
1825 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1826 +       struct raeth_debug      debug;
1827 +#endif
1828 +};
1829 +
1830 +struct ramips_soc_data
1831 +{
1832 +       unsigned char mac[6];
1833 +       void (*reset_fe)(void);
1834 +       int min_pkt_len;
1835 +};
1836 +
1837 +
1838 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1839 +int raeth_debugfs_root_init(void);
1840 +void raeth_debugfs_root_exit(void);
1841 +int raeth_debugfs_init(struct raeth_priv *re);
1842 +void raeth_debugfs_exit(struct raeth_priv *re);
1843 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status);
1844 +#else
1845 +static inline int raeth_debugfs_root_init(void) { return 0; }
1846 +static inline void raeth_debugfs_root_exit(void) {}
1847 +static inline int raeth_debugfs_init(struct raeth_priv *re) { return 0; }
1848 +static inline void raeth_debugfs_exit(struct raeth_priv *re) {}
1849 +static inline void raeth_debugfs_update_int_stats(struct raeth_priv *re,
1850 +                                                 u32 status) {}
1851 +#endif /* CONFIG_NET_RAMIPS_DEBUG_FS */
1852 +
1853 +#endif /* RAMIPS_ETH_H */
1854 --- /dev/null
1855 +++ b/drivers/net/ethernet/ramips/ramips_main.c
1856 @@ -0,0 +1,1281 @@
1857 +/*
1858 + *   This program is free software; you can redistribute it and/or modify
1859 + *   it under the terms of the GNU General Public License as published by
1860 + *   the Free Software Foundation; version 2 of the License
1861 + *
1862 + *   This program is distributed in the hope that it will be useful,
1863 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1864 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1865 + *   GNU General Public License for more details.
1866 + *
1867 + *   You should have received a copy of the GNU General Public License
1868 + *   along with this program; if not, write to the Free Software
1869 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1870 + *
1871 + *   Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1872 + */
1873 +
1874 +#include <linux/module.h>
1875 +#include <linux/kernel.h>
1876 +#include <linux/types.h>
1877 +#include <linux/dma-mapping.h>
1878 +#include <linux/init.h>
1879 +#include <linux/skbuff.h>
1880 +#include <linux/etherdevice.h>
1881 +#include <linux/ethtool.h>
1882 +#include <linux/platform_device.h>
1883 +#include <linux/phy.h>
1884 +#include <linux/of_device.h>
1885 +#include <linux/clk.h>
1886 +#include <linux/of_net.h>
1887 +#include <linux/of_mdio.h>
1888 +
1889 +#include "ramips_eth.h"
1890 +
1891 +#define TX_TIMEOUT (20 * HZ / 100)
1892 +#define        MAX_RX_LENGTH   1600
1893 +
1894 +#ifdef CONFIG_SOC_RT305X
1895 +#include <rt305x.h>
1896 +#include "ramips_esw.c"
1897 +#else
1898 +#include <asm/mach-ralink/ralink_regs.h>
1899 +static inline int rt305x_esw_init(void) { return 0; }
1900 +static inline void rt305x_esw_exit(void) { }
1901 +static inline int soc_is_rt5350(void) { return 0; }
1902 +#endif
1903 +
1904 +#define phys_to_bus(a)  (a & 0x1FFFFFFF)
1905 +
1906 +#ifdef CONFIG_NET_RAMIPS_DEBUG
1907 +#define RADEBUG(fmt, args...)  printk(KERN_DEBUG fmt, ## args)
1908 +#else
1909 +#define RADEBUG(fmt, args...)  do {} while (0)
1910 +#endif
1911 +
1912 +#define RX_DLY_INT ((soc_is_rt5350())?(RT5350_RX_DLY_INT):(RAMIPS_RX_DLY_INT))
1913 +#define TX_DLY_INT ((soc_is_rt5350())?(RT5350_TX_DLY_INT):(RAMIPS_TX_DLY_INT))
1914 +
1915 +enum raeth_reg {
1916 +       RAETH_REG_PDMA_GLO_CFG = 0,
1917 +       RAETH_REG_PDMA_RST_CFG,
1918 +       RAETH_REG_DLY_INT_CFG,
1919 +       RAETH_REG_TX_BASE_PTR0,
1920 +       RAETH_REG_TX_MAX_CNT0,
1921 +       RAETH_REG_TX_CTX_IDX0,
1922 +       RAETH_REG_RX_BASE_PTR0,
1923 +       RAETH_REG_RX_MAX_CNT0,
1924 +       RAETH_REG_RX_CALC_IDX0,
1925 +       RAETH_REG_FE_INT_ENABLE,
1926 +       RAETH_REG_FE_INT_STATUS,
1927 +       RAETH_REG_COUNT
1928 +};
1929 +
1930 +static const u32 ramips_reg_table[RAETH_REG_COUNT] = {
1931 +       [RAETH_REG_PDMA_GLO_CFG] = RAMIPS_PDMA_GLO_CFG,
1932 +       [RAETH_REG_PDMA_RST_CFG] = RAMIPS_PDMA_RST_CFG,
1933 +       [RAETH_REG_DLY_INT_CFG] = RAMIPS_DLY_INT_CFG,
1934 +       [RAETH_REG_TX_BASE_PTR0] = RAMIPS_TX_BASE_PTR0,
1935 +       [RAETH_REG_TX_MAX_CNT0] = RAMIPS_TX_MAX_CNT0,
1936 +       [RAETH_REG_TX_CTX_IDX0] = RAMIPS_TX_CTX_IDX0,
1937 +       [RAETH_REG_RX_BASE_PTR0] = RAMIPS_RX_BASE_PTR0,
1938 +       [RAETH_REG_RX_MAX_CNT0] = RAMIPS_RX_MAX_CNT0,
1939 +       [RAETH_REG_RX_CALC_IDX0] = RAMIPS_RX_CALC_IDX0,
1940 +       [RAETH_REG_FE_INT_ENABLE] = RAMIPS_FE_INT_ENABLE,
1941 +       [RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS,
1942 +};
1943 +
1944 +static const u32 rt5350_reg_table[RAETH_REG_COUNT] = {
1945 +       [RAETH_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
1946 +       [RAETH_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
1947 +       [RAETH_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
1948 +       [RAETH_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
1949 +       [RAETH_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
1950 +       [RAETH_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
1951 +       [RAETH_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
1952 +       [RAETH_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
1953 +       [RAETH_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
1954 +       [RAETH_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
1955 +       [RAETH_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
1956 +};
1957 +
1958 +static struct net_device * ramips_dev;
1959 +static void __iomem *ramips_fe_base = 0;
1960 +
1961 +static inline u32 get_reg_offset(enum raeth_reg reg)
1962 +{
1963 +       const u32 *table;
1964 +
1965 +       if (soc_is_rt5350())
1966 +               table = rt5350_reg_table;
1967 +       else
1968 +               table = ramips_reg_table;
1969 +
1970 +       return table[reg];
1971 +}
1972 +
1973 +static inline void
1974 +ramips_fe_wr(u32 val, unsigned reg)
1975 +{
1976 +       __raw_writel(val, ramips_fe_base + reg);
1977 +}
1978 +
1979 +static inline u32
1980 +ramips_fe_rr(unsigned reg)
1981 +{
1982 +       return __raw_readl(ramips_fe_base + reg);
1983 +}
1984 +
1985 +static inline void
1986 +ramips_fe_twr(u32 val, enum raeth_reg reg)
1987 +{
1988 +       ramips_fe_wr(val, get_reg_offset(reg));
1989 +}
1990 +
1991 +static inline u32
1992 +ramips_fe_trr(enum raeth_reg reg)
1993 +{
1994 +       return ramips_fe_rr(get_reg_offset(reg));
1995 +}
1996 +
1997 +static inline void
1998 +ramips_fe_int_disable(u32 mask)
1999 +{
2000 +       ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) & ~mask,
2001 +                    RAETH_REG_FE_INT_ENABLE);
2002 +       /* flush write */
2003 +       ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2004 +}
2005 +
2006 +static inline void
2007 +ramips_fe_int_enable(u32 mask)
2008 +{
2009 +       ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) | mask,
2010 +                    RAETH_REG_FE_INT_ENABLE);
2011 +       /* flush write */
2012 +       ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2013 +}
2014 +
2015 +static inline void
2016 +ramips_hw_set_macaddr(unsigned char *mac)
2017 +{
2018 +       if (soc_is_rt5350()) {
2019 +               ramips_fe_wr((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
2020 +               ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2021 +                            RT5350_SDM_MAC_ADRL);
2022 +       } else {
2023 +               ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH);
2024 +               ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2025 +                            RAMIPS_GDMA1_MAC_ADRL);
2026 +       }
2027 +}
2028 +
2029 +static struct sk_buff *
2030 +ramips_alloc_skb(struct raeth_priv *re)
2031 +{
2032 +       struct sk_buff *skb;
2033 +
2034 +       skb = netdev_alloc_skb(re->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2035 +       if (!skb)
2036 +               return NULL;
2037 +
2038 +       skb_reserve(skb, NET_IP_ALIGN);
2039 +
2040 +       return skb;
2041 +}
2042 +
2043 +static void
2044 +ramips_ring_setup(struct raeth_priv *re)
2045 +{
2046 +       int len;
2047 +       int i;
2048 +
2049 +       memset(re->tx_info, 0, NUM_TX_DESC * sizeof(struct raeth_tx_info));
2050 +
2051 +       len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2052 +       memset(re->tx, 0, len);
2053 +
2054 +       for (i = 0; i < NUM_TX_DESC; i++) {
2055 +               struct raeth_tx_info *txi;
2056 +               struct ramips_tx_dma *txd;
2057 +
2058 +               txd = &re->tx[i];
2059 +               txd->txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
2060 +               txd->txd2 = TX_DMA_LSO | TX_DMA_DONE;
2061 +
2062 +               txi = &re->tx_info[i];
2063 +               txi->tx_desc = txd;
2064 +               if (txi->tx_skb != NULL) {
2065 +                       netdev_warn(re->netdev,
2066 +                                   "dirty skb for TX desc %d\n", i);
2067 +                       txi->tx_skb = NULL;
2068 +               }
2069 +       }
2070 +
2071 +       len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2072 +       memset(re->rx, 0, len);
2073 +
2074 +       for (i = 0; i < NUM_RX_DESC; i++) {
2075 +               struct raeth_rx_info *rxi;
2076 +               struct ramips_rx_dma *rxd;
2077 +               dma_addr_t dma_addr;
2078 +
2079 +               rxd = &re->rx[i];
2080 +               rxi = &re->rx_info[i];
2081 +               BUG_ON(rxi->rx_skb == NULL);
2082 +               dma_addr = dma_map_single(&re->netdev->dev, rxi->rx_skb->data,
2083 +                                         MAX_RX_LENGTH, DMA_FROM_DEVICE);
2084 +               rxi->rx_dma = dma_addr;
2085 +               rxi->rx_desc = rxd;
2086 +
2087 +               rxd->rxd1 = (unsigned int) dma_addr;
2088 +               rxd->rxd2 = RX_DMA_LSO;
2089 +       }
2090 +
2091 +       /* flush descriptors */
2092 +       wmb();
2093 +}
2094 +
2095 +static void
2096 +ramips_ring_cleanup(struct raeth_priv *re)
2097 +{
2098 +       int i;
2099 +
2100 +       for (i = 0; i < NUM_RX_DESC; i++) {
2101 +               struct raeth_rx_info *rxi;
2102 +
2103 +               rxi = &re->rx_info[i];
2104 +               if (rxi->rx_skb)
2105 +                       dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2106 +                                        MAX_RX_LENGTH, DMA_FROM_DEVICE);
2107 +       }
2108 +
2109 +       for (i = 0; i < NUM_TX_DESC; i++) {
2110 +               struct raeth_tx_info *txi;
2111 +
2112 +               txi = &re->tx_info[i];
2113 +               if (txi->tx_skb) {
2114 +                       dev_kfree_skb_any(txi->tx_skb);
2115 +                       txi->tx_skb = NULL;
2116 +               }
2117 +       }
2118 +
2119 +       netdev_reset_queue(re->netdev);
2120 +}
2121 +
2122 +#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT3883)
2123 +
2124 +#define RAMIPS_MDIO_RETRY      1000
2125 +
2126 +static unsigned char *ramips_speed_str(struct raeth_priv *re)
2127 +{
2128 +       switch (re->speed) {
2129 +       case SPEED_1000:
2130 +               return "1000";
2131 +       case SPEED_100:
2132 +               return "100";
2133 +       case SPEED_10:
2134 +               return "10";
2135 +       }
2136 +
2137 +       return "?";
2138 +}
2139 +
2140 +static void ramips_link_adjust(struct raeth_priv *re)
2141 +{
2142 +       u32 mdio_cfg;
2143 +
2144 +       if (!re->link) {
2145 +               netif_carrier_off(re->netdev);
2146 +               netdev_info(re->netdev, "link down\n");
2147 +               return;
2148 +       }
2149 +
2150 +       mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
2151 +                  RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 |
2152 +                  RAMIPS_MDIO_CFG_GP1_FRC_EN;
2153 +
2154 +       if (re->duplex == DUPLEX_FULL)
2155 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX;
2156 +
2157 +       if (re->tx_fc)
2158 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX;
2159 +
2160 +       if (re->rx_fc)
2161 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX;
2162 +
2163 +       switch (re->speed) {
2164 +       case SPEED_10:
2165 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10;
2166 +               break;
2167 +       case SPEED_100:
2168 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100;
2169 +               break;
2170 +       case SPEED_1000:
2171 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000;
2172 +               break;
2173 +       default:
2174 +               BUG();
2175 +       }
2176 +
2177 +       ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG);
2178 +
2179 +       netif_carrier_on(re->netdev);
2180 +       netdev_info(re->netdev, "link up (%sMbps/%s duplex)\n",
2181 +                   ramips_speed_str(re),
2182 +                   (DUPLEX_FULL == re->duplex) ? "Full" : "Half");
2183 +}
2184 +
2185 +static int
2186 +ramips_mdio_wait_ready(struct raeth_priv *re)
2187 +{
2188 +       int retries;
2189 +
2190 +       retries = RAMIPS_MDIO_RETRY;
2191 +       while (1) {
2192 +               u32 t;
2193 +
2194 +               t = ramips_fe_rr(RAMIPS_MDIO_ACCESS);
2195 +               if ((t & (0x1 << 31)) == 0)
2196 +                       return 0;
2197 +
2198 +               if (retries-- == 0)
2199 +                       break;
2200 +
2201 +               udelay(1);
2202 +       }
2203 +
2204 +       dev_err(re->parent, "MDIO operation timed out\n");
2205 +       return -ETIMEDOUT;
2206 +}
2207 +
2208 +static int
2209 +ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2210 +{
2211 +       struct raeth_priv *re = bus->priv;
2212 +       int err;
2213 +       u32 t;
2214 +
2215 +       err = ramips_mdio_wait_ready(re);
2216 +       if (err)
2217 +               return 0xffff;
2218 +
2219 +       t = (phy_addr << 24) | (phy_reg << 16);
2220 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2221 +       t |= (1 << 31);
2222 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2223 +
2224 +       err = ramips_mdio_wait_ready(re);
2225 +       if (err)
2226 +               return 0xffff;
2227 +
2228 +       RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2229 +               phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2230 +
2231 +       return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff;
2232 +}
2233 +
2234 +static int
2235 +ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2236 +{
2237 +       struct raeth_priv *re = bus->priv;
2238 +       int err;
2239 +       u32 t;
2240 +
2241 +       RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2242 +               phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2243 +
2244 +       err = ramips_mdio_wait_ready(re);
2245 +       if (err)
2246 +               return err;
2247 +
2248 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2249 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2250 +       t |= (1 << 31);
2251 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2252 +
2253 +       return ramips_mdio_wait_ready(re);
2254 +}
2255 +
2256 +static int
2257 +ramips_mdio_reset(struct mii_bus *bus)
2258 +{
2259 +       /* TODO */
2260 +       return 0;
2261 +}
2262 +
2263 +static int
2264 +ramips_mdio_init(struct raeth_priv *re)
2265 +{
2266 +       struct device_node *mii_np;
2267 +       int err;
2268 +
2269 +       mii_np = of_get_child_by_name(re->of_node, "mdio-bus");
2270 +       if (!mii_np) {
2271 +               dev_err(re->parent, "no %s child node found", "mdio-bus");
2272 +               return -ENODEV;
2273 +       }
2274 +
2275 +       if (!of_device_is_available(mii_np)) {
2276 +               err = 0;
2277 +               goto err_put_node;
2278 +       }
2279 +
2280 +       re->mii_bus = mdiobus_alloc();
2281 +       if (re->mii_bus == NULL) {
2282 +               err = -ENOMEM;
2283 +               goto err_put_node;
2284 +       }
2285 +
2286 +       re->mii_bus->name = "ramips_mdio";
2287 +       re->mii_bus->read = ramips_mdio_read;
2288 +       re->mii_bus->write = ramips_mdio_write;
2289 +       re->mii_bus->reset = ramips_mdio_reset;
2290 +       re->mii_bus->irq = re->mii_irq;
2291 +       re->mii_bus->priv = re;
2292 +       re->mii_bus->parent = re->parent;
2293 +
2294 +       snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio");
2295 +       err = of_mdiobus_register(re->mii_bus, mii_np);
2296 +       if (err)
2297 +               goto err_free_bus;
2298 +
2299 +       return 0;
2300 +
2301 +err_free_bus:
2302 +       kfree(re->mii_bus);
2303 +err_put_node:
2304 +       of_node_put(mii_np);
2305 +       re->mii_bus = NULL;
2306 +       return err;
2307 +}
2308 +
2309 +static void
2310 +ramips_mdio_cleanup(struct raeth_priv *re)
2311 +{
2312 +       if (!re->mii_bus)
2313 +               return;
2314 +
2315 +       mdiobus_unregister(re->mii_bus);
2316 +       of_node_put(re->mii_bus->dev.of_node);
2317 +       kfree(re->mii_bus);
2318 +}
2319 +
2320 +static void
2321 +ramips_phy_link_adjust(struct net_device *dev)
2322 +{
2323 +       struct raeth_priv *re = netdev_priv(dev);
2324 +       struct phy_device *phydev = re->phy_dev;
2325 +       unsigned long flags;
2326 +       int status_change = 0;
2327 +
2328 +       spin_lock_irqsave(&re->phy_lock, flags);
2329 +
2330 +       if (phydev->link)
2331 +               if (re->duplex != phydev->duplex ||
2332 +                   re->speed != phydev->speed)
2333 +                       status_change = 1;
2334 +
2335 +       if (phydev->link != re->link)
2336 +               status_change = 1;
2337 +
2338 +       re->link = phydev->link;
2339 +       re->duplex = phydev->duplex;
2340 +       re->speed = phydev->speed;
2341 +
2342 +       if (status_change)
2343 +               ramips_link_adjust(re);
2344 +
2345 +       spin_unlock_irqrestore(&re->phy_lock, flags);
2346 +}
2347 +
2348 +static int
2349 +ramips_phy_connect_by_node(struct raeth_priv *re, struct device_node *phy_node)
2350 +{
2351 +       struct phy_device *phydev;
2352 +       int phy_mode;
2353 +
2354 +       phy_mode = of_get_phy_mode(re->of_node);
2355 +       if (phy_mode < 0) {
2356 +               dev_err(re->parent, "incorrect phy-mode\n");
2357 +               return -EINVAL;
2358 +       }
2359 +
2360 +       phydev = of_phy_connect(re->netdev, phy_node, ramips_phy_link_adjust,
2361 +                               0, phy_mode);
2362 +       if (IS_ERR(phydev)) {
2363 +               dev_err(re->parent, "could not connect to PHY\n");
2364 +               return PTR_ERR(re->phy_dev);
2365 +       }
2366 +
2367 +       phydev->supported &= PHY_GBIT_FEATURES;
2368 +       phydev->advertising = phydev->supported;
2369 +
2370 +       dev_info(re->parent,
2371 +                "connected to PHY at %s [uid=%08x, driver=%s]\n",
2372 +                dev_name(&phydev->dev), phydev->phy_id,
2373 +                phydev->drv->name);
2374 +
2375 +       re->phy_dev = phydev;
2376 +       re->link = 0;
2377 +       re->speed = 0;
2378 +       re->duplex = -1;
2379 +       re->rx_fc = 0;
2380 +       re->tx_fc = 0;
2381 +
2382 +       return 0;
2383 +}
2384 +
2385 +static int
2386 +ramips_phy_connect_fixed(struct raeth_priv *re, const __be32 *link, int size)
2387 +{
2388 +       if (size != (4 * sizeof(*link))) {
2389 +               dev_err(re->parent, "invalid fixed-link property\n");
2390 +               return -EINVAL;
2391 +       }
2392 +
2393 +       re->speed = be32_to_cpup(link++);
2394 +       re->duplex = be32_to_cpup(link++);
2395 +       re->tx_fc = be32_to_cpup(link++);
2396 +       re->rx_fc = be32_to_cpup(link++);
2397 +
2398 +       switch (re->speed) {
2399 +       case SPEED_10:
2400 +       case SPEED_100:
2401 +       case SPEED_1000:
2402 +               break;
2403 +       default:
2404 +               dev_err(re->parent, "invalid link speed: %d\n", re->speed);
2405 +               return -EINVAL;
2406 +       }
2407 +
2408 +       dev_info(re->parent, "using fixed link parameters\n");
2409 +       return 0;
2410 +}
2411 +
2412 +static int
2413 +ramips_phy_connect(struct raeth_priv *re)
2414 +{
2415 +       struct device_node *phy_node;
2416 +       const __be32 *p32;
2417 +       int size;
2418 +
2419 +       phy_node = of_parse_phandle(re->of_node, "phy-handle", 0);
2420 +       if (phy_node)
2421 +               return ramips_phy_connect_by_node(re, phy_node);
2422 +
2423 +       p32 = of_get_property(re->of_node, "ralink,fixed-link", &size);
2424 +       if (p32)
2425 +               return ramips_phy_connect_fixed(re, p32, size);
2426 +
2427 +       dev_err(re->parent, "unable to get connection type\n");
2428 +       return -EINVAL;
2429 +}
2430 +
2431 +static void
2432 +ramips_phy_disconnect(struct raeth_priv *re)
2433 +{
2434 +       if (re->phy_dev)
2435 +               phy_disconnect(re->phy_dev);
2436 +}
2437 +
2438 +static void
2439 +ramips_phy_start(struct raeth_priv *re)
2440 +{
2441 +       unsigned long flags;
2442 +
2443 +       if (re->phy_dev) {
2444 +               phy_start(re->phy_dev);
2445 +       } else {
2446 +               spin_lock_irqsave(&re->phy_lock, flags);
2447 +               re->link = 1;
2448 +               ramips_link_adjust(re);
2449 +               spin_unlock_irqrestore(&re->phy_lock, flags);
2450 +       }
2451 +}
2452 +
2453 +static void
2454 +ramips_phy_stop(struct raeth_priv *re)
2455 +{
2456 +       unsigned long flags;
2457 +
2458 +       if (re->phy_dev)
2459 +               phy_stop(re->phy_dev);
2460 +
2461 +       spin_lock_irqsave(&re->phy_lock, flags);
2462 +       re->link = 0;
2463 +       ramips_link_adjust(re);
2464 +       spin_unlock_irqrestore(&re->phy_lock, flags);
2465 +}
2466 +#else
2467 +static inline int
2468 +ramips_mdio_init(struct raeth_priv *re)
2469 +{
2470 +       return 0;
2471 +}
2472 +
2473 +static inline void
2474 +ramips_mdio_cleanup(struct raeth_priv *re)
2475 +{
2476 +}
2477 +
2478 +static inline int
2479 +ramips_phy_connect(struct raeth_priv *re)
2480 +{
2481 +       return 0;
2482 +}
2483 +
2484 +static inline void
2485 +ramips_phy_disconnect(struct raeth_priv *re)
2486 +{
2487 +}
2488 +
2489 +static inline void
2490 +ramips_phy_start(struct raeth_priv *re)
2491 +{
2492 +}
2493 +
2494 +static inline void
2495 +ramips_phy_stop(struct raeth_priv *re)
2496 +{
2497 +}
2498 +#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT3883 */
2499 +
2500 +static void
2501 +ramips_ring_free(struct raeth_priv *re)
2502 +{
2503 +       int len;
2504 +       int i;
2505 +
2506 +       if (re->rx_info) {
2507 +               for (i = 0; i < NUM_RX_DESC; i++) {
2508 +                       struct raeth_rx_info *rxi;
2509 +
2510 +                       rxi = &re->rx_info[i];
2511 +                       if (rxi->rx_skb)
2512 +                               dev_kfree_skb_any(rxi->rx_skb);
2513 +               }
2514 +               kfree(re->rx_info);
2515 +       }
2516 +
2517 +       if (re->rx) {
2518 +               len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2519 +               dma_free_coherent(&re->netdev->dev, len, re->rx,
2520 +                                 re->rx_desc_dma);
2521 +       }
2522 +
2523 +       if (re->tx) {
2524 +               len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2525 +               dma_free_coherent(&re->netdev->dev, len, re->tx,
2526 +                                 re->tx_desc_dma);
2527 +       }
2528 +
2529 +       kfree(re->tx_info);
2530 +}
2531 +
2532 +static int
2533 +ramips_ring_alloc(struct raeth_priv *re)
2534 +{
2535 +       int len;
2536 +       int err = -ENOMEM;
2537 +       int i;
2538 +
2539 +       re->tx_info = kzalloc(NUM_TX_DESC * sizeof(struct raeth_tx_info),
2540 +                             GFP_ATOMIC);
2541 +       if (!re->tx_info)
2542 +               goto err_cleanup;
2543 +
2544 +       re->rx_info = kzalloc(NUM_RX_DESC * sizeof(struct raeth_rx_info),
2545 +                             GFP_ATOMIC);
2546 +       if (!re->rx_info)
2547 +               goto err_cleanup;
2548 +
2549 +       /* allocate tx ring */
2550 +       len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2551 +       re->tx = dma_alloc_coherent(&re->netdev->dev, len,
2552 +                                         &re->tx_desc_dma, GFP_ATOMIC);
2553 +       if (!re->tx)
2554 +               goto err_cleanup;
2555 +
2556 +       /* allocate rx ring */
2557 +       len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2558 +       re->rx = dma_alloc_coherent(&re->netdev->dev, len,
2559 +                                   &re->rx_desc_dma, GFP_ATOMIC);
2560 +       if (!re->rx)
2561 +               goto err_cleanup;
2562 +
2563 +       for (i = 0; i < NUM_RX_DESC; i++) {
2564 +               struct sk_buff *skb;
2565 +
2566 +               skb = ramips_alloc_skb(re);
2567 +               if (!skb)
2568 +                       goto err_cleanup;
2569 +
2570 +               re->rx_info[i].rx_skb = skb;
2571 +       }
2572 +
2573 +       return 0;
2574 +
2575 +err_cleanup:
2576 +       ramips_ring_free(re);
2577 +       return err;
2578 +}
2579 +
2580 +static void
2581 +ramips_setup_dma(struct raeth_priv *re)
2582 +{
2583 +       ramips_fe_twr(re->tx_desc_dma, RAETH_REG_TX_BASE_PTR0);
2584 +       ramips_fe_twr(NUM_TX_DESC, RAETH_REG_TX_MAX_CNT0);
2585 +       ramips_fe_twr(0, RAETH_REG_TX_CTX_IDX0);
2586 +       ramips_fe_twr(RAMIPS_PST_DTX_IDX0, RAETH_REG_PDMA_RST_CFG);
2587 +
2588 +       ramips_fe_twr(re->rx_desc_dma, RAETH_REG_RX_BASE_PTR0);
2589 +       ramips_fe_twr(NUM_RX_DESC, RAETH_REG_RX_MAX_CNT0);
2590 +       ramips_fe_twr((NUM_RX_DESC - 1), RAETH_REG_RX_CALC_IDX0);
2591 +       ramips_fe_twr(RAMIPS_PST_DRX_IDX0, RAETH_REG_PDMA_RST_CFG);
2592 +}
2593 +
2594 +static int
2595 +ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
2596 +{
2597 +       struct raeth_priv *re = netdev_priv(dev);
2598 +       struct raeth_tx_info *txi, *txi_next;
2599 +       struct ramips_tx_dma *txd, *txd_next;
2600 +       unsigned long tx;
2601 +       unsigned int tx_next;
2602 +       dma_addr_t mapped_addr;
2603 +
2604 +       if (re->min_pkt_len) {
2605 +               if (skb->len < re->min_pkt_len) {
2606 +                       if (skb_padto(skb, re->min_pkt_len)) {
2607 +                               printk(KERN_ERR
2608 +                                      "ramips_eth: skb_padto failed\n");
2609 +                               kfree_skb(skb);
2610 +                               return 0;
2611 +                       }
2612 +                       skb_put(skb, re->min_pkt_len - skb->len);
2613 +               }
2614 +       }
2615 +
2616 +       dev->trans_start = jiffies;
2617 +       mapped_addr = dma_map_single(&re->netdev->dev, skb->data, skb->len,
2618 +                                    DMA_TO_DEVICE);
2619 +
2620 +       spin_lock(&re->page_lock);
2621 +       tx = ramips_fe_trr(RAETH_REG_TX_CTX_IDX0);
2622 +       tx_next = (tx + 1) % NUM_TX_DESC;
2623 +
2624 +       txi = &re->tx_info[tx];
2625 +       txd = txi->tx_desc;
2626 +       txi_next = &re->tx_info[tx_next];
2627 +       txd_next = txi_next->tx_desc;
2628 +
2629 +       if ((txi->tx_skb) || (txi_next->tx_skb) ||
2630 +           !(txd->txd2 & TX_DMA_DONE) ||
2631 +           !(txd_next->txd2 & TX_DMA_DONE))
2632 +               goto out;
2633 +
2634 +       txi->tx_skb = skb;
2635 +
2636 +       txd->txd1 = (unsigned int) mapped_addr;
2637 +       wmb();
2638 +       txd->txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
2639 +       dev->stats.tx_packets++;
2640 +       dev->stats.tx_bytes += skb->len;
2641 +       ramips_fe_twr(tx_next, RAETH_REG_TX_CTX_IDX0);
2642 +       netdev_sent_queue(dev, skb->len);
2643 +       spin_unlock(&re->page_lock);
2644 +       return NETDEV_TX_OK;
2645 +
2646 + out:
2647 +       spin_unlock(&re->page_lock);
2648 +       dev->stats.tx_dropped++;
2649 +       kfree_skb(skb);
2650 +       return NETDEV_TX_OK;
2651 +}
2652 +
2653 +static void
2654 +ramips_eth_rx_hw(unsigned long ptr)
2655 +{
2656 +       struct net_device *dev = (struct net_device *) ptr;
2657 +       struct raeth_priv *re = netdev_priv(dev);
2658 +       int rx;
2659 +       int max_rx = 16;
2660 +
2661 +       rx = ramips_fe_trr(RAETH_REG_RX_CALC_IDX0);
2662 +
2663 +       while (max_rx) {
2664 +               struct raeth_rx_info *rxi;
2665 +               struct ramips_rx_dma *rxd;
2666 +               struct sk_buff *rx_skb, *new_skb;
2667 +               int pktlen;
2668 +
2669 +               rx = (rx + 1) % NUM_RX_DESC;
2670 +
2671 +               rxi = &re->rx_info[rx];
2672 +               rxd = rxi->rx_desc;
2673 +               if (!(rxd->rxd2 & RX_DMA_DONE))
2674 +                       break;
2675 +
2676 +               rx_skb = rxi->rx_skb;
2677 +               pktlen = RX_DMA_PLEN0(rxd->rxd2);
2678 +
2679 +               new_skb = ramips_alloc_skb(re);
2680 +               /* Reuse the buffer on allocation failures */
2681 +               if (new_skb) {
2682 +                       dma_addr_t dma_addr;
2683 +
2684 +                       dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2685 +                                        MAX_RX_LENGTH, DMA_FROM_DEVICE);
2686 +
2687 +                       skb_put(rx_skb, pktlen);
2688 +                       rx_skb->dev = dev;
2689 +                       rx_skb->protocol = eth_type_trans(rx_skb, dev);
2690 +                       rx_skb->ip_summed = CHECKSUM_NONE;
2691 +                       dev->stats.rx_packets++;
2692 +                       dev->stats.rx_bytes += pktlen;
2693 +                       netif_rx(rx_skb);
2694 +
2695 +                       rxi->rx_skb = new_skb;
2696 +
2697 +                       dma_addr = dma_map_single(&re->netdev->dev,
2698 +                                                 new_skb->data,
2699 +                                                 MAX_RX_LENGTH,
2700 +                                                 DMA_FROM_DEVICE);
2701 +                       rxi->rx_dma = dma_addr;
2702 +                       rxd->rxd1 = (unsigned int) dma_addr;
2703 +                       wmb();
2704 +               } else {
2705 +                       dev->stats.rx_dropped++;
2706 +               }
2707 +
2708 +               rxd->rxd2 = RX_DMA_LSO;
2709 +               ramips_fe_twr(rx, RAETH_REG_RX_CALC_IDX0);
2710 +               max_rx--;
2711 +       }
2712 +
2713 +       if (max_rx == 0)
2714 +               tasklet_schedule(&re->rx_tasklet);
2715 +       else
2716 +               ramips_fe_int_enable(RX_DLY_INT);
2717 +}
2718 +
2719 +static void
2720 +ramips_eth_tx_housekeeping(unsigned long ptr)
2721 +{
2722 +       struct net_device *dev = (struct net_device*)ptr;
2723 +       struct raeth_priv *re = netdev_priv(dev);
2724 +       unsigned int bytes_compl = 0, pkts_compl = 0;
2725 +
2726 +       spin_lock(&re->page_lock);
2727 +       while (1) {
2728 +               struct raeth_tx_info *txi;
2729 +               struct ramips_tx_dma *txd;
2730 +
2731 +               txi = &re->tx_info[re->skb_free_idx];
2732 +               txd = txi->tx_desc;
2733 +
2734 +               if (!(txd->txd2 & TX_DMA_DONE) || !(txi->tx_skb))
2735 +                       break;
2736 +
2737 +               pkts_compl++;
2738 +               bytes_compl += txi->tx_skb->len;
2739 +
2740 +               dev_kfree_skb_irq(txi->tx_skb);
2741 +               txi->tx_skb = NULL;
2742 +               re->skb_free_idx++;
2743 +               if (re->skb_free_idx >= NUM_TX_DESC)
2744 +                       re->skb_free_idx = 0;
2745 +       }
2746 +       netdev_completed_queue(dev, pkts_compl, bytes_compl);
2747 +       spin_unlock(&re->page_lock);
2748 +
2749 +       ramips_fe_int_enable(TX_DLY_INT);
2750 +}
2751 +
2752 +static void
2753 +ramips_eth_timeout(struct net_device *dev)
2754 +{
2755 +       struct raeth_priv *re = netdev_priv(dev);
2756 +
2757 +       tasklet_schedule(&re->tx_housekeeping_tasklet);
2758 +}
2759 +
2760 +static irqreturn_t
2761 +ramips_eth_irq(int irq, void *dev)
2762 +{
2763 +       struct raeth_priv *re = netdev_priv(dev);
2764 +       unsigned int status;
2765 +
2766 +       status = ramips_fe_trr(RAETH_REG_FE_INT_STATUS);
2767 +       status &= ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2768 +
2769 +       if (!status)
2770 +               return IRQ_NONE;
2771 +
2772 +       ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS);
2773 +
2774 +       if (status & RX_DLY_INT) {
2775 +               ramips_fe_int_disable(RX_DLY_INT);
2776 +               tasklet_schedule(&re->rx_tasklet);
2777 +       }
2778 +
2779 +       if (status & TX_DLY_INT) {
2780 +               ramips_fe_int_disable(TX_DLY_INT);
2781 +               tasklet_schedule(&re->tx_housekeeping_tasklet);
2782 +       }
2783 +
2784 +       raeth_debugfs_update_int_stats(re, status);
2785 +
2786 +       return IRQ_HANDLED;
2787 +}
2788 +
2789 +static int
2790 +ramips_eth_hw_init(struct net_device *dev)
2791 +{
2792 +       struct raeth_priv *re = netdev_priv(dev);
2793 +       int err;
2794 +
2795 +       err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED,
2796 +                         dev_name(re->parent), dev);
2797 +       if (err)
2798 +               return err;
2799 +
2800 +       err = ramips_ring_alloc(re);
2801 +       if (err)
2802 +               goto err_free_irq;
2803 +
2804 +       ramips_ring_setup(re);
2805 +       ramips_hw_set_macaddr(dev->dev_addr);
2806 +
2807 +       ramips_setup_dma(re);
2808 +       ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) &
2809 +               ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) |
2810 +               ((re->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT),
2811 +               RAMIPS_FE_GLO_CFG);
2812 +
2813 +       tasklet_init(&re->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping,
2814 +                    (unsigned long)dev);
2815 +       tasklet_init(&re->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev);
2816 +
2817 +
2818 +       ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG);
2819 +       ramips_fe_twr(TX_DLY_INT | RX_DLY_INT, RAETH_REG_FE_INT_ENABLE);
2820 +       if (soc_is_rt5350()) {
2821 +               ramips_fe_wr(ramips_fe_rr(RT5350_SDM_CFG) &
2822 +                       ~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN | 0xffff),
2823 +                       RT5350_SDM_CFG);
2824 +       } else {
2825 +               ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
2826 +                       ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
2827 +                       RAMIPS_GDMA1_FWD_CFG);
2828 +               ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) &
2829 +                       ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN),
2830 +                       RAMIPS_CDMA_CSG_CFG);
2831 +               ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG);
2832 +       }
2833 +       ramips_fe_wr(1, RAMIPS_FE_RST_GL);
2834 +       ramips_fe_wr(0, RAMIPS_FE_RST_GL);
2835 +
2836 +       return 0;
2837 +
2838 +err_free_irq:
2839 +       free_irq(dev->irq, dev);
2840 +       return err;
2841 +}
2842 +
2843 +static int
2844 +ramips_eth_open(struct net_device *dev)
2845 +{
2846 +       struct raeth_priv *re = netdev_priv(dev);
2847 +
2848 +       ramips_fe_twr((ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & 0xff) |
2849 +               (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN |
2850 +               RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS),
2851 +               RAETH_REG_PDMA_GLO_CFG);
2852 +       ramips_phy_start(re);
2853 +       netif_start_queue(dev);
2854 +       return 0;
2855 +}
2856 +
2857 +static int
2858 +ramips_eth_stop(struct net_device *dev)
2859 +{
2860 +       struct raeth_priv *re = netdev_priv(dev);
2861 +
2862 +       ramips_fe_twr(ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) &
2863 +                    ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN),
2864 +                    RAETH_REG_PDMA_GLO_CFG);
2865 +
2866 +       netif_stop_queue(dev);
2867 +       ramips_phy_stop(re);
2868 +       RADEBUG("ramips_eth: stopped\n");
2869 +       return 0;
2870 +}
2871 +
2872 +static int __init
2873 +ramips_eth_probe(struct net_device *dev)
2874 +{
2875 +       struct raeth_priv *re = netdev_priv(dev);
2876 +       int err;
2877 +
2878 +       BUG_ON(!re->reset_fe);
2879 +       re->reset_fe();
2880 +       net_srandom(jiffies);
2881 +       memcpy(dev->dev_addr, re->mac, ETH_ALEN);
2882 +       of_get_mac_address_mtd(re->of_node, dev->dev_addr);
2883 +       ether_setup(dev);
2884 +       dev->mtu = 1500;
2885 +       dev->watchdog_timeo = TX_TIMEOUT;
2886 +       spin_lock_init(&re->page_lock);
2887 +       spin_lock_init(&re->phy_lock);
2888 +
2889 +       err = ramips_mdio_init(re);
2890 +       if (err)
2891 +               return err;
2892 +
2893 +       err = ramips_phy_connect(re);
2894 +       if (err)
2895 +               goto err_mdio_cleanup;
2896 +
2897 +       err = raeth_debugfs_init(re);
2898 +       if (err)
2899 +               goto err_phy_disconnect;
2900 +
2901 +       err = ramips_eth_hw_init(dev);
2902 +       if (err)
2903 +               goto err_debugfs;
2904 +
2905 +       return 0;
2906 +
2907 +err_debugfs:
2908 +       raeth_debugfs_exit(re);
2909 +err_phy_disconnect:
2910 +       ramips_phy_disconnect(re);
2911 +err_mdio_cleanup:
2912 +       ramips_mdio_cleanup(re);
2913 +       return err;
2914 +}
2915 +
2916 +static void
2917 +ramips_eth_uninit(struct net_device *dev)
2918 +{
2919 +       struct raeth_priv *re = netdev_priv(dev);
2920 +
2921 +       raeth_debugfs_exit(re);
2922 +       ramips_phy_disconnect(re);
2923 +       ramips_mdio_cleanup(re);
2924 +       ramips_fe_twr(0, RAETH_REG_FE_INT_ENABLE);
2925 +       free_irq(dev->irq, dev);
2926 +       tasklet_kill(&re->tx_housekeeping_tasklet);
2927 +       tasklet_kill(&re->rx_tasklet);
2928 +       ramips_ring_cleanup(re);
2929 +       ramips_ring_free(re);
2930 +}
2931 +
2932 +static const struct net_device_ops ramips_eth_netdev_ops = {
2933 +       .ndo_init               = ramips_eth_probe,
2934 +       .ndo_uninit             = ramips_eth_uninit,
2935 +       .ndo_open               = ramips_eth_open,
2936 +       .ndo_stop               = ramips_eth_stop,
2937 +       .ndo_start_xmit         = ramips_eth_hard_start_xmit,
2938 +       .ndo_tx_timeout         = ramips_eth_timeout,
2939 +       .ndo_change_mtu         = eth_change_mtu,
2940 +       .ndo_set_mac_address    = eth_mac_addr,
2941 +       .ndo_validate_addr      = eth_validate_addr,
2942 +};
2943 +
2944 +#ifdef CONFIG_SOC_RT305X
2945 +static void rt305x_fe_reset(void)
2946 +{
2947 +#define RT305X_RESET_FE                BIT(21)
2948 +#define RT305X_RESET_ESW       BIT(23)
2949 +#define SYSC_REG_RESET_CTRL    0x034
2950 +       u32 reset_bits = RT305X_RESET_FE;
2951 +
2952 +       if (soc_is_rt5350())
2953 +               reset_bits |= RT305X_RESET_ESW;
2954 +       rt_sysc_w32(reset_bits, SYSC_REG_RESET_CTRL);
2955 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
2956 +}
2957 +
2958 +struct ramips_soc_data rt3050_data = {
2959 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
2960 +       .reset_fe = rt305x_fe_reset,
2961 +       .min_pkt_len = 64,
2962 +};
2963 +
2964 +static const struct of_device_id ralink_eth_match[] = {
2965 +       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
2966 +       {},
2967 +};
2968 +#else
2969 +static void rt3883_fe_reset(void)
2970 +{
2971 +#define RT3883_SYSC_REG_RSTCTRL        0x34
2972 +#define RT3883_RSTCTRL_FE      BIT(21)
2973 +       u32 t;
2974 +
2975 +       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
2976 +       t |= RT3883_RSTCTRL_FE;
2977 +       rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
2978 +
2979 +       t &= ~RT3883_RSTCTRL_FE;
2980 +       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
2981 +}
2982 +
2983 +struct ramips_soc_data rt3883_data = {
2984 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
2985 +       .reset_fe = rt3883_fe_reset,
2986 +       .min_pkt_len = 64,
2987 +};
2988 +
2989 +static const struct of_device_id ralink_eth_match[] = {
2990 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
2991 +       {},
2992 +};
2993 +#endif
2994 +MODULE_DEVICE_TABLE(of, ralink_eth_match);
2995 +
2996 +static int
2997 +ramips_eth_plat_probe(struct platform_device *plat)
2998 +{
2999 +       struct raeth_priv *re;
3000 +       struct resource *res;
3001 +       struct clk *clk;
3002 +       int err;
3003 +       const struct of_device_id *match;
3004 +       const struct ramips_soc_data *soc = NULL;
3005 +
3006 +       match = of_match_device(ralink_eth_match, &plat->dev);
3007 +       if (match)
3008 +               soc = (const struct ramips_soc_data *) match->data;
3009 +
3010 +       if (!soc) {
3011 +               dev_err(&plat->dev, "no platform data specified\n");
3012 +               return -EINVAL;
3013 +       }
3014 +
3015 +       res = platform_get_resource(plat, IORESOURCE_MEM, 0);
3016 +       if (!res) {
3017 +               dev_err(&plat->dev, "no memory resource found\n");
3018 +               return -ENXIO;
3019 +       }
3020 +
3021 +       ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1);
3022 +       if (!ramips_fe_base)
3023 +               return -ENOMEM;
3024 +
3025 +       ramips_dev = alloc_etherdev(sizeof(struct raeth_priv));
3026 +       if (!ramips_dev) {
3027 +               dev_err(&plat->dev, "alloc_etherdev failed\n");
3028 +               err = -ENOMEM;
3029 +               goto err_unmap;
3030 +       }
3031 +
3032 +       strcpy(ramips_dev->name, "eth%d");
3033 +       ramips_dev->irq = platform_get_irq(plat, 0);
3034 +       if (ramips_dev->irq < 0) {
3035 +               dev_err(&plat->dev, "no IRQ resource found\n");
3036 +               err = -ENXIO;
3037 +               goto err_free_dev;
3038 +       }
3039 +       ramips_dev->addr_len = ETH_ALEN;
3040 +       ramips_dev->base_addr = (unsigned long)ramips_fe_base;
3041 +       ramips_dev->netdev_ops = &ramips_eth_netdev_ops;
3042 +
3043 +       re = netdev_priv(ramips_dev);
3044 +
3045 +       clk = clk_get(&plat->dev, NULL);
3046 +       if (IS_ERR(clk))
3047 +               panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
3048 +       re->sys_freq = clk_get_rate(clk);
3049 +
3050 +       re->netdev = ramips_dev;
3051 +       re->of_node = plat->dev.of_node;
3052 +       re->parent = &plat->dev;
3053 +       memcpy(re->mac, soc->mac, 6);
3054 +       re->reset_fe = soc->reset_fe;
3055 +       re->min_pkt_len = soc->min_pkt_len;
3056 +
3057 +       err = register_netdev(ramips_dev);
3058 +       if (err) {
3059 +               dev_err(&plat->dev, "error bringing up device\n");
3060 +               goto err_free_dev;
3061 +       }
3062 +
3063 +       netdev_info(ramips_dev, "done loading\n");
3064 +       return 0;
3065 +
3066 + err_free_dev:
3067 +       kfree(ramips_dev);
3068 + err_unmap:
3069 +       iounmap(ramips_fe_base);
3070 +       return err;
3071 +}
3072 +
3073 +static int
3074 +ramips_eth_plat_remove(struct platform_device *plat)
3075 +{
3076 +       unregister_netdev(ramips_dev);
3077 +       free_netdev(ramips_dev);
3078 +       RADEBUG("ramips_eth: unloaded\n");
3079 +       return 0;
3080 +}
3081 +
3082 +
3083 +
3084 +static struct platform_driver ramips_eth_driver = {
3085 +       .probe = ramips_eth_plat_probe,
3086 +       .remove = ramips_eth_plat_remove,
3087 +       .driver = {
3088 +               .name = "ramips_eth",
3089 +               .owner = THIS_MODULE,
3090 +               .of_match_table = ralink_eth_match
3091 +       },
3092 +};
3093 +
3094 +static int __init
3095 +ramips_eth_init(void)
3096 +{
3097 +       int ret;
3098 +
3099 +       ret = raeth_debugfs_root_init();
3100 +       if (ret)
3101 +               goto err_out;
3102 +
3103 +       ret = rt305x_esw_init();
3104 +       if (ret)
3105 +               goto err_debugfs_exit;
3106 +
3107 +       ret = platform_driver_register(&ramips_eth_driver);
3108 +       if (ret) {
3109 +               printk(KERN_ERR
3110 +                      "ramips_eth: Error registering platfom driver!\n");
3111 +               goto esw_cleanup;
3112 +       }
3113 +
3114 +       return 0;
3115 +
3116 +esw_cleanup:
3117 +       rt305x_esw_exit();
3118 +err_debugfs_exit:
3119 +       raeth_debugfs_root_exit();
3120 +err_out:
3121 +       return ret;
3122 +}
3123 +
3124 +static void __exit
3125 +ramips_eth_cleanup(void)
3126 +{
3127 +       platform_driver_unregister(&ramips_eth_driver);
3128 +       rt305x_esw_exit();
3129 +       raeth_debugfs_root_exit();
3130 +}
3131 +
3132 +module_init(ramips_eth_init);
3133 +module_exit(ramips_eth_cleanup);
3134 +
3135 +MODULE_LICENSE("GPL");
3136 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3137 +MODULE_DESCRIPTION("ethernet driver for ramips boards");