target/linux/ramips/patches-3.8/0129-MIPS-ralink-add-support-for-periodic-timer-irq.patch

   1 From 1f307fd0fdca585d5c7c32963e8a8a6f38d8a78c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 23 Mar 2013 19:44:41 +0100
   4 Subject: [PATCH 129/137] MIPS: ralink: add support for periodic timer irq
   5
   6 Adds a driver for the periodic timer found on Ralink SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/ralink/Makefile |    2 +-
  11  arch/mips/ralink/timer.c  |  192 +++++++++++++++++++++++++++++++++++++++++++++
  12  2 files changed, 193 insertions(+), 1 deletion(-)
  13  create mode 100644 arch/mips/ralink/timer.c
  14
  15 --- a/arch/mips/ralink/Makefile
  16 +++ b/arch/mips/ralink/Makefile
  17 @@ -6,7 +6,7 @@
  18  # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  19  # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  20
  21 -obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
  22 +obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
  23
  24  obj-$(CONFIG_SOC_RT288X) += rt288x.o
  25  obj-$(CONFIG_SOC_RT305X) += rt305x.o
  26 --- /dev/null
  27 +++ b/arch/mips/ralink/timer.c
  28 @@ -0,0 +1,192 @@
  29 +/*
  30 + * This program is free software; you can redistribute it and/or modify it
  31 + * under the terms of the GNU General Public License version 2 as published
  32 + * by the Free Software Foundation.
  33 + *
  34 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  35 +*/
  36 +
  37 +#include <linux/module.h>
  38 +#include <linux/platform_device.h>
  39 +#include <linux/interrupt.h>
  40 +#include <linux/timer.h>
  41 +#include <linux/of_gpio.h>
  42 +#include <linux/clk.h>
  43 +
  44 +#include <asm/mach-ralink/ralink_regs.h>
  45 +
  46 +#define TIMER_REG_TMRSTAT              0x00
  47 +#define TIMER_REG_TMR0LOAD             0x10
  48 +#define TIMER_REG_TMR0CTL              0x18
  49 +
  50 +#define TMRSTAT_TMR0INT                        BIT(0)
  51 +
  52 +#define TMR0CTL_ENABLE                 BIT(7)
  53 +#define TMR0CTL_MODE_PERIODIC          BIT(4)
  54 +#define TMR0CTL_PRESCALER              1
  55 +#define TMR0CTL_PRESCALE_VAL           (0xf - TMR0CTL_PRESCALER)
  56 +#define TMR0CTL_PRESCALE_DIV           (65536 / BIT(TMR0CTL_PRESCALER))
  57 +
  58 +struct rt_timer {
  59 +       struct device   *dev;
  60 +       void __iomem    *membase;
  61 +       int             irq;
  62 +       unsigned long   timer_freq;
  63 +       unsigned long   timer_div;
  64 +};
  65 +
  66 +static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
  67 +{
  68 +       __raw_writel(val, rt->membase + reg);
  69 +}
  70 +
  71 +static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
  72 +{
  73 +       return __raw_readl(rt->membase + reg);
  74 +}
  75 +
  76 +static irqreturn_t rt_timer_irq(int irq, void *_rt)
  77 +{
  78 +       struct rt_timer *rt =  (struct rt_timer *) _rt;
  79 +
  80 +       rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
  81 +       rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
  82 +
  83 +       return IRQ_HANDLED;
  84 +}
  85 +
  86 +
  87 +static int rt_timer_request(struct rt_timer *rt)
  88 +{
  89 +       int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
  90 +                                               dev_name(rt->dev), rt);
  91 +       if (err) {
  92 +               dev_err(rt->dev, "failed to request irq\n");
  93 +       } else {
  94 +               u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
  95 +               rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
  96 +       }
  97 +       return err;
  98 +}
  99 +
 100 +static void rt_timer_free(struct rt_timer *rt)
 101 +{
 102 +       free_irq(rt->irq, rt);
 103 +}
 104 +
 105 +static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
 106 +{
 107 +       if (rt->timer_freq < divisor)
 108 +               rt->timer_div = rt->timer_freq;
 109 +       else
 110 +               rt->timer_div = divisor;
 111 +
 112 +       rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
 113 +
 114 +       return 0;
 115 +}
 116 +
 117 +static int rt_timer_enable(struct rt_timer *rt)
 118 +{
 119 +       u32 t;
 120 +
 121 +       rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
 122 +
 123 +       t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
 124 +       t |= TMR0CTL_ENABLE;
 125 +       rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
 126 +
 127 +       return 0;
 128 +}
 129 +
 130 +static void rt_timer_disable(struct rt_timer *rt)
 131 +{
 132 +       u32 t;
 133 +
 134 +       t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
 135 +       t &= ~TMR0CTL_ENABLE;
 136 +       rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
 137 +}
 138 +
 139 +static int rt_timer_probe(struct platform_device *pdev)
 140 +{
 141 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 142 +       struct rt_timer *rt;
 143 +       struct clk *clk;
 144 +
 145 +       if (!res) {
 146 +               dev_err(&pdev->dev, "no memory resource found\n");
 147 +               return -EINVAL;
 148 +       }
 149 +
 150 +       rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
 151 +       if (!rt) {
 152 +               dev_err(&pdev->dev, "failed to allocate memory\n");
 153 +               return -ENOMEM;
 154 +       }
 155 +
 156 +       rt->irq = platform_get_irq(pdev, 0);
 157 +       if (!rt->irq) {
 158 +               dev_err(&pdev->dev, "failed to load irq\n");
 159 +               return -ENOENT;
 160 +       }
 161 +
 162 +       rt->membase = devm_request_and_ioremap(&pdev->dev, res);
 163 +       if (!rt->membase) {
 164 +               dev_err(&pdev->dev, "failed to ioremap\n");
 165 +               return -ENOMEM;
 166 +       }
 167 +
 168 +       clk = devm_clk_get(&pdev->dev, NULL);
 169 +       if (IS_ERR(clk)) {
 170 +               dev_err(&pdev->dev, "failed get clock rate\n");
 171 +               return PTR_ERR(clk);
 172 +       }
 173 +
 174 +       rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
 175 +       if (!rt->timer_freq)
 176 +               return -EINVAL;
 177 +
 178 +       rt->dev = &pdev->dev;
 179 +       platform_set_drvdata(pdev, rt);
 180 +
 181 +       rt_timer_request(rt);
 182 +       rt_timer_config(rt, 2);
 183 +       rt_timer_enable(rt);
 184 +
 185 +       dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
 186 +
 187 +       return 0;
 188 +}
 189 +
 190 +static int rt_timer_remove(struct platform_device *pdev)
 191 +{
 192 +       struct rt_timer *rt = platform_get_drvdata(pdev);
 193 +
 194 +       rt_timer_disable(rt);
 195 +       rt_timer_free(rt);
 196 +
 197 +       return 0;
 198 +}
 199 +
 200 +static const struct of_device_id rt_timer_match[] = {
 201 +       { .compatible = "ralink,rt2880-timer" },
 202 +       {},
 203 +};
 204 +MODULE_DEVICE_TABLE(of, rt_timer_match);
 205 +
 206 +static struct platform_driver rt_timer_driver = {
 207 +       .probe = rt_timer_probe,
 208 +       .remove = rt_timer_remove,
 209 +       .driver = {
 210 +               .name           = "rt-timer",
 211 +               .owner          = THIS_MODULE,
 212 +               .of_match_table = rt_timer_match
 213 +       },
 214 +};
 215 +
 216 +module_platform_driver(rt_timer_driver);
 217 +
 218 +MODULE_DESCRIPTION("Ralink RT2880 timer");
 219 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
 220 +MODULE_LICENSE("GPL");