target/linux/ramips/patches-3.8/0117-DT-MIPS-ralink-clean-up-RT3050-dtsi-and-dts-file.patch

   1 From 7a30e00a278fe94ac8e42d0967ffde99d1ab74ee Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:47:07 +0100
   4 Subject: [PATCH 117/137] DT: MIPS: ralink: clean up RT3050 dtsi and dts file
   5
   6 * remove nodes for cores whose drivers are not upstream yet
   7 * add compat string for an additional soc
   8 * fix a whitespace error
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Acked-by: Grant Likely <grant.likely@secretlab.ca>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5186/
  13 ---
  14  arch/mips/ralink/dts/rt3050.dtsi     |   52 ++--------------------------------
  15  arch/mips/ralink/dts/rt3052_eval.dts |   10 ++-----
  16  2 files changed, 4 insertions(+), 58 deletions(-)
  17
  18 --- a/arch/mips/ralink/dts/rt3050.dtsi
  19 +++ b/arch/mips/ralink/dts/rt3050.dtsi
  20 @@ -1,7 +1,7 @@
  21  / {
  22         #address-cells = <1>;
  23         #size-cells = <1>;
  24 -       compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
  25 +       compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
  26
  27         cpus {
  28                 cpu@0 {
  29 @@ -9,10 +9,6 @@
  30                 };
  31         };
  32
  33 -       chosen {
  34 -               bootargs = "console=ttyS0,57600 init=/init";
  35 -       };
  36 -
  37         cpuintc: cpuintc@0 {
  38                 #address-cells = <0>;
  39                 #interrupt-cells = <1>;
  40 @@ -23,7 +19,7 @@
  41         palmbus@10000000 {
  42                 compatible = "palmbus";
  43                 reg = <0x10000000 0x200000>;
  44 -                ranges = <0x0 0x10000000 0x1FFFFF>;
  45 +               ranges = <0x0 0x10000000 0x1FFFFF>;
  46
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49 @@ -33,11 +29,6 @@
  50                         reg = <0x0 0x100>;
  51                 };
  52
  53 -               timer@100 {
  54 -                       compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
  55 -                       reg = <0x100 0x100>;
  56 -               };
  57 -
  58                 intc: intc@200 {
  59                         compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
  60                         reg = <0x200 0x100>;
  61 @@ -54,45 +45,6 @@
  62                         reg = <0x300 0x100>;
  63                 };
  64
  65 -               gpio0: gpio@600 {
  66 -                       compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
  67 -                       reg = <0x600 0x34>;
  68 -
  69 -                       gpio-controller;
  70 -                       #gpio-cells = <2>;
  71 -
  72 -                       ralink,ngpio = <24>;
  73 -                       ralink,regs = [ 00 04 08 0c
  74 -                                       20 24 28 2c
  75 -                                       30 34 ];
  76 -               };
  77 -
  78 -               gpio1: gpio@638 {
  79 -                       compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
  80 -                       reg = <0x638 0x24>;
  81 -
  82 -                       gpio-controller;
  83 -                       #gpio-cells = <2>;
  84 -
  85 -                       ralink,ngpio = <16>;
  86 -                       ralink,regs = [ 00 04 08 0c
  87 -                                       10 14 18 1c
  88 -                                       20 24 ];
  89 -               };
  90 -
  91 -               gpio2: gpio@660 {
  92 -                       compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
  93 -                       reg = <0x660 0x24>;
  94 -
  95 -                       gpio-controller;
  96 -                       #gpio-cells = <2>;
  97 -
  98 -                       ralink,ngpio = <12>;
  99 -                       ralink,regs = [ 00 04 08 0c
 100 -                                       10 14 18 1c
 101 -                                       20 24 ];
 102 -               };
 103 -
 104                 uartlite@c00 {
 105                         compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
 106                         reg = <0xc00 0x100>;
 107 --- a/arch/mips/ralink/dts/rt3052_eval.dts
 108 +++ b/arch/mips/ralink/dts/rt3052_eval.dts
 109 @@ -3,8 +3,6 @@
 110  /include/ "rt3050.dtsi"
 111
 112  / {
 113 -       #address-cells = <1>;
 114 -       #size-cells = <1>;
 115         compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
 116         model = "Ralink RT3052 evaluation board";
 117