target/linux/ramips/patches-3.8/0072-NET-MIPS-add-ralink-SoC-ethernet-driver.patch

   1 From 34564578e57bd2bffddbd5f463c55db4a220f2a0 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 20 Jun 2013 18:52:00 +0200
   4 Subject: [PATCH 72/79] NET: MIPS: add ralink SoC ethernet driver
   5
   6 Add support for Ralink FE and ESW.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
  11  arch/mips/ralink/rt305x.c                          |    1 +
  12  drivers/net/ethernet/Kconfig                       |    1 +
  13  drivers/net/ethernet/Makefile                      |    1 +
  14  drivers/net/ethernet/ralink/Kconfig                |   31 +
  15  drivers/net/ethernet/ralink/Makefile               |   18 +
  16  drivers/net/ethernet/ralink/esw_rt3052.c           | 1463 ++++++++++++++++++++
  17  drivers/net/ethernet/ralink/esw_rt3052.h           |   32 +
  18  drivers/net/ethernet/ralink/gsw_mt7620a.c          | 1027 ++++++++++++++
  19  drivers/net/ethernet/ralink/gsw_mt7620a.h          |   29 +
  20  drivers/net/ethernet/ralink/mdio.c                 |  245 ++++
  21  drivers/net/ethernet/ralink/mdio.h                 |   29 +
  22  drivers/net/ethernet/ralink/mdio_rt2880.c          |  163 +++
  23  drivers/net/ethernet/ralink/mdio_rt2880.h          |   25 +
  24  drivers/net/ethernet/ralink/ralink_soc_eth.c       |  759 ++++++++++
  25  drivers/net/ethernet/ralink/ralink_soc_eth.h       |  372 +++++
  26  drivers/net/ethernet/ralink/soc_mt7620.c           |  111 ++
  27  drivers/net/ethernet/ralink/soc_rt2880.c           |   51 +
  28  drivers/net/ethernet/ralink/soc_rt305x.c           |  102 ++
  29  drivers/net/ethernet/ralink/soc_rt3883.c           |   59 +
  30  20 files changed, 4546 insertions(+)
  31  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  32  create mode 100644 drivers/net/ethernet/ralink/Kconfig
  33  create mode 100644 drivers/net/ethernet/ralink/Makefile
  34  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
  35  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
  36  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
  37  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
  38  create mode 100644 drivers/net/ethernet/ralink/mdio.c
  39  create mode 100644 drivers/net/ethernet/ralink/mdio.h
  40  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
  41  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
  42  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
  43  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
  44  create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
  45  create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
  46  create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
  47  create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
  48
  49 diff --git a/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  50 new file mode 100644
  51 index 0000000..2098c5c
  52 --- /dev/null
  53 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  54 @@ -0,0 +1,27 @@
  55 +/*
  56 + *  Ralink RT305x SoC platform device registration
  57 + *
  58 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  59 + *
  60 + *  This program is free software; you can redistribute it and/or modify it
  61 + *  under the terms of the GNU General Public License version 2 as published
  62 + *  by the Free Software Foundation.
  63 + */
  64 +
  65 +#ifndef _RT305X_ESW_PLATFORM_H
  66 +#define _RT305X_ESW_PLATFORM_H
  67 +
  68 +enum {
  69 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
  70 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
  71 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
  72 +};
  73 +
  74 +struct rt305x_esw_platform_data
  75 +{
  76 +       u8 vlan_config;
  77 +       u32 reg_initval_fct2;
  78 +       u32 reg_initval_fpa2;
  79 +};
  80 +
  81 +#endif /* _RT305X_ESW_PLATFORM_H */
  82 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
  83 index ca7ee3a..1a6b458 100644
  84 --- a/arch/mips/ralink/rt305x.c
  85 +++ b/arch/mips/ralink/rt305x.c
  86 @@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
  87         }
  88
  89         ralink_clk_add("cpu", cpu_rate);
  90 +       ralink_clk_add("sys", sys_rate);
  91         ralink_clk_add("10000b00.spi", sys_rate);
  92         ralink_clk_add("10000100.timer", wdt_rate);
  93         ralink_clk_add("10000120.watchdog", wdt_rate);
  94 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
  95 index e4ff389..08c3c93 100644
  96 --- a/drivers/net/ethernet/Kconfig
  97 +++ b/drivers/net/ethernet/Kconfig
  98 @@ -137,6 +137,7 @@ source "drivers/net/ethernet/pasemi/Kconfig"
  99  source "drivers/net/ethernet/qlogic/Kconfig"
 100  source "drivers/net/ethernet/racal/Kconfig"
 101  source "drivers/net/ethernet/realtek/Kconfig"
 102 +source "drivers/net/ethernet/ralink/Kconfig"
 103  source "drivers/net/ethernet/renesas/Kconfig"
 104  source "drivers/net/ethernet/rdc/Kconfig"
 105
 106 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
 107 index d447307..f6bffb1 100644
 108 --- a/drivers/net/ethernet/Makefile
 109 +++ b/drivers/net/ethernet/Makefile
 110 @@ -55,6 +55,7 @@ obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
 111  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
 112  obj-$(CONFIG_NET_VENDOR_RACAL) += racal/
 113  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
 114 +obj-$(CONFIG_NET_RALINK) += ralink/
 115  obj-$(CONFIG_SH_ETH) += renesas/
 116  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
 117  obj-$(CONFIG_S6GMAC) += s6gmac.o
 118 diff --git a/drivers/net/ethernet/ralink/Kconfig b/drivers/net/ethernet/ralink/Kconfig
 119 new file mode 100644
 120 index 0000000..ca2c9ad
 121 --- /dev/null
 122 +++ b/drivers/net/ethernet/ralink/Kconfig
 123 @@ -0,0 +1,31 @@
 124 +config NET_RALINK
 125 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
 126 +       depends on RALINK
 127 +       help
 128 +         This driver supports the ethernet mac inside the ralink wisocs
 129 +
 130 +if NET_RALINK
 131 +
 132 +config NET_RALINK_MDIO
 133 +       def_bool NET_RALINK
 134 +       depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
 135 +       select PHYLIB
 136 +
 137 +config NET_RALINK_MDIO_RT2880
 138 +       def_bool NET_RALINK
 139 +       depends on (SOC_RT288X || SOC_RT3883)
 140 +       select NET_RALINK_MDIO
 141 +
 142 +config NET_RALINK_ESW_RT3052
 143 +       def_bool NET_RALINK
 144 +       depends on SOC_RT305X
 145 +       select PHYLIB
 146 +       select SWCONFIG
 147 +
 148 +config NET_RALINK_GSW_MT7620
 149 +       def_bool NET_RALINK
 150 +       depends on SOC_MT7620
 151 +       select NET_RALINK_MDIO
 152 +       select PHYLIB
 153 +       select SWCONFIG
 154 +endif
 155 diff --git a/drivers/net/ethernet/ralink/Makefile b/drivers/net/ethernet/ralink/Makefile
 156 new file mode 100644
 157 index 0000000..a38fa21
 158 --- /dev/null
 159 +++ b/drivers/net/ethernet/ralink/Makefile
 160 @@ -0,0 +1,18 @@
 161 +#
 162 +# Makefile for the Ralink SoCs built-in ethernet macs
 163 +#
 164 +
 165 +ralink-eth-y                                   += ralink_soc_eth.o
 166 +
 167 +ralink-eth-$(CONFIG_NET_RALINK_MDIO)           += mdio.o
 168 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)    += mdio_rt2880.o
 169 +
 170 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052)     += esw_rt3052.o
 171 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620)     += gsw_mt7620a.o
 172 +
 173 +ralink-eth-$(CONFIG_SOC_RT288X)                        += soc_rt2880.o
 174 +ralink-eth-$(CONFIG_SOC_RT305X)                        += soc_rt305x.o
 175 +ralink-eth-$(CONFIG_SOC_RT3883)                        += soc_rt3883.o
 176 +ralink-eth-$(CONFIG_SOC_MT7620)                        += soc_mt7620.o
 177 +
 178 +obj-$(CONFIG_NET_RALINK)                       += ralink-eth.o
 179 diff --git a/drivers/net/ethernet/ralink/esw_rt3052.c b/drivers/net/ethernet/ralink/esw_rt3052.c
 180 new file mode 100644
 181 index 0000000..b937062
 182 --- /dev/null
 183 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
 184 @@ -0,0 +1,1463 @@
 185 +/*
 186 + *   This program is free software; you can redistribute it and/or modify
 187 + *   it under the terms of the GNU General Public License as published by
 188 + *   the Free Software Foundation; version 2 of the License
 189 + *
 190 + *   This program is distributed in the hope that it will be useful,
 191 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 192 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 193 + *   GNU General Public License for more details.
 194 + *
 195 + *   You should have received a copy of the GNU General Public License
 196 + *   along with this program; if not, write to the Free Software
 197 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 198 + *
 199 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
 200 + */
 201 +
 202 +#include <linux/module.h>
 203 +#include <linux/kernel.h>
 204 +#include <linux/types.h>
 205 +#include <linux/dma-mapping.h>
 206 +#include <linux/init.h>
 207 +#include <linux/skbuff.h>
 208 +#include <linux/etherdevice.h>
 209 +#include <linux/ethtool.h>
 210 +#include <linux/platform_device.h>
 211 +#include <linux/of_device.h>
 212 +#include <linux/clk.h>
 213 +#include <linux/of_net.h>
 214 +#include <linux/of_mdio.h>
 215 +
 216 +#include <asm/mach-ralink/ralink_regs.h>
 217 +
 218 +#include "ralink_soc_eth.h"
 219 +
 220 +#include <linux/ioport.h>
 221 +#include <linux/switch.h>
 222 +#include <linux/mii.h>
 223 +
 224 +#include <ralink_regs.h>
 225 +#include <asm/mach-ralink/rt305x.h>
 226 +#include <asm/mach-ralink/rt305x_esw_platform.h>
 227 +
 228 +/*
 229 + * HW limitations for this switch:
 230 + * - No large frame support (PKT_MAX_LEN at most 1536)
 231 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
 232 + *   though this might be possible using the undocumented PPE.
 233 + */
 234 +
 235 +#define RT305X_ESW_REG_ISR             0x00
 236 +#define RT305X_ESW_REG_IMR             0x04
 237 +#define RT305X_ESW_REG_FCT0            0x08
 238 +#define RT305X_ESW_REG_PFC1            0x14
 239 +#define RT305X_ESW_REG_ATS             0x24
 240 +#define RT305X_ESW_REG_ATS0            0x28
 241 +#define RT305X_ESW_REG_ATS1            0x2c
 242 +#define RT305X_ESW_REG_ATS2            0x30
 243 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 244 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 245 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 246 +#define RT305X_ESW_REG_POA             0x80
 247 +#define RT305X_ESW_REG_FPA             0x84
 248 +#define RT305X_ESW_REG_SOCPC           0x8c
 249 +#define RT305X_ESW_REG_POC0            0x90
 250 +#define RT305X_ESW_REG_POC1            0x94
 251 +#define RT305X_ESW_REG_POC2            0x98
 252 +#define RT305X_ESW_REG_SGC             0x9c
 253 +#define RT305X_ESW_REG_STRT            0xa0
 254 +#define RT305X_ESW_REG_PCR0            0xc0
 255 +#define RT305X_ESW_REG_PCR1            0xc4
 256 +#define RT305X_ESW_REG_FPA2            0xc8
 257 +#define RT305X_ESW_REG_FCT2            0xcc
 258 +#define RT305X_ESW_REG_SGC2            0xe4
 259 +#define RT305X_ESW_REG_P0LED           0xa4
 260 +#define RT305X_ESW_REG_P1LED           0xa8
 261 +#define RT305X_ESW_REG_P2LED           0xac
 262 +#define RT305X_ESW_REG_P3LED           0xb0
 263 +#define RT305X_ESW_REG_P4LED           0xb4
 264 +#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
 265 +#define RT305X_ESW_REG_P1PC            0xec
 266 +#define RT305X_ESW_REG_P2PC            0xf0
 267 +#define RT305X_ESW_REG_P3PC            0xf4
 268 +#define RT305X_ESW_REG_P4PC            0xf8
 269 +#define RT305X_ESW_REG_P5PC            0xfc
 270 +
 271 +#define RT305X_ESW_LED_LINK            0
 272 +#define RT305X_ESW_LED_100M            1
 273 +#define RT305X_ESW_LED_DUPLEX          2
 274 +#define RT305X_ESW_LED_ACTIVITY                3
 275 +#define RT305X_ESW_LED_COLLISION       4
 276 +#define RT305X_ESW_LED_LINKACT         5
 277 +#define RT305X_ESW_LED_DUPLCOLL                6
 278 +#define RT305X_ESW_LED_10MACT          7
 279 +#define RT305X_ESW_LED_100MACT         8
 280 +/* Additional led states not in datasheet: */
 281 +#define RT305X_ESW_LED_BLINK           10
 282 +#define RT305X_ESW_LED_ON              12
 283 +
 284 +#define RT305X_ESW_LINK_S              25
 285 +#define RT305X_ESW_DUPLEX_S            9
 286 +#define RT305X_ESW_SPD_S               0
 287 +
 288 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
 289 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
 290 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
 291 +
 292 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
 293 +
 294 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
 295 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 296 +
 297 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
 298 +#define RT305X_ESW_PVIDC_PVID_S                12
 299 +
 300 +#define RT305X_ESW_VLANI_VID_M         0xfff
 301 +#define RT305X_ESW_VLANI_VID_S         12
 302 +
 303 +#define RT305X_ESW_VMSC_MSC_M          0xff
 304 +#define RT305X_ESW_VMSC_MSC_S          8
 305 +
 306 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
 307 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
 308 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
 309 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
 310 +
 311 +#define RT305X_ESW_POC0_EN_BP_S                0
 312 +#define RT305X_ESW_POC0_EN_FC_S                8
 313 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
 314 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
 315 +#define RT305X_ESW_POC0_DIS_PORT_S     23
 316 +
 317 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
 318 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
 319 +#define RT305X_ESW_POC2_ENAGING_S      8
 320 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
 321 +
 322 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
 323 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
 324 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
 325 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
 326 +
 327 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
 328 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
 329 +#define RT305X_ESW_PFC1_EN_TOS_S       24
 330 +
 331 +#define RT305X_ESW_VLAN_NONE           0xfff
 332 +
 333 +#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
 334 +#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
 335 +
 336 +#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
 337 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
 338 +
 339 +#define RT305X_ESW_POA_LINK_MASK       0x1f
 340 +#define RT305X_ESW_POA_LINK_SHIFT      25
 341 +
 342 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
 343 +#define RT305X_ESW_PORT0               0
 344 +#define RT305X_ESW_PORT1               1
 345 +#define RT305X_ESW_PORT2               2
 346 +#define RT305X_ESW_PORT3               3
 347 +#define RT305X_ESW_PORT4               4
 348 +#define RT305X_ESW_PORT5               5
 349 +#define RT305X_ESW_PORT6               6
 350 +
 351 +#define RT305X_ESW_PORTS_NONE          0
 352 +
 353 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
 354 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
 355 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
 356 +
 357 +#define RT305X_ESW_PORTS_INTERNAL                                      \
 358 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 359 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 360 +                BIT(RT305X_ESW_PORT4))
 361 +
 362 +#define RT305X_ESW_PORTS_NOCPU                                         \
 363 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 364 +
 365 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
 366 +
 367 +#define RT305X_ESW_PORTS_ALL                                           \
 368 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 369 +
 370 +#define RT305X_ESW_NUM_VLANS           16
 371 +#define RT305X_ESW_NUM_VIDS            4096
 372 +#define RT305X_ESW_NUM_PORTS           7
 373 +#define RT305X_ESW_NUM_LANWAN          6
 374 +#define RT305X_ESW_NUM_LEDS            5
 375 +
 376 +#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
 377 +#define RT5350_EWS_REG_LED_POLARITY    0x168
 378 +#define RT5350_RESET_EPHY              BIT(24)
 379 +#define SYSC_REG_RESET_CTRL            0x34
 380 +
 381 +enum {
 382 +       /* Global attributes. */
 383 +       RT305X_ESW_ATTR_ENABLE_VLAN,
 384 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 385 +       RT305X_ESW_ATTR_BC_STATUS,
 386 +       RT305X_ESW_ATTR_LED_FREQ,
 387 +       /* Port attributes. */
 388 +       RT305X_ESW_ATTR_PORT_DISABLE,
 389 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
 390 +       RT305X_ESW_ATTR_PORT_UNTAG,
 391 +       RT305X_ESW_ATTR_PORT_LED,
 392 +       RT305X_ESW_ATTR_PORT_LAN,
 393 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
 394 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
 395 +       RT5350_ESW_ATTR_PORT_TR_BAD,
 396 +       RT5350_ESW_ATTR_PORT_TR_GOOD,
 397 +};
 398 +
 399 +struct esw_port {
 400 +       bool    disable;
 401 +       bool    doubletag;
 402 +       bool    untag;
 403 +       u8      led;
 404 +       u16     pvid;
 405 +};
 406 +
 407 +struct esw_vlan {
 408 +       u8      ports;
 409 +       u16     vid;
 410 +};
 411 +
 412 +struct rt305x_esw {
 413 +       struct device           *dev;
 414 +       void __iomem            *base;
 415 +       int                     irq;
 416 +       const struct rt305x_esw_platform_data *pdata;
 417 +       /* Protects against concurrent register rmw operations. */
 418 +       spinlock_t              reg_rw_lock;
 419 +
 420 +       unsigned char           port_map;
 421 +       unsigned int            reg_initval_fct2;
 422 +       unsigned int            reg_initval_fpa2;
 423 +       unsigned int            reg_led_polarity;
 424 +
 425 +
 426 +       struct switch_dev       swdev;
 427 +       bool                    global_vlan_enable;
 428 +       bool                    alt_vlan_disable;
 429 +       int                     bc_storm_protect;
 430 +       int                     led_frequency;
 431 +       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 432 +       struct esw_port ports[RT305X_ESW_NUM_PORTS];
 433 +
 434 +};
 435 +
 436 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
 437 +{
 438 +       __raw_writel(val, esw->base + reg);
 439 +}
 440 +
 441 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
 442 +{
 443 +       return __raw_readl(esw->base + reg);
 444 +}
 445 +
 446 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 447 +                  unsigned long val)
 448 +{
 449 +       unsigned long t;
 450 +
 451 +       t = __raw_readl(esw->base + reg) & ~mask;
 452 +       __raw_writel(t | val, esw->base + reg);
 453 +}
 454 +
 455 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 456 +              unsigned long val)
 457 +{
 458 +       unsigned long flags;
 459 +
 460 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
 461 +       esw_rmw_raw(esw, reg, mask, val);
 462 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 463 +}
 464 +
 465 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 466 +                u32 write_data)
 467 +{
 468 +       unsigned long t_start = jiffies;
 469 +       int ret = 0;
 470 +
 471 +       while (1) {
 472 +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
 473 +                     RT305X_ESW_PCR1_WT_DONE))
 474 +                       break;
 475 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 476 +                       ret = 1;
 477 +                       goto out;
 478 +               }
 479 +       }
 480 +
 481 +       write_data &= 0xffff;
 482 +       esw_w32(esw,
 483 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 484 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 485 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 486 +                     RT305X_ESW_REG_PCR0);
 487 +
 488 +       t_start = jiffies;
 489 +       while (1) {
 490 +               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
 491 +                   RT305X_ESW_PCR1_WT_DONE)
 492 +                       break;
 493 +
 494 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 495 +                       ret = 1;
 496 +                       break;
 497 +               }
 498 +       }
 499 +out:
 500 +       if (ret)
 501 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 502 +       return ret;
 503 +}
 504 +
 505 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 506 +{
 507 +       unsigned s;
 508 +       unsigned val;
 509 +
 510 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 511 +       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 512 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 513 +
 514 +       return val;
 515 +}
 516 +
 517 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 518 +{
 519 +       unsigned s;
 520 +
 521 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 522 +       esw_rmw(esw,
 523 +                      RT305X_ESW_REG_VLANI(vlan / 2),
 524 +                      RT305X_ESW_VLANI_VID_M << s,
 525 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
 526 +}
 527 +
 528 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 529 +{
 530 +       unsigned s, val;
 531 +
 532 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 533 +       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
 534 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 535 +}
 536 +
 537 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 538 +{
 539 +       unsigned s;
 540 +
 541 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 542 +       esw_rmw(esw,
 543 +                      RT305X_ESW_REG_PVIDC(port / 2),
 544 +                      RT305X_ESW_PVIDC_PVID_M << s,
 545 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 546 +}
 547 +
 548 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 549 +{
 550 +       unsigned s, val;
 551 +
 552 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 553 +       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 554 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 555 +
 556 +       return val;
 557 +}
 558 +
 559 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 560 +{
 561 +       unsigned s;
 562 +
 563 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 564 +       esw_rmw(esw,
 565 +                      RT305X_ESW_REG_VMSC(vlan / 4),
 566 +                      RT305X_ESW_VMSC_MSC_M << s,
 567 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
 568 +}
 569 +
 570 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
 571 +{
 572 +       unsigned reg;
 573 +       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
 574 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
 575 +              RT305X_ESW_POC0_DIS_PORT_M;
 576 +}
 577 +
 578 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
 579 +{
 580 +       unsigned old_mask;
 581 +       unsigned enable_mask;
 582 +       unsigned changed;
 583 +       int i;
 584 +
 585 +       old_mask = esw_get_port_disable(esw);
 586 +       changed = old_mask ^ disable_mask;
 587 +       enable_mask = old_mask & disable_mask;
 588 +
 589 +       /* enable before writing to MII */
 590 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 591 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 592 +                       RT305X_ESW_POC0_DIS_PORT_S),
 593 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 594 +
 595 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
 596 +               if (!(changed & (1 << i)))
 597 +                       continue;
 598 +               if (disable_mask & (1 << i)) {
 599 +                       /* disable */
 600 +                       rt305x_mii_write(esw, i, MII_BMCR,
 601 +                                        BMCR_PDOWN);
 602 +               } else {
 603 +                       /* enable */
 604 +                       rt305x_mii_write(esw, i, MII_BMCR,
 605 +                                        BMCR_FULLDPLX |
 606 +                                        BMCR_ANENABLE |
 607 +                                        BMCR_ANRESTART |
 608 +                                        BMCR_SPEED100);
 609 +               }
 610 +       }
 611 +
 612 +       /* disable after writing to MII */
 613 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 614 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 615 +                       RT305X_ESW_POC0_DIS_PORT_S),
 616 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 617 +}
 618 +
 619 +static void esw_set_gsc(struct rt305x_esw *esw)
 620 +{
 621 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 622 +               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
 623 +               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
 624 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 625 +               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
 626 +               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
 627 +}
 628 +
 629 +static int esw_apply_config(struct switch_dev *dev);
 630 +
 631 +static void esw_hw_init(struct rt305x_esw *esw)
 632 +{
 633 +       int i;
 634 +       u8 port_disable = 0;
 635 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 636 +
 637 +       /* vodoo from original driver */
 638 +       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 639 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 640 +       /* Port priority 1 for all ports, vlan enabled. */
 641 +       esw_w32(esw, 0x00005555 |
 642 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 643 +                     RT305X_ESW_REG_PFC1);
 644 +
 645 +       /* Enable Back Pressure, and Flow Control */
 646 +       esw_w32(esw,
 647 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 648 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 649 +                     RT305X_ESW_REG_POC0);
 650 +
 651 +       /* Enable Aging, and VLAN TAG removal */
 652 +       esw_w32(esw,
 653 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 654 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 655 +                     RT305X_ESW_REG_POC2);
 656 +
 657 +       if (esw->reg_initval_fct2)
 658 +               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 659 +       else
 660 +               esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 661 +
 662 +       /*
 663 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
 664 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
 665 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
 666 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 667 +        * ports.
 668 +        */
 669 +       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 670 +
 671 +       /* Setup SoC Port control register */
 672 +       esw_w32(esw,
 673 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
 674 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 675 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 676 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 677 +                     RT305X_ESW_REG_SOCPC);
 678 +
 679 +       if (esw->reg_initval_fpa2)
 680 +               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 681 +       else
 682 +               esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 683 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
 684 +
 685 +       /* Force Link/Activity on ports */
 686 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 687 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 688 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 689 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 690 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 691 +
 692 +       /* Copy disabled port configuration from bootloader setup */
 693 +       port_disable = esw_get_port_disable(esw);
 694 +       for (i = 0; i < 6; i++)
 695 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 696 +
 697 +       if (soc_is_rt3352()) {
 698 +               /* reset EPHY */
 699 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 700 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 701 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 702 +
 703 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 704 +               for (i = 0; i < 5; i++) {
 705 +                       if (esw->ports[i].disable) {
 706 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 707 +                       } else {
 708 +                               rt305x_mii_write(esw, i, MII_BMCR,
 709 +                                        BMCR_FULLDPLX |
 710 +                                        BMCR_ANENABLE |
 711 +                                        BMCR_SPEED100);
 712 +                       }
 713 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 714 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 715 +                       /* TX100/TX10 AD/DA current bias */
 716 +                       rt305x_mii_write(esw, i, 29, 0x7016);
 717 +                       /* TX100 slew rate control */
 718 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 719 +               }
 720 +
 721 +               /* select global register */
 722 +               rt305x_mii_write(esw, 0, 31, 0x0);
 723 +               /* enlarge agcsel threshold 3 and threshold 2 */
 724 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 725 +               /* enlarge agcsel threshold 5 and threshold 4 */
 726 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 727 +               /* enlarge agcsel threshold  */
 728 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 729 +               rt305x_mii_write(esw, 0,12, 0x7eaa);
 730 +               /* longer TP_IDL tail length */
 731 +               rt305x_mii_write(esw, 0, 14, 0x65);
 732 +               /* increased squelch pulse count threshold. */
 733 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 734 +               /* set TX10 signal amplitude threshold to minimum */
 735 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 736 +               /* set squelch amplitude to higher threshold */
 737 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 738 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 739 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 740 +               /* set PLL/Receive bias current are calibrated */
 741 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 742 +               /* change PLL/Receive bias current to internal(RT3350) */
 743 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 744 +               /* change PLL bias current to internal(RT3052_MP3) */
 745 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 746 +               /* select local register */
 747 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 748 +       } else if (soc_is_rt5350()) {
 749 +               /* reset EPHY */
 750 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 751 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 752 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 753 +
 754 +               /* set the led polarity */
 755 +               esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
 756 +
 757 +               /* local registers */
 758 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 759 +               for (i = 0; i < 5; i++) {
 760 +                       if (esw->ports[i].disable) {
 761 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 762 +                       } else {
 763 +                               rt305x_mii_write(esw, i, MII_BMCR,
 764 +                                        BMCR_FULLDPLX |
 765 +                                        BMCR_ANENABLE |
 766 +                                        BMCR_SPEED100);
 767 +                       }
 768 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 769 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 770 +                       /* TX100/TX10 AD/DA current bias */
 771 +                       rt305x_mii_write(esw, i, 29, 0x7015);
 772 +                       /* TX100 slew rate control */
 773 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 774 +               }
 775 +
 776 +               /* global registers */
 777 +               rt305x_mii_write(esw, 0, 31, 0x0);
 778 +               /* enlarge agcsel threshold 3 and threshold 2 */
 779 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 780 +               /* enlarge agcsel threshold 5 and threshold 4 */
 781 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 782 +               /* enlarge agcsel threshold 6 */
 783 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 784 +               rt305x_mii_write(esw, 0, 12, 0x7eaa);
 785 +               /* longer TP_IDL tail length */
 786 +               rt305x_mii_write(esw, 0, 14, 0x65);
 787 +               /* increased squelch pulse count threshold. */
 788 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 789 +               /* set TX10 signal amplitude threshold to minimum */
 790 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 791 +               /* set squelch amplitude to higher threshold */
 792 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 793 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 794 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 795 +               /* set PLL/Receive bias current are calibrated */
 796 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 797 +               /* change PLL/Receive bias current to internal(RT3350) */
 798 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 799 +               /* change PLL bias current to internal(RT3052_MP3) */
 800 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 801 +               /* select local register */
 802 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 803 +       } else {
 804 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 805 +               for (i = 0; i < 5; i++) {
 806 +                       if (esw->ports[i].disable) {
 807 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 808 +                       } else {
 809 +                               rt305x_mii_write(esw, i, MII_BMCR,
 810 +                                        BMCR_FULLDPLX |
 811 +                                        BMCR_ANENABLE |
 812 +                                        BMCR_SPEED100);
 813 +                       }
 814 +                       /* TX10 waveform coefficient */
 815 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 816 +                       /* TX100/TX10 AD/DA current bias */
 817 +                       rt305x_mii_write(esw, i, 29, 0x7058);
 818 +                       /* TX100 slew rate control */
 819 +                       rt305x_mii_write(esw, i, 30, 0x0018);
 820 +               }
 821 +
 822 +               /* PHY IOT */
 823 +               /* select global register */
 824 +               rt305x_mii_write(esw, 0, 31, 0x0);
 825 +               /* tune TP_IDL tail and head waveform */
 826 +               rt305x_mii_write(esw, 0, 22, 0x052f);
 827 +               /* set TX10 signal amplitude threshold to minimum */
 828 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 829 +               /* set squelch amplitude to higher threshold */
 830 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 831 +               /* longer TP_IDL tail length */
 832 +               rt305x_mii_write(esw, 0, 14, 0x65);
 833 +               /* select local register */
 834 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 835 +       }
 836 +
 837 +       if (esw->port_map)
 838 +               port_map = esw->port_map;
 839 +       else
 840 +               port_map = RT305X_ESW_PMAP_LLLLLL;
 841 +
 842 +       /*
 843 +        * Unused HW feature, but still nice to be consistent here...
 844 +        * This is also exported to userspace ('lan' attribute) so it's
 845 +        * conveniently usable to decide which ports go into the wan vlan by
 846 +        * default.
 847 +        */
 848 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 849 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 850 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 851 +
 852 +       /* make the switch leds blink */
 853 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
 854 +               esw->ports[i].led = 0x05;
 855 +
 856 +       /* Apply the empty config. */
 857 +       esw_apply_config(&esw->swdev);
 858 +
 859 +       /* Only unmask the port change interrupt */
 860 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
 861 +}
 862 +
 863 +static irqreturn_t esw_interrupt(int irq, void *_esw)
 864 +{
 865 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
 866 +       u32 status;
 867 +
 868 +       status = esw_r32(esw, RT305X_ESW_REG_ISR);
 869 +       if (status & RT305X_ESW_PORT_ST_CHG) {
 870 +               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
 871 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
 872 +               link &= RT305X_ESW_POA_LINK_MASK;
 873 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
 874 +       }
 875 +       esw_w32(esw, status, RT305X_ESW_REG_ISR);
 876 +
 877 +       return IRQ_HANDLED;
 878 +}
 879 +
 880 +static int esw_apply_config(struct switch_dev *dev)
 881 +{
 882 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 883 +       int i;
 884 +       u8 disable = 0;
 885 +       u8 doubletag = 0;
 886 +       u8 en_vlan = 0;
 887 +       u8 untag = 0;
 888 +
 889 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 890 +               u32 vid, vmsc;
 891 +               if (esw->global_vlan_enable) {
 892 +                       vid = esw->vlans[i].vid;
 893 +                       vmsc = esw->vlans[i].ports;
 894 +               } else {
 895 +                       vid = RT305X_ESW_VLAN_NONE;
 896 +                       vmsc = RT305X_ESW_PORTS_NONE;
 897 +               }
 898 +               esw_set_vlan_id(esw, i, vid);
 899 +               esw_set_vmsc(esw, i, vmsc);
 900 +       }
 901 +
 902 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 903 +               u32 pvid;
 904 +               disable |= esw->ports[i].disable << i;
 905 +               if (esw->global_vlan_enable) {
 906 +                       doubletag |= esw->ports[i].doubletag << i;
 907 +                       en_vlan   |= 1                       << i;
 908 +                       untag     |= esw->ports[i].untag     << i;
 909 +                       pvid       = esw->ports[i].pvid;
 910 +               } else {
 911 +                       int x = esw->alt_vlan_disable ? 0 : 1;
 912 +                       doubletag |= x << i;
 913 +                       en_vlan   |= x << i;
 914 +                       untag     |= x << i;
 915 +                       pvid       = 0;
 916 +               }
 917 +               esw_set_pvid(esw, i, pvid);
 918 +               if (i < RT305X_ESW_NUM_LEDS)
 919 +                       esw_w32(esw, esw->ports[i].led,
 920 +                                     RT305X_ESW_REG_P0LED + 4*i);
 921 +       }
 922 +
 923 +       esw_set_gsc(esw);
 924 +       esw_set_port_disable(esw, disable);
 925 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 926 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 927 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
 928 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 929 +       esw_rmw(esw, RT305X_ESW_REG_PFC1,
 930 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 931 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 932 +       esw_rmw(esw, RT305X_ESW_REG_POC2,
 933 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 934 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
 935 +
 936 +       if (!esw->global_vlan_enable) {
 937 +               /*
 938 +                * Still need to put all ports into vlan 0 or they'll be
 939 +                * isolated.
 940 +                * NOTE: vlan 0 is special, no vlan tag is prepended
 941 +                */
 942 +               esw_set_vlan_id(esw, 0, 0);
 943 +               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 944 +       }
 945 +
 946 +       return 0;
 947 +}
 948 +
 949 +static int esw_reset_switch(struct switch_dev *dev)
 950 +{
 951 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 952 +
 953 +       esw->global_vlan_enable = 0;
 954 +       memset(esw->ports, 0, sizeof(esw->ports));
 955 +       memset(esw->vlans, 0, sizeof(esw->vlans));
 956 +       esw_hw_init(esw);
 957 +
 958 +       return 0;
 959 +}
 960 +
 961 +static int esw_get_vlan_enable(struct switch_dev *dev,
 962 +                          const struct switch_attr *attr,
 963 +                          struct switch_val *val)
 964 +{
 965 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 966 +
 967 +       val->value.i = esw->global_vlan_enable;
 968 +
 969 +       return 0;
 970 +}
 971 +
 972 +static int esw_set_vlan_enable(struct switch_dev *dev,
 973 +                          const struct switch_attr *attr,
 974 +                          struct switch_val *val)
 975 +{
 976 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 977 +
 978 +       esw->global_vlan_enable = val->value.i != 0;
 979 +
 980 +       return 0;
 981 +}
 982 +
 983 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
 984 +                               const struct switch_attr *attr,
 985 +                               struct switch_val *val)
 986 +{
 987 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 988 +
 989 +       val->value.i = esw->alt_vlan_disable;
 990 +
 991 +       return 0;
 992 +}
 993 +
 994 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
 995 +                               const struct switch_attr *attr,
 996 +                               struct switch_val *val)
 997 +{
 998 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 999 +
1000 +       esw->alt_vlan_disable = val->value.i != 0;
1001 +
1002 +       return 0;
1003 +}
1004 +
1005 +static int
1006 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1007 +                       const struct switch_attr *attr,
1008 +                       struct switch_val *val)
1009 +{
1010 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1011 +
1012 +       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1013 +
1014 +       return 0;
1015 +}
1016 +
1017 +static int
1018 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1019 +                       const struct switch_attr *attr,
1020 +                       struct switch_val *val)
1021 +{
1022 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1023 +
1024 +       val->value.i = esw->bc_storm_protect;
1025 +
1026 +       return 0;
1027 +}
1028 +
1029 +static int
1030 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1031 +                       const struct switch_attr *attr,
1032 +                       struct switch_val *val)
1033 +{
1034 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1035 +
1036 +       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1037 +
1038 +       return 0;
1039 +}
1040 +
1041 +static int
1042 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1043 +                       const struct switch_attr *attr,
1044 +                       struct switch_val *val)
1045 +{
1046 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1047 +
1048 +       val->value.i = esw->led_frequency;
1049 +
1050 +       return 0;
1051 +}
1052 +
1053 +static int esw_get_port_link(struct switch_dev *dev,
1054 +                        int port,
1055 +                        struct switch_port_link *link)
1056 +{
1057 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1058 +       u32 speed, poa;
1059 +
1060 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1061 +               return -EINVAL;
1062 +
1063 +       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1064 +
1065 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1066 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1067 +       if (port < RT305X_ESW_NUM_LEDS) {
1068 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
1069 +       } else {
1070 +               if (port == RT305X_ESW_NUM_PORTS - 1)
1071 +                       poa >>= 1;
1072 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
1073 +       }
1074 +       switch (speed) {
1075 +       case 0:
1076 +               link->speed = SWITCH_PORT_SPEED_10;
1077 +               break;
1078 +       case 1:
1079 +               link->speed = SWITCH_PORT_SPEED_100;
1080 +               break;
1081 +       case 2:
1082 +       case 3: /* forced gige speed can be 2 or 3 */
1083 +               link->speed = SWITCH_PORT_SPEED_1000;
1084 +               break;
1085 +       default:
1086 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1087 +               break;
1088 +       }
1089 +
1090 +       return 0;
1091 +}
1092 +
1093 +static int esw_get_port_bool(struct switch_dev *dev,
1094 +                        const struct switch_attr *attr,
1095 +                        struct switch_val *val)
1096 +{
1097 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1098 +       int idx = val->port_vlan;
1099 +       u32 x, reg, shift;
1100 +
1101 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1102 +               return -EINVAL;
1103 +
1104 +       switch (attr->id) {
1105 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1106 +               reg = RT305X_ESW_REG_POC0;
1107 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
1108 +               break;
1109 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1110 +               reg = RT305X_ESW_REG_SGC2;
1111 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1112 +               break;
1113 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1114 +               reg = RT305X_ESW_REG_POC2;
1115 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
1116 +               break;
1117 +       case RT305X_ESW_ATTR_PORT_LAN:
1118 +               reg = RT305X_ESW_REG_SGC2;
1119 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1120 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1121 +                       return -EINVAL;
1122 +               break;
1123 +       default:
1124 +               return -EINVAL;
1125 +       }
1126 +
1127 +       x = esw_r32(esw, reg);
1128 +       val->value.i = (x >> (idx + shift)) & 1;
1129 +
1130 +       return 0;
1131 +}
1132 +
1133 +static int esw_set_port_bool(struct switch_dev *dev,
1134 +                        const struct switch_attr *attr,
1135 +                        struct switch_val *val)
1136 +{
1137 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1138 +       int idx = val->port_vlan;
1139 +
1140 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1141 +           val->value.i < 0 || val->value.i > 1)
1142 +               return -EINVAL;
1143 +
1144 +       switch (attr->id) {
1145 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1146 +               esw->ports[idx].disable = val->value.i;
1147 +               break;
1148 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1149 +               esw->ports[idx].doubletag = val->value.i;
1150 +               break;
1151 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1152 +               esw->ports[idx].untag = val->value.i;
1153 +               break;
1154 +       default:
1155 +               return -EINVAL;
1156 +       }
1157 +
1158 +       return 0;
1159 +}
1160 +
1161 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1162 +                                const struct switch_attr *attr,
1163 +                                struct switch_val *val)
1164 +{
1165 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1166 +       int idx = val->port_vlan;
1167 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1168 +       u32 reg;
1169 +
1170 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1171 +               return -EINVAL;
1172 +       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1173 +       val->value.i = (reg >> shift) & 0xffff;
1174 +
1175 +       return 0;
1176 +}
1177 +
1178 +static int
1179 +esw_get_port_tr_badgood(struct switch_dev *dev,
1180 +                                const struct switch_attr *attr,
1181 +                                struct switch_val *val)
1182 +{
1183 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1184 +
1185 +       int idx = val->port_vlan;
1186 +       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1187 +       u32 reg;
1188 +
1189 +       if (!soc_is_rt5350())
1190 +               return -EINVAL;
1191 +
1192 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1193 +               return -EINVAL;
1194 +
1195 +       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1196 +       val->value.i = (reg >> shift) & 0xffff;
1197 +
1198 +       return 0;
1199 +}
1200 +
1201 +static int esw_get_port_led(struct switch_dev *dev,
1202 +                       const struct switch_attr *attr,
1203 +                       struct switch_val *val)
1204 +{
1205 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1206 +       int idx = val->port_vlan;
1207 +
1208 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1209 +           idx >= RT305X_ESW_NUM_LEDS)
1210 +               return -EINVAL;
1211 +
1212 +       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1213 +
1214 +       return 0;
1215 +}
1216 +
1217 +static int esw_set_port_led(struct switch_dev *dev,
1218 +                       const struct switch_attr *attr,
1219 +                       struct switch_val *val)
1220 +{
1221 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1222 +       int idx = val->port_vlan;
1223 +
1224 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1225 +               return -EINVAL;
1226 +
1227 +       esw->ports[idx].led = val->value.i;
1228 +
1229 +       return 0;
1230 +}
1231 +
1232 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1233 +{
1234 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1235 +
1236 +       if (port >= RT305X_ESW_NUM_PORTS)
1237 +               return -EINVAL;
1238 +
1239 +       *val = esw_get_pvid(esw, port);
1240 +
1241 +       return 0;
1242 +}
1243 +
1244 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1245 +{
1246 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1247 +
1248 +       if (port >= RT305X_ESW_NUM_PORTS)
1249 +               return -EINVAL;
1250 +
1251 +       esw->ports[port].pvid = val;
1252 +
1253 +       return 0;
1254 +}
1255 +
1256 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1257 +{
1258 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1259 +       u32 vmsc, poc2;
1260 +       int vlan_idx = -1;
1261 +       int i;
1262 +
1263 +       val->len = 0;
1264 +
1265 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1266 +               return -EINVAL;
1267 +
1268 +       /* valid vlan? */
1269 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1270 +               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1271 +                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1272 +                       vlan_idx = i;
1273 +                       break;
1274 +               }
1275 +       }
1276 +
1277 +       if (vlan_idx == -1)
1278 +               return -EINVAL;
1279 +
1280 +       vmsc = esw_get_vmsc(esw, vlan_idx);
1281 +       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1282 +
1283 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1284 +               struct switch_port *p;
1285 +               int port_mask = 1 << i;
1286 +
1287 +               if (!(vmsc & port_mask))
1288 +                       continue;
1289 +
1290 +               p = &val->value.ports[val->len++];
1291 +               p->id = i;
1292 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1293 +                       p->flags = 0;
1294 +               else
1295 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1296 +       }
1297 +
1298 +       return 0;
1299 +}
1300 +
1301 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1302 +{
1303 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1304 +       int ports;
1305 +       int vlan_idx = -1;
1306 +       int i;
1307 +
1308 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1309 +           val->len > RT305X_ESW_NUM_PORTS)
1310 +               return -EINVAL;
1311 +
1312 +       /* one of the already defined vlans? */
1313 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1314 +               if (esw->vlans[i].vid == val->port_vlan &&
1315 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1316 +                       vlan_idx = i;
1317 +                       break;
1318 +               }
1319 +       }
1320 +
1321 +       /* select a free slot */
1322 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1323 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1324 +                       vlan_idx = i;
1325 +       }
1326 +
1327 +       /* bail if all slots are in use */
1328 +       if (vlan_idx == -1)
1329 +               return -EINVAL;
1330 +
1331 +       ports = RT305X_ESW_PORTS_NONE;
1332 +       for (i = 0; i < val->len; i++) {
1333 +               struct switch_port *p = &val->value.ports[i];
1334 +               int port_mask = 1 << p->id;
1335 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1336 +
1337 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1338 +                       return -EINVAL;
1339 +
1340 +               ports |= port_mask;
1341 +               esw->ports[p->id].untag = untagged;
1342 +       }
1343 +       esw->vlans[vlan_idx].ports = ports;
1344 +       if (ports == RT305X_ESW_PORTS_NONE)
1345 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1346 +       else
1347 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1348 +
1349 +       return 0;
1350 +}
1351 +
1352 +static const struct switch_attr esw_global[] = {
1353 +       {
1354 +               .type = SWITCH_TYPE_INT,
1355 +               .name = "enable_vlan",
1356 +               .description = "VLAN mode (1:enabled)",
1357 +               .max = 1,
1358 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1359 +               .get = esw_get_vlan_enable,
1360 +               .set = esw_set_vlan_enable,
1361 +       },
1362 +       {
1363 +               .type = SWITCH_TYPE_INT,
1364 +               .name = "alternate_vlan_disable",
1365 +               .description = "Use en_vlan instead of doubletag to disable"
1366 +                               " VLAN mode",
1367 +               .max = 1,
1368 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1369 +               .get = esw_get_alt_vlan_disable,
1370 +               .set = esw_set_alt_vlan_disable,
1371 +       },
1372 +       {
1373 +               .type = SWITCH_TYPE_INT,
1374 +               .name = "bc_storm_protect",
1375 +               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1376 +               .max = 3,
1377 +               .id = RT305X_ESW_ATTR_BC_STATUS,
1378 +               .get = rt305x_esw_get_bc_status,
1379 +               .set = rt305x_esw_set_bc_status,
1380 +       },
1381 +       {
1382 +               .type = SWITCH_TYPE_INT,
1383 +               .name = "led_frequency",
1384 +               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1385 +               .max = 3,
1386 +               .id = RT305X_ESW_ATTR_LED_FREQ,
1387 +               .get = rt305x_esw_get_led_freq,
1388 +               .set = rt305x_esw_set_led_freq,
1389 +       }
1390 +};
1391 +
1392 +static const struct switch_attr esw_port[] = {
1393 +       {
1394 +               .type = SWITCH_TYPE_INT,
1395 +               .name = "disable",
1396 +               .description = "Port state (1:disabled)",
1397 +               .max = 1,
1398 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1399 +               .get = esw_get_port_bool,
1400 +               .set = esw_set_port_bool,
1401 +       },
1402 +       {
1403 +               .type = SWITCH_TYPE_INT,
1404 +               .name = "doubletag",
1405 +               .description = "Double tagging for incoming vlan packets "
1406 +                               "(1:enabled)",
1407 +               .max = 1,
1408 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1409 +               .get = esw_get_port_bool,
1410 +               .set = esw_set_port_bool,
1411 +       },
1412 +       {
1413 +               .type = SWITCH_TYPE_INT,
1414 +               .name = "untag",
1415 +               .description = "Untag (1:strip outgoing vlan tag)",
1416 +               .max = 1,
1417 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1418 +               .get = esw_get_port_bool,
1419 +               .set = esw_set_port_bool,
1420 +       },
1421 +       {
1422 +               .type = SWITCH_TYPE_INT,
1423 +               .name = "led",
1424 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1425 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1426 +                               " 8:100mact, 10:blink, 11:off, 12:on)",
1427 +               .max = 15,
1428 +               .id = RT305X_ESW_ATTR_PORT_LED,
1429 +               .get = esw_get_port_led,
1430 +               .set = esw_set_port_led,
1431 +       },
1432 +       {
1433 +               .type = SWITCH_TYPE_INT,
1434 +               .name = "lan",
1435 +               .description = "HW port group (0:wan, 1:lan)",
1436 +               .max = 1,
1437 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1438 +               .get = esw_get_port_bool,
1439 +       },
1440 +       {
1441 +               .type = SWITCH_TYPE_INT,
1442 +               .name = "recv_bad",
1443 +               .description = "Receive bad packet counter",
1444 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1445 +               .get = esw_get_port_recv_badgood,
1446 +       },
1447 +       {
1448 +               .type = SWITCH_TYPE_INT,
1449 +               .name = "recv_good",
1450 +               .description = "Receive good packet counter",
1451 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1452 +               .get = esw_get_port_recv_badgood,
1453 +       },
1454 +       {
1455 +               .type = SWITCH_TYPE_INT,
1456 +               .name = "tr_bad",
1457 +
1458 +               .description = "Transmit bad packet counter. rt5350 only",
1459 +               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1460 +               .get = esw_get_port_tr_badgood,
1461 +       },
1462 +       {
1463 +               .type = SWITCH_TYPE_INT,
1464 +               .name = "tr_good",
1465 +
1466 +               .description = "Transmit good packet counter. rt5350 only",
1467 +               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1468 +               .get = esw_get_port_tr_badgood,
1469 +       },
1470 +};
1471 +
1472 +static const struct switch_attr esw_vlan[] = {
1473 +};
1474 +
1475 +static const struct switch_dev_ops esw_ops = {
1476 +       .attr_global = {
1477 +               .attr = esw_global,
1478 +               .n_attr = ARRAY_SIZE(esw_global),
1479 +       },
1480 +       .attr_port = {
1481 +               .attr = esw_port,
1482 +               .n_attr = ARRAY_SIZE(esw_port),
1483 +       },
1484 +       .attr_vlan = {
1485 +               .attr = esw_vlan,
1486 +               .n_attr = ARRAY_SIZE(esw_vlan),
1487 +       },
1488 +       .get_vlan_ports = esw_get_vlan_ports,
1489 +       .set_vlan_ports = esw_set_vlan_ports,
1490 +       .get_port_pvid = esw_get_port_pvid,
1491 +       .set_port_pvid = esw_set_port_pvid,
1492 +       .get_port_link = esw_get_port_link,
1493 +       .apply_config = esw_apply_config,
1494 +       .reset_switch = esw_reset_switch,
1495 +};
1496 +
1497 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1498 +       /* All ports are LAN ports. */
1499 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1500 +       .reg_initval_fct2       = 0x00d6500c,
1501 +       /*
1502 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1503 +        * turbo mii off, rgmi 3.3v off
1504 +        * port5: disabled
1505 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1506 +        */
1507 +       .reg_initval_fpa2       = 0x3f502b28,
1508 +};
1509 +
1510 +static const struct of_device_id ralink_esw_match[] = {
1511 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1512 +       {},
1513 +};
1514 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1515 +
1516 +static int esw_probe(struct platform_device *pdev)
1517 +{
1518 +       struct device_node *np = pdev->dev.of_node;
1519 +       const struct rt305x_esw_platform_data *pdata;
1520 +       const __be32 *port_map, *reg_init;
1521 +       struct rt305x_esw *esw;
1522 +       struct switch_dev *swdev;
1523 +       struct resource *res, *irq;
1524 +       int err;
1525 +
1526 +       pdata = pdev->dev.platform_data;
1527 +       if (!pdata) {
1528 +               const struct of_device_id *match;
1529 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1530 +               if (match)
1531 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1532 +       }
1533 +       if (!pdata)
1534 +               return -EINVAL;
1535 +
1536 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 +       if (!res) {
1538 +               dev_err(&pdev->dev, "no memory resource found\n");
1539 +               return -ENOMEM;
1540 +       }
1541 +
1542 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1543 +       if (!irq) {
1544 +               dev_err(&pdev->dev, "no irq resource found\n");
1545 +               return -ENOMEM;
1546 +       }
1547 +
1548 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1549 +       if (!esw) {
1550 +               dev_err(&pdev->dev, "no memory for private data\n");
1551 +               return -ENOMEM;
1552 +       }
1553 +
1554 +       esw->dev = &pdev->dev;
1555 +       esw->irq = irq->start;
1556 +       esw->base = ioremap(res->start, resource_size(res));
1557 +       if (!esw->base) {
1558 +               dev_err(&pdev->dev, "ioremap failed\n");
1559 +               err = -ENOMEM;
1560 +               goto free_esw;
1561 +       }
1562 +
1563 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1564 +        if (port_map)
1565 +               esw->port_map = be32_to_cpu(*port_map);
1566 +
1567 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1568 +        if (reg_init)
1569 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1570 +
1571 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1572 +        if (reg_init)
1573 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1574 +
1575 +       reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1576 +        if (reg_init)
1577 +               esw->reg_led_polarity = be32_to_cpu(*reg_init);
1578 +
1579 +       swdev = &esw->swdev;
1580 +       swdev->of_node = pdev->dev.of_node;
1581 +       swdev->name = "rt305x-esw";
1582 +       swdev->alias = "rt305x";
1583 +       swdev->cpu_port = RT305X_ESW_PORT6;
1584 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1585 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1586 +       swdev->ops = &esw_ops;
1587 +
1588 +       err = register_switch(swdev, NULL);
1589 +       if (err < 0) {
1590 +               dev_err(&pdev->dev, "register_switch failed\n");
1591 +               goto unmap_base;
1592 +       }
1593 +
1594 +       platform_set_drvdata(pdev, esw);
1595 +
1596 +       esw->pdata = pdata;
1597 +       spin_lock_init(&esw->reg_rw_lock);
1598 +
1599 +       esw_hw_init(esw);
1600 +
1601 +       esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1602 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1603 +       request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1604 +
1605 +       return 0;
1606 +
1607 +unmap_base:
1608 +       iounmap(esw->base);
1609 +free_esw:
1610 +       kfree(esw);
1611 +       return err;
1612 +}
1613 +
1614 +static int esw_remove(struct platform_device *pdev)
1615 +{
1616 +       struct rt305x_esw *esw;
1617 +
1618 +       esw = platform_get_drvdata(pdev);
1619 +       if (esw) {
1620 +               unregister_switch(&esw->swdev);
1621 +               platform_set_drvdata(pdev, NULL);
1622 +               iounmap(esw->base);
1623 +               kfree(esw);
1624 +       }
1625 +
1626 +       return 0;
1627 +}
1628 +
1629 +static struct platform_driver esw_driver = {
1630 +       .probe = esw_probe,
1631 +       .remove = esw_remove,
1632 +       .driver = {
1633 +               .name = "rt305x-esw",
1634 +               .owner = THIS_MODULE,
1635 +               .of_match_table = ralink_esw_match,
1636 +       },
1637 +};
1638 +
1639 +int __init rtesw_init(void)
1640 +{
1641 +       return platform_driver_register(&esw_driver);
1642 +}
1643 +
1644 +void rtesw_exit(void)
1645 +{
1646 +       platform_driver_unregister(&esw_driver);
1647 +}
1648 diff --git a/drivers/net/ethernet/ralink/esw_rt3052.h b/drivers/net/ethernet/ralink/esw_rt3052.h
1649 new file mode 100644
1650 index 0000000..2ced3dff
1651 --- /dev/null
1652 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1653 @@ -0,0 +1,32 @@
1654 +/*
1655 + *   This program is free software; you can redistribute it and/or modify
1656 + *   it under the terms of the GNU General Public License as published by
1657 + *   the Free Software Foundation; version 2 of the License
1658 + *
1659 + *   This program is distributed in the hope that it will be useful,
1660 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1661 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1662 + *   GNU General Public License for more details.
1663 + *
1664 + *   You should have received a copy of the GNU General Public License
1665 + *   along with this program; if not, write to the Free Software
1666 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1667 + *
1668 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1669 + */
1670 +
1671 +#ifndef _RALINK_ESW_RT3052_H__
1672 +#define _RALINK_ESW_RT3052_H__
1673 +
1674 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1675 +
1676 +int __init rtesw_init(void);
1677 +void rtesw_exit(void);
1678 +
1679 +#else
1680 +
1681 +static inline int __init rtesw_init(void) { return 0; }
1682 +static inline void rtesw_exit(void) { }
1683 +
1684 +#endif
1685 +#endif
1686 diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.c b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1687 new file mode 100644
1688 index 0000000..9fa6a54
1689 --- /dev/null
1690 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1691 @@ -0,0 +1,1027 @@
1692 +/*
1693 + *   This program is free software; you can redistribute it and/or modify
1694 + *   it under the terms of the GNU General Public License as published by
1695 + *   the Free Software Foundation; version 2 of the License
1696 + *
1697 + *   This program is distributed in the hope that it will be useful,
1698 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1699 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1700 + *   GNU General Public License for more details.
1701 + *
1702 + *   You should have received a copy of the GNU General Public License
1703 + *   along with this program; if not, write to the Free Software
1704 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1705 + *
1706 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1707 + */
1708 +
1709 +#include <linux/module.h>
1710 +#include <linux/kernel.h>
1711 +#include <linux/types.h>
1712 +#include <linux/dma-mapping.h>
1713 +#include <linux/init.h>
1714 +#include <linux/skbuff.h>
1715 +#include <linux/etherdevice.h>
1716 +#include <linux/ethtool.h>
1717 +#include <linux/platform_device.h>
1718 +#include <linux/of_device.h>
1719 +#include <linux/clk.h>
1720 +#include <linux/of_net.h>
1721 +#include <linux/of_mdio.h>
1722 +#include <linux/of_irq.h>
1723 +#include <linux/of_address.h>
1724 +#include <linux/switch.h>
1725 +
1726 +#include <asm/mach-ralink/ralink_regs.h>
1727 +
1728 +#include "ralink_soc_eth.h"
1729 +
1730 +#include <linux/ioport.h>
1731 +#include <linux/switch.h>
1732 +#include <linux/mii.h>
1733 +
1734 +#include <ralink_regs.h>
1735 +#include <asm/mach-ralink/mt7620.h>
1736 +
1737 +#include "ralink_soc_eth.h"
1738 +#include "gsw_mt7620a.h"
1739 +#include "mdio.h"
1740 +
1741 +#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
1742 +
1743 +#define MT7620A_GSW_REG_PIAC   0x7004
1744 +
1745 +#define GSW_NUM_VLANS          16
1746 +#define GSW_NUM_VIDS           4096
1747 +#define GSW_NUM_PORTS          7
1748 +#define GSW_PORT6              6
1749 +
1750 +#define GSW_MDIO_ACCESS                BIT(31)
1751 +#define GSW_MDIO_READ          BIT(19)
1752 +#define GSW_MDIO_WRITE         BIT(18)
1753 +#define GSW_MDIO_START         BIT(16)
1754 +#define GSW_MDIO_ADDR_SHIFT    20
1755 +#define GSW_MDIO_REG_SHIFT     25
1756 +
1757 +#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
1758 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1759 +#define GSW_REG_SMACCR0                0x3fE4
1760 +#define GSW_REG_SMACCR1                0x3fE8
1761 +#define GSW_REG_CKGCR          0x3ff0
1762 +
1763 +#define GSW_REG_IMR            0x7008
1764 +#define GSW_REG_ISR            0x700c
1765 +
1766 +#define SYSC_REG_CFG1          0x14
1767 +
1768 +#define PORT_IRQ_ST_CHG                0x7f
1769 +
1770 +#define GSW_VLAN_VTCR          0x90
1771 +#define GSW_VLAN_VTCR_VID_M    0xfff
1772 +#define GSW_VLAN_ID(_x)                (0x100 + (4 * (_x)))
1773 +#define GSW_VLAN_ID_VID_S      12
1774 +#define GSW_VLAN_ID_VID_M      0xfff
1775 +
1776 +#define GSW_VAWD1              0x94
1777 +#define GSW_VAWD1_VTAG_EN      BIT(28)
1778 +#define GSW_VAWD1_PORTM_S      16
1779 +#define GSW_VAWD1_PORTM_M      0xff
1780 +
1781 +#define GSW_VAWD2              0x98
1782 +#define GSW_VAWD2_PORTT_S      16
1783 +#define GSW_VAWD2_PORTT_M      0xff
1784 +
1785 +#define GSW_VTIM(_x)           (0x100 + (4 * (_x)))
1786 +#define GSW_VTIM_M             0xfff
1787 +#define GSW_VTIM_S             12
1788 +
1789 +#define GSW_REG_PCR(x)         (0x2004 + (x * 0x100))
1790 +#define GSW_REG_PCR_EG_TAG_S   28
1791 +#define GSW_REG_PCR_EG_TAG_M   0x3
1792 +
1793 +#define SYSCFG1                        0x14
1794 +
1795 +#define ESW_PHY_POLLING                0x7000
1796 +
1797 +#define        PMCR_IPG                BIT(18)
1798 +#define        PMCR_MAC_MODE           BIT(16)
1799 +#define        PMCR_FORCE              BIT(15)
1800 +#define        PMCR_TX_EN              BIT(14)
1801 +#define        PMCR_RX_EN              BIT(13)
1802 +#define        PMCR_BACKOFF            BIT(9)
1803 +#define        PMCR_BACKPRES           BIT(8)
1804 +#define        PMCR_RX_FC              BIT(5)
1805 +#define        PMCR_TX_FC              BIT(4)
1806 +#define        PMCR_SPEED(_x)          (_x << 2)
1807 +#define        PMCR_DUPLEX             BIT(1)
1808 +#define        PMCR_LINK               BIT(0)
1809 +
1810 +#define PHY_AN_EN              BIT(31)
1811 +#define PHY_PRE_EN             BIT(30)
1812 +#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
1813 +
1814 +enum {
1815 +       /* Global attributes. */
1816 +       GSW_ATTR_ENABLE_VLAN,
1817 +       /* Port attributes. */
1818 +       GSW_ATTR_PORT_UNTAG,
1819 +};
1820 +
1821 +enum {
1822 +       PORT4_EPHY = 0,
1823 +       PORT4_EXT,
1824 +};
1825 +
1826 +struct gsw_port {
1827 +       bool    disable;
1828 +       bool    untag;
1829 +       u16     pvid;
1830 +};
1831 +
1832 +struct gsw_vlan {
1833 +       u8      ports;
1834 +       u16     vid;
1835 +};
1836 +
1837 +struct mt7620_gsw {
1838 +       struct device           *dev;
1839 +       void __iomem            *base;
1840 +       int                     irq;
1841 +
1842 +       struct switch_dev       swdev;
1843 +       bool                    global_vlan_enable;
1844 +       struct gsw_vlan         vlans[GSW_NUM_VLANS];
1845 +       struct gsw_port         ports[GSW_NUM_PORTS];
1846 +       long unsigned int       autopoll;
1847 +       int                     port4;
1848 +};
1849 +
1850 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1851 +{
1852 +       iowrite32(val, gsw->base + reg);
1853 +}
1854 +
1855 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1856 +{
1857 +       return ioread32(gsw->base + reg);
1858 +}
1859 +
1860 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1861 +{
1862 +       unsigned long t_start = jiffies;
1863 +
1864 +       while (1) {
1865 +               if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1866 +                       return 0;
1867 +               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1868 +                       break;
1869 +               }
1870 +       }
1871 +
1872 +       printk(KERN_ERR "mdio: MDIO timeout\n");
1873 +       return -1;
1874 +}
1875 +
1876 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1877 +                               u32 write_data)
1878 +{
1879 +       if (mt7620_mii_busy_wait(gsw))
1880 +               return -1;
1881 +
1882 +       write_data &= 0xffff;
1883 +
1884 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1885 +               (phy_register << GSW_MDIO_REG_SHIFT) |
1886 +               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1887 +               MT7620A_GSW_REG_PIAC);
1888 +
1889 +       if (mt7620_mii_busy_wait(gsw))
1890 +               return -1;
1891 +
1892 +       return 0;
1893 +}
1894 +
1895 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1896 +{
1897 +       struct fe_priv *priv = bus->priv;
1898 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1899 +
1900 +       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1901 +}
1902 +
1903 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1904 +{
1905 +       struct fe_priv *priv = bus->priv;
1906 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1907 +       u32 d;
1908 +
1909 +       if (mt7620_mii_busy_wait(gsw))
1910 +               return 0xffff;
1911 +
1912 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1913 +               (phy_reg << GSW_MDIO_REG_SHIFT) |
1914 +               (phy_addr << GSW_MDIO_ADDR_SHIFT),
1915 +               MT7620A_GSW_REG_PIAC);
1916 +
1917 +       if (mt7620_mii_busy_wait(gsw))
1918 +               return 0xffff;
1919 +
1920 +       d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1921 +
1922 +       return d;
1923 +}
1924 +
1925 +static unsigned char *fe_speed_str(int speed)
1926 +{
1927 +       switch (speed) {
1928 +       case 2:
1929 +       case SPEED_1000:
1930 +               return "1000";
1931 +       case 1:
1932 +       case SPEED_100:
1933 +               return "100";
1934 +       case 0:
1935 +       case SPEED_10:
1936 +               return "10";
1937 +       }
1938 +
1939 +       return "? ";
1940 +}
1941 +
1942 +int mt7620a_has_carrier(struct fe_priv *priv)
1943 +{
1944 +        struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1945 +       int i;
1946 +
1947 +       for (i = 0; i < GSW_PORT6; i++)
1948 +               if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1949 +                       return 1;
1950 +       return 0;
1951 +}
1952 +
1953 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1954 +{
1955 +       if (!priv->phy)
1956 +               return;
1957 +
1958 +       if (mt7620a_has_carrier(priv))
1959 +               netif_carrier_on(priv->netdev);
1960 +       else
1961 +               netif_carrier_off(priv->netdev);
1962 +}
1963 +
1964 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1965 +{
1966 +       if (priv->link[port])
1967 +               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1968 +                       port, fe_speed_str(priv->phy->speed[port]),
1969 +                       (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1970 +       else
1971 +               netdev_info(priv->netdev, "port %d link down\n", port);
1972 +       mt7620a_handle_carrier(priv);
1973 +}
1974 +
1975 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1976 +{
1977 +       struct fe_priv *priv = (struct fe_priv *) _priv;
1978 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1979 +       u32 status;
1980 +       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1981 +
1982 +       status = gsw_r32(gsw, GSW_REG_ISR);
1983 +       if (status & PORT_IRQ_ST_CHG)
1984 +               for (i = 0; i <= max; i++) {
1985 +                       u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1986 +                       int link = status & 0x1;
1987 +
1988 +                       if (link != priv->link[i]) {
1989 +                               if (link)
1990 +                                       netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1991 +                                                       i, fe_speed_str((status >> 2) & 3),
1992 +                                                       (status & 0x2) ? "Full" : "Half");
1993 +                               else
1994 +                                       netdev_info(priv->netdev, "port %d link down\n", i);
1995 +                       }
1996 +
1997 +                       priv->link[i] = link;
1998 +               }
1999 +       mt7620a_handle_carrier(priv);
2000 +
2001 +       gsw_w32(gsw, status, GSW_REG_ISR);
2002 +
2003 +       return IRQ_HANDLED;
2004 +}
2005 +
2006 +static int mt7620_is_bga(void)
2007 +{
2008 +       u32 bga = rt_sysc_r32(0x0c);
2009 +
2010 +       return (bga >> 16) & 1;
2011 +}
2012 +
2013 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
2014 +{
2015 +       int phy;
2016 +       int lsb = -1, msb = 0;
2017 +
2018 +       for_each_set_bit(phy, &gsw->autopoll, 32) {
2019 +               if (lsb < 0)
2020 +                       lsb = phy;
2021 +               msb = phy;
2022 +       }
2023 +
2024 +       gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
2025 +}
2026 +
2027 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
2028 +{
2029 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2030 +       const __be32 *_id = of_get_property(np, "reg", NULL);
2031 +       int phy_mode, size, id;
2032 +       int shift = 12;
2033 +       u32 val, mask = 0;
2034 +       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2035 +
2036 +       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2037 +               if (_id)
2038 +                       pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2039 +               else
2040 +                       pr_err("%s: invalid port id\n", np->name);
2041 +               return;
2042 +       }
2043 +
2044 +       id = be32_to_cpu(*_id);
2045 +
2046 +       if (id == 4)
2047 +               shift = 14;
2048 +
2049 +       priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2050 +       if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2051 +               pr_err("%s: invalid fixed link property\n", np->name);
2052 +               priv->phy->phy_fixed[id] = NULL;
2053 +               return;
2054 +       }
2055 +
2056 +       phy_mode = of_get_phy_mode(np);
2057 +       switch (phy_mode) {
2058 +       case PHY_INTERFACE_MODE_RGMII:
2059 +               mask = 0;
2060 +               break;
2061 +       case PHY_INTERFACE_MODE_MII:
2062 +               mask = 1;
2063 +               break;
2064 +       case PHY_INTERFACE_MODE_RMII:
2065 +               mask = 2;
2066 +               break;
2067 +       default:
2068 +               dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[id]);
2069 +               return;
2070 +       }
2071 +
2072 +       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2073 +       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2074 +               return;
2075 +
2076 +       val = rt_sysc_r32(SYSCFG1);
2077 +       val &= ~(3 << shift);
2078 +       val |= mask << shift;
2079 +       rt_sysc_w32(val, SYSCFG1);
2080 +
2081 +       if (priv->phy->phy_fixed[id]) {
2082 +               const __be32 *link = priv->phy->phy_fixed[id];
2083 +               int tx_fc = be32_to_cpup(link++);
2084 +               int rx_fc = be32_to_cpup(link++);
2085 +               u32 val = 0;
2086 +
2087 +               priv->phy->speed[id] = be32_to_cpup(link++);
2088 +               priv->phy->duplex[id] = be32_to_cpup(link++);
2089 +               priv->link[id] = 1;
2090 +
2091 +               switch (priv->phy->speed[id]) {
2092 +               case SPEED_10:
2093 +                       val = 0;
2094 +                       break;
2095 +               case SPEED_100:
2096 +                       val = 1;
2097 +                       break;
2098 +               case SPEED_1000:
2099 +                       val = 2;
2100 +                       break;
2101 +               default:
2102 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2103 +                       priv->phy->phy_fixed[id] = 0;
2104 +                       return;
2105 +               }
2106 +               val = PMCR_SPEED(val);
2107 +               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2108 +                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2109 +               if (tx_fc)
2110 +                       val |= PMCR_TX_FC;
2111 +               if (rx_fc)
2112 +                       val |= PMCR_RX_FC;
2113 +               if (priv->phy->duplex[id])
2114 +                       val |= PMCR_DUPLEX;
2115 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2116 +               dev_info(priv->device, "using fixed link parameters\n");
2117 +               return;
2118 +       }
2119 +
2120 +       if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2121 +               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2122 +                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
2123 +
2124 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2125 +               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2126 +               gsw->autopoll |= BIT(id);
2127 +               gsw_auto_poll(gsw);
2128 +               return;
2129 +       }
2130 +}
2131 +
2132 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2133 +{
2134 +       u32 is_BGA = mt7620_is_bga();
2135 +
2136 +       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2137 +       gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2138 +
2139 +       /*correct  PHY  setting L3.0 BGA*/
2140 +       _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2141 +
2142 +       _mt7620_mii_write(gsw, 1, 17, 0x7444);
2143 +       if (is_BGA)
2144 +               _mt7620_mii_write(gsw, 1, 19, 0x0114);
2145 +       else
2146 +               _mt7620_mii_write(gsw, 1, 19, 0x0117);
2147 +
2148 +       _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2149 +       _mt7620_mii_write(gsw, 1, 25, 0x6212);
2150 +       _mt7620_mii_write(gsw, 1, 26, 0x0777);
2151 +       _mt7620_mii_write(gsw, 1, 29, 0x4000);
2152 +       _mt7620_mii_write(gsw, 1, 28, 0xc077);
2153 +       _mt7620_mii_write(gsw, 1, 24, 0x0000);
2154 +
2155 +       _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2156 +       _mt7620_mii_write(gsw, 1, 17, 0x4838);
2157 +
2158 +       _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2159 +       if (is_BGA) {
2160 +               _mt7620_mii_write(gsw, 1, 21, 0x0515);
2161 +               _mt7620_mii_write(gsw, 1, 22, 0x0053);
2162 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2163 +               _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2164 +               _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2165 +               _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2166 +       } else {
2167 +               _mt7620_mii_write(gsw, 1, 21, 0x0517);
2168 +               _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2169 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2170 +               _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2171 +               _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2172 +               _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2173 +       }
2174 +       _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2175 +       _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2176 +
2177 +       _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2178 +       _mt7620_mii_write(gsw, 0, 30, 0xa000);
2179 +       _mt7620_mii_write(gsw, 1, 30, 0xa000);
2180 +       _mt7620_mii_write(gsw, 2, 30, 0xa000);
2181 +       _mt7620_mii_write(gsw, 3, 30, 0xa000);
2182 +
2183 +       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2184 +       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2185 +       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2186 +       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2187 +       _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2188 +       _mt7620_mii_write(gsw, 0, 16, 0x1111);
2189 +       _mt7620_mii_write(gsw, 1, 16, 0x1010);
2190 +       _mt7620_mii_write(gsw, 2, 16, 0x1515);
2191 +       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2192 +
2193 +       /* CPU Port6 Force Link 1G, FC ON */
2194 +       gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2195 +       /* Set Port6 CPU Port */
2196 +       gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2197 +
2198 +//     GSW_VAWD2
2199 +
2200 +       /* setup port 4 */
2201 +       if (gsw->port4 == PORT4_EPHY) {
2202 +               u32 val = rt_sysc_r32(SYSCFG1);
2203 +               val |= 3 << 14;
2204 +               rt_sysc_w32(val, SYSCFG1);
2205 +               _mt7620_mii_write(gsw, 4, 30, 0xa000);
2206 +               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2207 +               _mt7620_mii_write(gsw, 4, 16, 0x1313);
2208 +               pr_info("gsw: setting port4 to ephy mode\n");
2209 +       }
2210 +}
2211 +
2212 +static int gsw_reset_switch(struct switch_dev *dev)
2213 +{
2214 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2215 +
2216 +       gsw->global_vlan_enable = 0;
2217 +       memset(gsw->ports, 0, sizeof(gsw->ports));
2218 +       memset(gsw->vlans, 0, sizeof(gsw->vlans));
2219 +       gsw_hw_init(gsw);
2220 +
2221 +       return 0;
2222 +}
2223 +
2224 +static int gsw_get_vlan_enable(struct switch_dev *dev,
2225 +                          const struct switch_attr *attr,
2226 +                          struct switch_val *val)
2227 +{
2228 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2229 +
2230 +       val->value.i = gsw->global_vlan_enable;
2231 +
2232 +       return 0;
2233 +}
2234 +
2235 +static int gsw_set_vlan_enable(struct switch_dev *dev,
2236 +                          const struct switch_attr *attr,
2237 +                          struct switch_val *val)
2238 +{
2239 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2240 +
2241 +       gsw->global_vlan_enable = val->value.i != 0;
2242 +
2243 +       return 0;
2244 +}
2245 +
2246 +static unsigned gsw_get_pvid(struct mt7620_gsw *gsw, unsigned port)
2247 +{
2248 +       unsigned s, val;
2249 +
2250 +       s = GSW_VTIM_S * (port % 2);
2251 +       val = gsw_r32(gsw, GSW_VTIM(port / 2));
2252 +
2253 +       return (val >> s) & GSW_VTIM_M;
2254 +}
2255 +
2256 +static void gsw_set_pvid(struct mt7620_gsw *gsw, unsigned port, unsigned pvid)
2257 +{
2258 +       unsigned s, val;
2259 +
2260 +       s = GSW_VTIM_S * (port % 2);
2261 +       val = gsw_r32(gsw, GSW_VTIM(port / 2));
2262 +       val &= ~(GSW_VTIM_M << s);
2263 +       val |= (pvid && GSW_VTIM_M) << s;
2264 +       gsw_w32(gsw, val, GSW_VTIM(port / 2));
2265 +}
2266 +
2267 +static int gsw_get_port_bool(struct switch_dev *dev,
2268 +                        const struct switch_attr *attr,
2269 +                        struct switch_val *val)
2270 +{
2271 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2272 +       int idx = val->port_vlan;
2273 +
2274 +       if (idx < 0 || idx >= GSW_NUM_PORTS)
2275 +               return -EINVAL;
2276 +
2277 +       switch (attr->id) {
2278 +       case GSW_ATTR_PORT_UNTAG:
2279 +               return gsw->ports[idx].untag;
2280 +       }
2281 +
2282 +       return -EINVAL;
2283 +}
2284 +
2285 +static int gsw_get_port_pvid(struct switch_dev *dev, int port, int *val)
2286 +{
2287 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2288 +
2289 +       if (port >= GSW_NUM_PORTS)
2290 +               return -EINVAL;
2291 +
2292 +       *val = gsw_get_pvid(gsw, port);
2293 +
2294 +       return 0;
2295 +}
2296 +
2297 +static int gsw_set_port_pvid(struct switch_dev *dev, int port, int val)
2298 +{
2299 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2300 +
2301 +       if (port >= GSW_NUM_PORTS)
2302 +               return -EINVAL;
2303 +
2304 +       gsw->ports[port].pvid = val;
2305 +
2306 +       return 0;
2307 +}
2308 +
2309 +static void gsw_set_vtcr(struct switch_dev *dev, u32 vid)
2310 +{
2311 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2312 +       int retry = 1000;
2313 +
2314 +       gsw_w32(gsw, 0x80000000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2315 +       while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2316 +               ;
2317 +}
2318 +
2319 +static void gsw_apply_vtcr(struct switch_dev *dev, u32 vid)
2320 +{
2321 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2322 +       int retry = 1000;
2323 +
2324 +       gsw_w32(gsw, 0x80001000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2325 +       while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2326 +               ;
2327 +}
2328 +
2329 +static unsigned gsw_get_vlan_id(struct mt7620_gsw *gsw, unsigned vlan)
2330 +{
2331 +       unsigned s;
2332 +       unsigned val;
2333 +
2334 +       s = GSW_VLAN_ID_VID_S * (vlan % 2);
2335 +       val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2336 +       val = (val >> s) & GSW_VLAN_ID_VID_M;
2337 +
2338 +       return val;
2339 +}
2340 +
2341 +static void gsw_set_vlan_id(struct mt7620_gsw *gsw, unsigned vlan, unsigned vid)
2342 +{
2343 +       unsigned s;
2344 +       unsigned val;
2345 +
2346 +       s = GSW_VLAN_ID_VID_S * (vlan % 2);
2347 +       val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2348 +       val &= ~(GSW_VLAN_ID_VID_M << s);
2349 +       val |= (vid << s);
2350 +       gsw_w32(gsw, val, GSW_VLAN_ID(vlan / 2));
2351 +}
2352 +
2353 +static void gsw_vlan_tagging_enable(struct mt7620_gsw *gsw, unsigned vlan, unsigned enable)
2354 +{
2355 +       unsigned val;
2356 +
2357 +       val = gsw_r32(gsw, GSW_VAWD1);
2358 +       if (enable)
2359 +               val |= GSW_VAWD1_VTAG_EN;
2360 +       else
2361 +               val &= ~GSW_VAWD1_VTAG_EN;
2362 +       gsw_w32(gsw, val, GSW_VAWD1);
2363 +}
2364 +
2365 +static unsigned gsw_get_port_member(struct mt7620_gsw *gsw, unsigned vlan)
2366 +{
2367 +       unsigned val;
2368 +
2369 +       gsw_set_vtcr(&gsw->swdev, vlan);
2370 +
2371 +       val = gsw_r32(gsw, GSW_VAWD1);
2372 +       val = (val >> GSW_VAWD1_PORTM_S) & GSW_VAWD1_PORTM_M;
2373 +
2374 +       return val;
2375 +}
2376 +
2377 +static void gsw_set_port_member(struct mt7620_gsw *gsw, unsigned vlan, unsigned member)
2378 +{
2379 +       unsigned val;
2380 +
2381 +       val = gsw_r32(gsw, GSW_VAWD1);
2382 +       val = ~(GSW_VAWD1_PORTM_M << GSW_VAWD1_PORTM_S);
2383 +       val |= (member & GSW_VAWD1_PORTM_M) << GSW_VAWD1_PORTM_S;
2384 +        gsw_w32(gsw, val, GSW_VAWD1);
2385 +}
2386 +
2387 +static unsigned gsw_get_port_tag(struct mt7620_gsw *gsw, unsigned port)
2388 +{
2389 +       unsigned val;
2390 +
2391 +       val = gsw_r32(gsw, GSW_REG_PCR(port));
2392 +       val >>= GSW_REG_PCR_EG_TAG_S;
2393 +       val &= GSW_REG_PCR_EG_TAG_M;
2394 +
2395 +       return !!val;
2396 +}
2397 +
2398 +static void gsw_set_port_untag(struct mt7620_gsw *gsw, unsigned port, unsigned untag)
2399 +{
2400 +       unsigned val;
2401 +
2402 +       val = gsw_r32(gsw, GSW_REG_PCR(port));
2403 +       if (!untag)
2404 +               untag = 0x2;
2405 +       else
2406 +               untag = 0;
2407 +       val &= ~(GSW_REG_PCR_EG_TAG_M << GSW_REG_PCR_EG_TAG_S);
2408 +       val |= (untag & GSW_REG_PCR_EG_TAG_M) << GSW_REG_PCR_EG_TAG_S;
2409 +       gsw_w32(gsw, val, GSW_REG_PCR(port));
2410 +}
2411 +
2412 +static int gsw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2413 +{
2414 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2415 +       int vlan_idx = -1;
2416 +       u32 member;
2417 +       int i;
2418 +
2419 +       val->len = 0;
2420 +
2421 +       if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS)
2422 +               return -EINVAL;
2423 +
2424 +       /* valid vlan? */
2425 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2426 +               if (gsw_get_vlan_id(gsw, i) != val->port_vlan)
2427 +                       continue;
2428 +               member = gsw_get_port_member(gsw, i);
2429 +               vlan_idx = i;
2430 +               break;
2431 +       }
2432 +
2433 +       if (vlan_idx == -1)
2434 +               return -EINVAL;
2435 +
2436 +       for (i = 0; i < GSW_NUM_PORTS; i++) {
2437 +               struct switch_port *p;
2438 +               int port_mask = 1 << i;
2439 +
2440 +               if (!(member & port_mask))
2441 +                       continue;
2442 +
2443 +               p = &val->value.ports[val->len++];
2444 +               p->id = i;
2445 +               if (gsw_get_port_tag(gsw, i))
2446 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
2447 +               else
2448 +                       p->flags = 0;
2449 +       }
2450 +
2451 +       return 0;
2452 +}
2453 +
2454 +static int gsw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2455 +{
2456 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2457 +       int ports;
2458 +       int vlan_idx = -1;
2459 +       int i;
2460 +
2461 +       if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS ||
2462 +                       val->len > GSW_NUM_PORTS)
2463 +               return -EINVAL;
2464 +
2465 +       /* one of the already defined vlans? */
2466 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2467 +               if (gsw->vlans[i].vid == val->port_vlan &&
2468 +                   gsw->vlans[i].ports) {
2469 +                       vlan_idx = i;
2470 +                       break;
2471 +               }
2472 +       }
2473 +
2474 +       /* select a free slot */
2475 +       for (i = 0; vlan_idx == -1 && i < GSW_NUM_VLANS; i++) {
2476 +               if (!gsw->vlans[i].ports)
2477 +                       vlan_idx = i;
2478 +       }
2479 +
2480 +       /* bail if all slots are in use */
2481 +       if (vlan_idx == -1)
2482 +               return -EINVAL;
2483 +
2484 +       ports = 0;
2485 +       for (i = 0; i < val->len; i++) {
2486 +               struct switch_port *p = &val->value.ports[i];
2487 +               int port_mask = 1 << p->id;
2488 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
2489 +
2490 +               if (p->id >= GSW_NUM_PORTS)
2491 +                       return -EINVAL;
2492 +
2493 +               ports |= port_mask;
2494 +               gsw->ports[p->id].untag = untagged;
2495 +       }
2496 +       gsw->vlans[vlan_idx].ports = ports;
2497 +       if (!ports)
2498 +               gsw->vlans[vlan_idx].vid = 0xfff;
2499 +       else
2500 +               gsw->vlans[vlan_idx].vid = val->port_vlan;
2501 +
2502 +       return 0;
2503 +}
2504 +
2505 +static int gsw_apply_config(struct switch_dev *dev)
2506 +{
2507 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2508 +       int i;
2509 +
2510 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2511 +               gsw_set_vtcr(&gsw->swdev, i);
2512 +               if (gsw->global_vlan_enable) {
2513 +                       gsw_set_vlan_id(gsw, i, gsw->vlans[i].vid);
2514 +                       gsw_set_port_member(gsw, i, gsw->vlans[i].ports);
2515 +                       gsw_vlan_tagging_enable(gsw, i, 1);
2516 +               } else {
2517 +                       gsw_set_vlan_id(gsw, i, 0xfff);
2518 +                       gsw_set_port_member(gsw, i, 0);
2519 +                       gsw_vlan_tagging_enable(gsw, i, 0);
2520 +               }
2521 +               gsw_apply_vtcr(&gsw->swdev, i);
2522 +       }
2523 +
2524 +       for (i = 0; i < GSW_NUM_PORTS; i++) {
2525 +               if (gsw->global_vlan_enable) {
2526 +                       gsw_set_port_untag(gsw, i, !gsw->ports[i].untag);
2527 +                       gsw_set_pvid(gsw, i, gsw->ports[i].pvid);
2528 +               } else {
2529 +                       gsw_set_port_untag(gsw, i, 0);
2530 +                       gsw_set_pvid(gsw, i, 0);
2531 +               }
2532 +       }
2533 +
2534 +       if (!gsw->global_vlan_enable)
2535 +               gsw_set_vlan_id(gsw, 0, 0);
2536 +
2537 +       return 0;
2538 +}
2539 +
2540 +static int gsw_get_port_link(struct switch_dev *dev,
2541 +                        int port,
2542 +                        struct switch_port_link *link)
2543 +{
2544 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2545 +       u32 status;
2546 +
2547 +       if (port < 0 || port >= GSW_NUM_PORTS)
2548 +               return -EINVAL;
2549 +
2550 +       status = gsw_r32(gsw, GSW_REG_PORT_STATUS(port));
2551 +       link->link = status & 0x1;
2552 +       link->duplex = (status >> 1) & 1;
2553 +
2554 +       switch ((status >> 2) & 0x3) {
2555 +       case 0:
2556 +               link->speed = SWITCH_PORT_SPEED_10;
2557 +               break;
2558 +       case 1:
2559 +               link->speed = SWITCH_PORT_SPEED_100;
2560 +               break;
2561 +       case 2:
2562 +       case 3: // forced gige speed can be 2 or 3
2563 +               link->speed = SWITCH_PORT_SPEED_1000;
2564 +               break;
2565 +       }
2566 +
2567 +       return 0;
2568 +}
2569 +
2570 +static int gsw_set_port_bool(struct switch_dev *dev,
2571 +                        const struct switch_attr *attr,
2572 +                        struct switch_val *val)
2573 +{
2574 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2575 +       int idx = val->port_vlan;
2576 +
2577 +       if (idx < 0 || idx >= GSW_NUM_PORTS ||
2578 +           val->value.i < 0 || val->value.i > 1)
2579 +               return -EINVAL;
2580 +
2581 +       switch (attr->id) {
2582 +       case GSW_ATTR_PORT_UNTAG:
2583 +               gsw->ports[idx].untag = val->value.i;
2584 +               break;
2585 +       default:
2586 +               return -EINVAL;
2587 +       }
2588 +
2589 +       return 0;
2590 +}
2591 +
2592 +static const struct switch_attr gsw_global[] = {
2593 +       {
2594 +               .type = SWITCH_TYPE_INT,
2595 +               .name = "enable_vlan",
2596 +               .description = "VLAN mode (1:enabled)",
2597 +               .max = 1,
2598 +               .id = GSW_ATTR_ENABLE_VLAN,
2599 +               .get = gsw_get_vlan_enable,
2600 +               .set = gsw_set_vlan_enable,
2601 +       },
2602 +};
2603 +
2604 +static const struct switch_attr gsw_port[] = {
2605 +       {
2606 +               .type = SWITCH_TYPE_INT,
2607 +               .name = "untag",
2608 +               .description = "Untag (1:strip outgoing vlan tag)",
2609 +               .max = 1,
2610 +               .id = GSW_ATTR_PORT_UNTAG,
2611 +               .get = gsw_get_port_bool,
2612 +               .set = gsw_set_port_bool,
2613 +       },
2614 +};
2615 +
2616 +static const struct switch_attr gsw_vlan[] = {
2617 +};
2618 +
2619 +static const struct switch_dev_ops gsw_ops = {
2620 +       .attr_global = {
2621 +               .attr = gsw_global,
2622 +               .n_attr = ARRAY_SIZE(gsw_global),
2623 +       },
2624 +       .attr_port = {
2625 +               .attr = gsw_port,
2626 +               .n_attr = ARRAY_SIZE(gsw_port),
2627 +       },
2628 +       .attr_vlan = {
2629 +               .attr = gsw_vlan,
2630 +               .n_attr = ARRAY_SIZE(gsw_vlan),
2631 +       },
2632 +       .get_vlan_ports = gsw_get_vlan_ports,
2633 +       .set_vlan_ports = gsw_set_vlan_ports,
2634 +       .get_port_pvid = gsw_get_port_pvid,
2635 +       .set_port_pvid = gsw_set_port_pvid,
2636 +       .get_port_link = gsw_get_port_link,
2637 +       .apply_config = gsw_apply_config,
2638 +       .reset_switch = gsw_reset_switch,
2639 +};
2640 +
2641 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2642 +{
2643 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2644 +       unsigned long flags;
2645 +
2646 +       spin_lock_irqsave(&priv->page_lock, flags);
2647 +       gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2648 +       gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2649 +               GSW_REG_SMACCR0);
2650 +       spin_unlock_irqrestore(&priv->page_lock, flags);
2651 +}
2652 +
2653 +static struct of_device_id gsw_match[] = {
2654 +       { .compatible = "ralink,mt7620a-gsw" },
2655 +       {}
2656 +};
2657 +
2658 +int mt7620_gsw_probe(struct fe_priv *priv)
2659 +{
2660 +       struct mt7620_gsw *gsw;
2661 +       struct device_node *np;
2662 +       struct switch_dev *swdev;
2663 +       const char *port4 = NULL;
2664 +
2665 +       np = of_find_matching_node(NULL, gsw_match);
2666 +       if (!np) {
2667 +               dev_err(priv->device, "no gsw node found\n");
2668 +               return -EINVAL;
2669 +       }
2670 +       np = of_node_get(np);
2671 +
2672 +       gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2673 +       if (!gsw) {
2674 +               dev_err(priv->device, "no gsw memory for private data\n");
2675 +               return -ENOMEM;
2676 +       }
2677 +
2678 +       gsw->irq = irq_of_parse_and_map(np, 0);
2679 +       if (!gsw->irq) {
2680 +               dev_err(priv->device, "no gsw irq resource found\n");
2681 +               return -ENOMEM;
2682 +       }
2683 +
2684 +       gsw->base = of_iomap(np, 0);
2685 +       if (!gsw->base) {
2686 +               dev_err(priv->device, "gsw ioremap failed\n");
2687 +       }
2688 +
2689 +       gsw->dev = priv->device;
2690 +       priv->soc->swpriv = gsw;
2691 +
2692 +       swdev = &gsw->swdev;
2693 +       swdev->of_node = np;
2694 +       swdev->name = "mt7620a-gsw";
2695 +       swdev->alias = "mt7620x";
2696 +       swdev->cpu_port = GSW_PORT6;
2697 +       swdev->ports = GSW_NUM_PORTS;
2698 +       swdev->vlans = GSW_NUM_VLANS;
2699 +       swdev->ops = &gsw_ops;
2700 +
2701 +       if (register_switch(swdev, NULL))
2702 +               dev_err(priv->device, "register_switch failed\n");
2703 +
2704 +       of_property_read_string(np, "ralink,port4", &port4);
2705 +       if (port4 && !strcmp(port4, "ephy"))
2706 +               gsw->port4 = PORT4_EPHY;
2707 +       else if (port4 && !strcmp(port4, "gmac"))
2708 +               gsw->port4 = PORT4_EXT;
2709 +       else
2710 +               WARN_ON(port4);
2711 +
2712 +       gsw_hw_init(gsw);
2713 +
2714 +       gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2715 +       request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2716 +
2717 +       return 0;
2718 +}
2719 diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.h b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2720 new file mode 100644
2721 index 0000000..fd4add5
2722 --- /dev/null
2723 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2724 @@ -0,0 +1,29 @@
2725 +/*
2726 + *   This program is free software; you can redistribute it and/or modify
2727 + *   it under the terms of the GNU General Public License as published by
2728 + *   the Free Software Foundation; version 2 of the License
2729 + *
2730 + *   This program is distributed in the hope that it will be useful,
2731 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2732 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2733 + *   GNU General Public License for more details.
2734 + *
2735 + *   You should have received a copy of the GNU General Public License
2736 + *   along with this program; if not, write to the Free Software
2737 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2738 + *
2739 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2740 + */
2741 +
2742 +#ifndef _RALINK_GSW_MT7620_H__
2743 +#define _RALINK_GSW_MT7620_H__
2744 +
2745 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2746 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2747 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2748 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2749 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2750 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2751 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2752 +
2753 +#endif
2754 diff --git a/drivers/net/ethernet/ralink/mdio.c b/drivers/net/ethernet/ralink/mdio.c
2755 new file mode 100644
2756 index 0000000..b265c75
2757 --- /dev/null
2758 +++ b/drivers/net/ethernet/ralink/mdio.c
2759 @@ -0,0 +1,245 @@
2760 +/*
2761 + *   This program is free software; you can redistribute it and/or modify
2762 + *   it under the terms of the GNU General Public License as published by
2763 + *   the Free Software Foundation; version 2 of the License
2764 + *
2765 + *   This program is distributed in the hope that it will be useful,
2766 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2767 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2768 + *   GNU General Public License for more details.
2769 + *
2770 + *   You should have received a copy of the GNU General Public License
2771 + *   along with this program; if not, write to the Free Software
2772 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2773 + *
2774 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2775 + */
2776 +
2777 +#include <linux/module.h>
2778 +#include <linux/kernel.h>
2779 +#include <linux/types.h>
2780 +#include <linux/dma-mapping.h>
2781 +#include <linux/init.h>
2782 +#include <linux/skbuff.h>
2783 +#include <linux/etherdevice.h>
2784 +#include <linux/ethtool.h>
2785 +#include <linux/platform_device.h>
2786 +#include <linux/phy.h>
2787 +#include <linux/of_device.h>
2788 +#include <linux/clk.h>
2789 +#include <linux/of_net.h>
2790 +#include <linux/of_mdio.h>
2791 +
2792 +#include "ralink_soc_eth.h"
2793 +#include "mdio.h"
2794 +
2795 +static int fe_mdio_reset(struct mii_bus *bus)
2796 +{
2797 +       /* TODO */
2798 +       return 0;
2799 +}
2800 +
2801 +static void fe_phy_link_adjust(struct net_device *dev)
2802 +{
2803 +       struct fe_priv *priv = netdev_priv(dev);
2804 +       unsigned long flags;
2805 +       int i;
2806 +
2807 +       spin_lock_irqsave(&priv->phy->lock, flags);
2808 +       for (i = 0; i < 8; i++) {
2809 +               if (priv->phy->phy_node[i]) {
2810 +                       struct phy_device *phydev = priv->phy->phy[i];
2811 +                       int status_change = 0;
2812 +
2813 +                       if (phydev->link)
2814 +                               if (priv->phy->duplex[i] != phydev->duplex ||
2815 +                                               priv->phy->speed[i] != phydev->speed)
2816 +                                       status_change = 1;
2817 +
2818 +                       if (phydev->link != priv->link[i])
2819 +                               status_change = 1;
2820 +
2821 +                       switch (phydev->speed) {
2822 +                       case SPEED_1000:
2823 +                       case SPEED_100:
2824 +                       case SPEED_10:
2825 +                               priv->link[i] = phydev->link;
2826 +                               priv->phy->duplex[i] = phydev->duplex;
2827 +                               priv->phy->speed[i] = phydev->speed;
2828 +
2829 +                               if (status_change && priv->soc->mdio_adjust_link)
2830 +                                       priv->soc->mdio_adjust_link(priv, i);
2831 +                               break;
2832 +                       }
2833 +               }
2834 +       }
2835 +       spin_unlock_irqrestore(&priv->phy->lock, flags);
2836 +}
2837 +
2838 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2839 +{
2840 +       const __be32 *_port = NULL;
2841 +       struct phy_device *phydev;
2842 +       int phy_mode, port;
2843 +
2844 +       _port = of_get_property(phy_node, "reg", NULL);
2845 +
2846 +       if (!_port || (be32_to_cpu(*_port) >= 8)) {
2847 +               pr_err("%s: invalid port id\n", phy_node->name);
2848 +               return -EINVAL;
2849 +       }
2850 +       port = be32_to_cpu(*_port);
2851 +       phy_mode = of_get_phy_mode(phy_node);
2852 +       if (phy_mode < 0) {
2853 +               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2854 +               priv->phy->phy_node[port] = NULL;
2855 +               return -EINVAL;
2856 +       }
2857 +
2858 +       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2859 +                               0, phy_mode);
2860 +       if (IS_ERR(phydev)) {
2861 +               dev_err(priv->device, "could not connect to PHY\n");
2862 +               priv->phy->phy_node[port] = NULL;
2863 +               return PTR_ERR(phydev);
2864 +       }
2865 +
2866 +       phydev->supported &= PHY_GBIT_FEATURES;
2867 +       phydev->advertising = phydev->supported;
2868 +       phydev->no_auto_carrier_off = 1;
2869 +
2870 +       dev_info(priv->device,
2871 +                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2872 +                port, dev_name(&phydev->dev), phydev->phy_id,
2873 +                phydev->drv->name);
2874 +
2875 +       priv->phy->phy[port] = phydev;
2876 +       priv->link[port] = 0;
2877 +
2878 +       return 0;
2879 +}
2880 +
2881 +static int fe_phy_connect(struct fe_priv *priv)
2882 +{
2883 +       return 0;
2884 +}
2885 +
2886 +static void fe_phy_disconnect(struct fe_priv *priv)
2887 +{
2888 +       unsigned long flags;
2889 +       int i;
2890 +
2891 +       for (i = 0; i < 8; i++)
2892 +               if (priv->phy->phy_fixed[i]) {
2893 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2894 +                       priv->link[i] = 0;
2895 +                       if (priv->soc->mdio_adjust_link)
2896 +                               priv->soc->mdio_adjust_link(priv, i);
2897 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2898 +               } else if (priv->phy->phy[i]) {
2899 +                       phy_disconnect(priv->phy->phy[i]);
2900 +               }
2901 +}
2902 +
2903 +static void fe_phy_start(struct fe_priv *priv)
2904 +{
2905 +       unsigned long flags;
2906 +       int i;
2907 +
2908 +       for (i = 0; i < 8; i++) {
2909 +               if (priv->phy->phy_fixed[i]) {
2910 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2911 +                       priv->link[i] = 1;
2912 +                       if (priv->soc->mdio_adjust_link)
2913 +                               priv->soc->mdio_adjust_link(priv, i);
2914 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2915 +               } else if (priv->phy->phy[i]) {
2916 +                       phy_start(priv->phy->phy[i]);
2917 +               }
2918 +       }
2919 +}
2920 +
2921 +static void fe_phy_stop(struct fe_priv *priv)
2922 +{
2923 +       unsigned long flags;
2924 +       int i;
2925 +
2926 +       for (i = 0; i < 8; i++)
2927 +               if (priv->phy->phy_fixed[i]) {
2928 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2929 +                       priv->link[i] = 0;
2930 +                       if (priv->soc->mdio_adjust_link)
2931 +                               priv->soc->mdio_adjust_link(priv, i);
2932 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2933 +               } else if (priv->phy->phy[i]) {
2934 +                       phy_stop(priv->phy->phy[i]);
2935 +               }
2936 +}
2937 +
2938 +static struct fe_phy phy_ralink = {
2939 +       .connect = fe_phy_connect,
2940 +       .disconnect = fe_phy_disconnect,
2941 +       .start = fe_phy_start,
2942 +       .stop = fe_phy_stop,
2943 +};
2944 +
2945 +int fe_mdio_init(struct fe_priv *priv)
2946 +{
2947 +       struct device_node *mii_np;
2948 +       int err;
2949 +
2950 +       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2951 +               return 0;
2952 +
2953 +       spin_lock_init(&phy_ralink.lock);
2954 +       priv->phy = &phy_ralink;
2955 +
2956 +       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2957 +       if (!mii_np) {
2958 +               dev_err(priv->device, "no %s child node found", "mdio-bus");
2959 +               return -ENODEV;
2960 +       }
2961 +
2962 +       if (!of_device_is_available(mii_np)) {
2963 +               err = 0;
2964 +               goto err_put_node;
2965 +       }
2966 +
2967 +       priv->mii_bus = mdiobus_alloc();
2968 +       if (priv->mii_bus == NULL) {
2969 +               err = -ENOMEM;
2970 +               goto err_put_node;
2971 +       }
2972 +
2973 +       priv->mii_bus->name = "mdio";
2974 +       priv->mii_bus->read = priv->soc->mdio_read;
2975 +       priv->mii_bus->write = priv->soc->mdio_write;
2976 +       priv->mii_bus->reset = fe_mdio_reset;
2977 +       priv->mii_bus->irq = priv->mii_irq;
2978 +       priv->mii_bus->priv = priv;
2979 +       priv->mii_bus->parent = priv->device;
2980 +
2981 +       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2982 +       err = of_mdiobus_register(priv->mii_bus, mii_np);
2983 +       if (err)
2984 +               goto err_free_bus;
2985 +
2986 +       return 0;
2987 +
2988 +err_free_bus:
2989 +       kfree(priv->mii_bus);
2990 +err_put_node:
2991 +       of_node_put(mii_np);
2992 +       priv->mii_bus = NULL;
2993 +       return err;
2994 +}
2995 +
2996 +void fe_mdio_cleanup(struct fe_priv *priv)
2997 +{
2998 +       if (!priv->mii_bus)
2999 +               return;
3000 +
3001 +       mdiobus_unregister(priv->mii_bus);
3002 +       of_node_put(priv->mii_bus->dev.of_node);
3003 +       kfree(priv->mii_bus);
3004 +}
3005 diff --git a/drivers/net/ethernet/ralink/mdio.h b/drivers/net/ethernet/ralink/mdio.h
3006 new file mode 100644
3007 index 0000000..c3910a0
3008 --- /dev/null
3009 +++ b/drivers/net/ethernet/ralink/mdio.h
3010 @@ -0,0 +1,29 @@
3011 +/*
3012 + *   This program is free software; you can redistribute it and/or modify
3013 + *   it under the terms of the GNU General Public License as published by
3014 + *   the Free Software Foundation; version 2 of the License
3015 + *
3016 + *   This program is distributed in the hope that it will be useful,
3017 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3018 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3019 + *   GNU General Public License for more details.
3020 + *
3021 + *   You should have received a copy of the GNU General Public License
3022 + *   along with this program; if not, write to the Free Software
3023 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3024 + *
3025 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3026 + */
3027 +
3028 +#ifndef _RALINK_MDIO_H__
3029 +#define _RALINK_MDIO_H__
3030 +
3031 +#ifdef CONFIG_NET_RALINK_MDIO
3032 +extern int fe_mdio_init(struct fe_priv *priv);
3033 +extern void fe_mdio_cleanup(struct fe_priv *priv);
3034 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
3035 +#else
3036 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
3037 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
3038 +#endif
3039 +#endif
3040 diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.c b/drivers/net/ethernet/ralink/mdio_rt2880.c
3041 new file mode 100644
3042 index 0000000..54dbc53
3043 --- /dev/null
3044 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
3045 @@ -0,0 +1,163 @@
3046 +/*
3047 + *   This program is free software; you can redistribute it and/or modify
3048 + *   it under the terms of the GNU General Public License as published by
3049 + *   the Free Software Foundation; version 2 of the License
3050 + *
3051 + *   This program is distributed in the hope that it will be useful,
3052 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3053 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3054 + *   GNU General Public License for more details.
3055 + *
3056 + *   You should have received a copy of the GNU General Public License
3057 + *   along with this program; if not, write to the Free Software
3058 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3059 + *
3060 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3061 + */
3062 +
3063 +#include <linux/module.h>
3064 +#include <linux/kernel.h>
3065 +#include <linux/types.h>
3066 +#include <linux/dma-mapping.h>
3067 +#include <linux/init.h>
3068 +#include <linux/skbuff.h>
3069 +#include <linux/etherdevice.h>
3070 +#include <linux/ethtool.h>
3071 +#include <linux/platform_device.h>
3072 +#include <linux/phy.h>
3073 +#include <linux/of_device.h>
3074 +#include <linux/clk.h>
3075 +#include <linux/of_net.h>
3076 +#include <linux/of_mdio.h>
3077 +
3078 +#include "ralink_soc_eth.h"
3079 +#include "mdio_rt2880.h"
3080 +
3081 +#define FE_MDIO_RETRY  1000
3082 +
3083 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
3084 +{
3085 +       switch (priv->phy->speed[0]) {
3086 +       case SPEED_1000:
3087 +               return "1000";
3088 +       case SPEED_100:
3089 +               return "100";
3090 +       case SPEED_10:
3091 +               return "10";
3092 +       }
3093 +
3094 +       return "?";
3095 +}
3096 +
3097 +void rt2880_mdio_link_adjust(struct fe_priv *priv)
3098 +{
3099 +       u32 mdio_cfg;
3100 +
3101 +       if (!priv->link[0]) {
3102 +               netif_carrier_off(priv->netdev);
3103 +               netdev_info(priv->netdev, "link down\n");
3104 +               return;
3105 +       }
3106 +
3107 +       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
3108 +                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
3109 +                  FE_MDIO_CFG_GP1_FRC_EN;
3110 +
3111 +       if (priv->phy->duplex[0] == DUPLEX_FULL)
3112 +               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
3113 +
3114 +       if (priv->phy->tx_fc)
3115 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
3116 +
3117 +       if (priv->phy->rx_fc)
3118 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
3119 +
3120 +       switch (priv->phy->speed[0]) {
3121 +       case SPEED_10:
3122 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
3123 +               break;
3124 +       case SPEED_100:
3125 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
3126 +               break;
3127 +       case SPEED_1000:
3128 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
3129 +               break;
3130 +       default:
3131 +               BUG();
3132 +       }
3133 +
3134 +       fe_w32(mdio_cfg, FE_MDIO_CFG);
3135 +
3136 +       netif_carrier_on(priv->netdev);
3137 +       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
3138 +                   rt2880_speed_str(priv),
3139 +                   (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
3140 +}
3141 +
3142 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
3143 +{
3144 +       int retries;
3145 +
3146 +       retries = FE_MDIO_RETRY;
3147 +       while (1) {
3148 +               u32 t;
3149 +
3150 +               t = fe_r32(FE_MDIO_ACCESS);
3151 +               if ((t & (0x1 << 31)) == 0)
3152 +                       return 0;
3153 +
3154 +               if (retries-- == 0)
3155 +                       break;
3156 +
3157 +               udelay(1);
3158 +       }
3159 +
3160 +       dev_err(priv->device, "MDIO operation timed out\n");
3161 +       return -ETIMEDOUT;
3162 +}
3163 +
3164 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
3165 +{
3166 +       struct fe_priv *priv = bus->priv;
3167 +       int err;
3168 +       u32 t;
3169 +
3170 +       err = rt2880_mdio_wait_ready(priv);
3171 +       if (err)
3172 +               return 0xffff;
3173 +
3174 +       t = (phy_addr << 24) | (phy_reg << 16);
3175 +       fe_w32(t, FE_MDIO_ACCESS);
3176 +       t |= (1 << 31);
3177 +       fe_w32(t, FE_MDIO_ACCESS);
3178 +
3179 +       err = rt2880_mdio_wait_ready(priv);
3180 +       if (err)
3181 +               return 0xffff;
3182 +
3183 +       pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3184 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3185 +
3186 +       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
3187 +}
3188 +
3189 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
3190 +{
3191 +       struct fe_priv *priv = bus->priv;
3192 +       int err;
3193 +       u32 t;
3194 +
3195 +       pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3196 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3197 +
3198 +       err = rt2880_mdio_wait_ready(priv);
3199 +       if (err)
3200 +               return err;
3201 +
3202 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
3203 +       fe_w32(t, FE_MDIO_ACCESS);
3204 +       t |= (1 << 31);
3205 +       fe_w32(t, FE_MDIO_ACCESS);
3206 +
3207 +       return rt2880_mdio_wait_ready(priv);
3208 +}
3209 diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.h b/drivers/net/ethernet/ralink/mdio_rt2880.h
3210 new file mode 100644
3211 index 0000000..c9ac0fe
3212 --- /dev/null
3213 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
3214 @@ -0,0 +1,25 @@
3215 +/*
3216 + *   This program is free software; you can redistribute it and/or modify
3217 + *   it under the terms of the GNU General Public License as published by
3218 + *   the Free Software Foundation; version 2 of the License
3219 + *
3220 + *   This program is distributed in the hope that it will be useful,
3221 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3222 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3223 + *   GNU General Public License for more details.
3224 + *
3225 + *   You should have received a copy of the GNU General Public License
3226 + *   along with this program; if not, write to the Free Software
3227 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3228 + *
3229 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3230 + */
3231 +
3232 +#ifndef _RALINK_MDIO_RT2880_H__
3233 +#define _RALINK_MDIO_RT2880_H__
3234 +
3235 +void rt2880_mdio_link_adjust(struct fe_priv *priv);
3236 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
3237 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
3238 +
3239 +#endif
3240 diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.c b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3241 new file mode 100644
3242 index 0000000..04e82eb
3243 --- /dev/null
3244 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3245 @@ -0,0 +1,759 @@
3246 +/*
3247 + *   This program is free software; you can redistribute it and/or modify
3248 + *   it under the terms of the GNU General Public License as published by
3249 + *   the Free Software Foundation; version 2 of the License
3250 + *
3251 + *   This program is distributed in the hope that it will be useful,
3252 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3253 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3254 + *   GNU General Public License for more details.
3255 + *
3256 + *   You should have received a copy of the GNU General Public License
3257 + *   along with this program; if not, write to the Free Software
3258 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3259 + *
3260 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3261 + */
3262 +
3263 +#include <linux/module.h>
3264 +#include <linux/kernel.h>
3265 +#include <linux/types.h>
3266 +#include <linux/dma-mapping.h>
3267 +#include <linux/init.h>
3268 +#include <linux/skbuff.h>
3269 +#include <linux/etherdevice.h>
3270 +#include <linux/ethtool.h>
3271 +#include <linux/platform_device.h>
3272 +#include <linux/of_device.h>
3273 +#include <linux/clk.h>
3274 +#include <linux/of_net.h>
3275 +#include <linux/of_mdio.h>
3276 +#include <linux/if_vlan.h>
3277 +
3278 +#include <asm/mach-ralink/ralink_regs.h>
3279 +
3280 +#include "ralink_soc_eth.h"
3281 +#include "esw_rt3052.h"
3282 +#include "mdio.h"
3283 +
3284 +#define TX_TIMEOUT             (20 * HZ / 100)
3285 +#define        MAX_RX_LENGTH           1536
3286 +
3287 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3288 +       [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3289 +       [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3290 +       [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3291 +       [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3292 +       [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3293 +       [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3294 +       [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3295 +       [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3296 +       [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3297 +       [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3298 +       [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3299 +       [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
3300 +};
3301 +
3302 +static const u32 *fe_reg_table = fe_reg_table_default;
3303 +
3304 +static void __iomem *fe_base = 0;
3305 +
3306 +void fe_w32(u32 val, unsigned reg)
3307 +{
3308 +       __raw_writel(val, fe_base + reg);
3309 +}
3310 +
3311 +u32 fe_r32(unsigned reg)
3312 +{
3313 +       return __raw_readl(fe_base + reg);
3314 +}
3315 +
3316 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3317 +{
3318 +       fe_w32(val, fe_reg_table[reg]);
3319 +}
3320 +
3321 +static inline u32 fe_reg_r32(enum fe_reg reg)
3322 +{
3323 +       return fe_r32(fe_reg_table[reg]);
3324 +}
3325 +
3326 +static inline void fe_int_disable(u32 mask)
3327 +{
3328 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3329 +                    FE_REG_FE_INT_ENABLE);
3330 +       /* flush write */
3331 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3332 +}
3333 +
3334 +static inline void fe_int_enable(u32 mask)
3335 +{
3336 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3337 +                    FE_REG_FE_INT_ENABLE);
3338 +       /* flush write */
3339 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3340 +}
3341 +
3342 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3343 +{
3344 +       unsigned long flags;
3345 +
3346 +       spin_lock_irqsave(&priv->page_lock, flags);
3347 +       fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3348 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3349 +                    FE_GDMA1_MAC_ADRL);
3350 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3351 +}
3352 +
3353 +static int fe_set_mac_address(struct net_device *dev, void *p)
3354 +{
3355 +       int ret = eth_mac_addr(dev, p);
3356 +
3357 +       if (!ret) {
3358 +               struct fe_priv *priv = netdev_priv(dev);
3359 +
3360 +               if (priv->soc->set_mac)
3361 +                       priv->soc->set_mac(priv, dev->dev_addr);
3362 +               else
3363 +                       fe_hw_set_macaddr(priv, p);
3364 +       }
3365 +
3366 +       return ret;
3367 +}
3368 +
3369 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3370 +{
3371 +       struct sk_buff *skb;
3372 +
3373 +       skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3374 +       if (!skb)
3375 +               return NULL;
3376 +
3377 +       skb_reserve(skb, NET_IP_ALIGN);
3378 +
3379 +       return skb;
3380 +}
3381 +
3382 +static int fe_alloc_rx(struct fe_priv *priv)
3383 +{
3384 +       int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3385 +       int i;
3386 +
3387 +       priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3388 +                                       &priv->rx_phys, GFP_ATOMIC);
3389 +       if (!priv->rx_dma)
3390 +               return -ENOMEM;
3391 +
3392 +       memset(priv->rx_dma, 0, size);
3393 +
3394 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3395 +               priv->rx_skb[i] = fe_alloc_skb(priv);
3396 +               if (!priv->rx_skb[i])
3397 +                       return -ENOMEM;
3398 +       }
3399 +
3400 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3401 +               dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3402 +                                               priv->rx_skb[i]->data,
3403 +                                               MAX_RX_LENGTH,
3404 +                                               DMA_FROM_DEVICE);
3405 +               priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3406 +
3407 +               if (priv->soc->rx_dma)
3408 +                       priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3409 +               else
3410 +                       priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3411 +       }
3412 +       wmb();
3413 +
3414 +       fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3415 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3416 +       fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3417 +       fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3418 +
3419 +       return 0;
3420 +}
3421 +
3422 +static int fe_alloc_tx(struct fe_priv *priv)
3423 +{
3424 +       int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3425 +       int i;
3426 +
3427 +       priv->tx_free_idx = 0;
3428 +
3429 +       priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3430 +                                       &priv->tx_phys, GFP_ATOMIC);
3431 +       if (!priv->tx_dma)
3432 +               return -ENOMEM;
3433 +
3434 +       memset(priv->tx_dma, 0, size);
3435 +
3436 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3437 +               if (priv->soc->tx_dma) {
3438 +                       priv->soc->tx_dma(priv, i, 0);
3439 +                       continue;
3440 +               }
3441 +
3442 +               priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3443 +               priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3444 +       }
3445 +
3446 +       fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3447 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3448 +       fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3449 +       fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3450 +
3451 +       return 0;
3452 +}
3453 +
3454 +static void fe_free_dma(struct fe_priv *priv)
3455 +{
3456 +       int i;
3457 +
3458 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3459 +               if (priv->rx_skb[i]) {
3460 +                       dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3461 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3462 +                       dev_kfree_skb_any(priv->rx_skb[i]);
3463 +                       priv->rx_skb[i] = NULL;
3464 +               }
3465 +
3466 +               if (priv->tx_skb[i]) {
3467 +                       dev_kfree_skb_any(priv->tx_skb[i]);
3468 +                       priv->tx_skb[i] = NULL;
3469 +               }
3470 +       }
3471 +
3472 +       if (priv->rx_dma) {
3473 +               int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3474 +               dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3475 +                                       priv->rx_phys);
3476 +       }
3477 +
3478 +       if (priv->tx_dma) {
3479 +               int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3480 +               dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3481 +                                       priv->tx_phys);
3482 +       }
3483 +
3484 +       netdev_reset_queue(priv->netdev);
3485 +}
3486 +
3487 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3488 +{
3489 +       struct fe_priv *priv = netdev_priv(dev);
3490 +       dma_addr_t mapped_addr;
3491 +       u32 tx_next;
3492 +       u32 tx;
3493 +
3494 +       if (priv->soc->min_pkt_len) {
3495 +               if (skb->len < priv->soc->min_pkt_len) {
3496 +                       if (skb_padto(skb, priv->soc->min_pkt_len)) {
3497 +                               printk(KERN_ERR
3498 +                                      "fe_eth: skb_padto failed\n");
3499 +                               kfree_skb(skb);
3500 +                               return 0;
3501 +                       }
3502 +                       skb_put(skb, priv->soc->min_pkt_len - skb->len);
3503 +               }
3504 +       }
3505 +
3506 +       dev->trans_start = jiffies;
3507 +       mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3508 +                               skb->len, DMA_TO_DEVICE);
3509 +
3510 +       spin_lock(&priv->page_lock);
3511 +
3512 +       tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3513 +       tx_next = (tx + 1) % NUM_DMA_DESC;
3514 +
3515 +       if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3516 +                       !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3517 +                       !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3518 +       {
3519 +               spin_unlock(&priv->page_lock);
3520 +               dev->stats.tx_dropped++;
3521 +               kfree_skb(skb);
3522 +
3523 +               return NETDEV_TX_OK;
3524 +       }
3525 +
3526 +       priv->tx_skb[tx] = skb;
3527 +       priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3528 +       wmb();
3529 +       if (priv->soc->tx_dma)
3530 +               priv->soc->tx_dma(priv, tx, skb->len);
3531 +       else
3532 +               priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3533 +
3534 +       if (skb->ip_summed == CHECKSUM_PARTIAL)
3535 +               priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3536 +       else
3537 +               priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3538 +
3539 +        if (fe_reg_table[FE_REG_FE_DMA_VID_BASE] && vlan_tx_tag_present(skb))
3540 +               priv->tx_dma[tx].txd4 |= 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
3541 +       else
3542 +               priv->tx_dma[tx].txd4 &= ~0x80;
3543 +
3544 +       dev->stats.tx_packets++;
3545 +       dev->stats.tx_bytes += skb->len;
3546 +
3547 +       fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3548 +       netdev_sent_queue(dev, skb->len);
3549 +
3550 +       spin_unlock(&priv->page_lock);
3551 +
3552 +       return NETDEV_TX_OK;
3553 +}
3554 +
3555 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3556 +{
3557 +       struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3558 +       int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3559 +       unsigned long flags;
3560 +       int complete = 0;
3561 +       int rx = 0;
3562 +
3563 +       while ((rx < budget) && !complete) {
3564 +
3565 +               idx = (idx + 1) % NUM_DMA_DESC;
3566 +
3567 +               if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3568 +                       struct sk_buff *new_skb = fe_alloc_skb(priv);
3569 +
3570 +                       if (new_skb) {
3571 +                               int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3572 +                               dma_addr_t dma_addr;
3573 +
3574 +                               dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3575 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3576 +
3577 +                               skb_put(priv->rx_skb[idx], pktlen);
3578 +                               priv->rx_skb[idx]->dev = priv->netdev;
3579 +                               priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3580 +                               if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3581 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3582 +                               else
3583 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3584 +                               priv->netdev->stats.rx_packets++;
3585 +                               priv->netdev->stats.rx_bytes += pktlen;
3586 +                               netif_rx(priv->rx_skb[idx]);
3587 +
3588 +                               priv->rx_skb[idx] = new_skb;
3589 +
3590 +                               dma_addr = dma_map_single(&priv->netdev->dev,
3591 +                                                 new_skb->data,
3592 +                                                 MAX_RX_LENGTH,
3593 +                                                 DMA_FROM_DEVICE);
3594 +                               priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3595 +                               wmb();
3596 +                       } else {
3597 +                               priv->netdev->stats.rx_dropped++;
3598 +                       }
3599 +
3600 +                       if (priv->soc->rx_dma)
3601 +                               priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3602 +                       else
3603 +                               priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3604 +                       fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3605 +                       rx++;
3606 +               } else {
3607 +                       complete = 1;
3608 +               }
3609 +       }
3610 +
3611 +       if (complete || !rx) {
3612 +               napi_complete(&priv->rx_napi);
3613 +               spin_lock_irqsave(&priv->page_lock, flags);
3614 +               fe_int_enable(priv->soc->rx_dly_int);
3615 +               spin_unlock_irqrestore(&priv->page_lock, flags);
3616 +       }
3617 +
3618 +       return rx;
3619 +}
3620 +
3621 +static int fe_poll_tx(struct napi_struct *napi, int budget)
3622 +{
3623 +       struct fe_priv *priv = container_of(napi, struct fe_priv, tx_napi);
3624 +       unsigned int bytes_compl = 0;
3625 +       unsigned int pkts_compl = 0;
3626 +       struct netdev_queue *txq;
3627 +       unsigned long flags;
3628 +
3629 +       spin_lock_irqsave(&priv->page_lock, flags);
3630 +       while (pkts_compl < budget) {
3631 +               struct fe_tx_dma *txd;
3632 +
3633 +               txd = &priv->tx_dma[priv->tx_free_idx];
3634 +
3635 +               if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3636 +                       break;
3637 +
3638 +               bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3639 +               pkts_compl++;
3640 +
3641 +               dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3642 +               priv->tx_skb[priv->tx_free_idx] = NULL;
3643 +               priv->tx_free_idx++;
3644 +               if (priv->tx_free_idx >= NUM_DMA_DESC)
3645 +                       priv->tx_free_idx = 0;
3646 +       }
3647 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3648 +
3649 +       txq = netdev_get_tx_queue(priv->netdev, 0);
3650 +       if (netif_tx_queue_stopped(txq))
3651 +               netif_tx_start_queue(txq);
3652 +
3653 +       napi_complete(napi);
3654 +       netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3655 +
3656 +       spin_lock_irqsave(&priv->page_lock, flags);
3657 +       fe_int_enable(priv->soc->tx_dly_int);
3658 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3659 +
3660 +       return pkts_compl;
3661 +}
3662 +
3663 +static void fe_tx_timeout(struct net_device *dev)
3664 +{
3665 +       struct fe_priv *priv = netdev_priv(dev);
3666 +
3667 +       priv->netdev->stats.tx_errors++;
3668 +       netdev_err(dev, "transmit timed out, waking up the queue\n");
3669 +       netif_wake_queue(dev);
3670 +}
3671 +
3672 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3673 +{
3674 +       struct fe_priv *priv = netdev_priv(dev);
3675 +       unsigned int status;
3676 +       unsigned int mask;
3677 +
3678 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3679 +       mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3680 +
3681 +       if (!(status & mask))
3682 +               return IRQ_NONE;
3683 +
3684 +       if (status & priv->soc->rx_dly_int) {
3685 +               fe_int_disable(priv->soc->rx_dly_int);
3686 +               napi_schedule(&priv->rx_napi);
3687 +       }
3688 +
3689 +       if (status & priv->soc->tx_dly_int) {
3690 +               fe_int_disable(priv->soc->tx_dly_int);
3691 +               napi_schedule(&priv->tx_napi);
3692 +       }
3693 +
3694 +       fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3695 +
3696 +       return IRQ_HANDLED;
3697 +}
3698 +
3699 +static int fe_hw_init(struct net_device *dev)
3700 +{
3701 +       struct fe_priv *priv = netdev_priv(dev);
3702 +       int err, i;
3703 +
3704 +       err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3705 +                               dev_name(priv->device), dev);
3706 +       if (err)
3707 +               return err;
3708 +
3709 +       err = fe_alloc_rx(priv);
3710 +       if (!err)
3711 +               err = fe_alloc_tx(priv);
3712 +       if (err)
3713 +               return err;
3714 +
3715 +       if (priv->soc->set_mac)
3716 +               priv->soc->set_mac(priv, dev->dev_addr);
3717 +       else
3718 +               fe_hw_set_macaddr(priv, dev->dev_addr);
3719 +
3720 +       fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3721 +
3722 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3723 +
3724 +
3725 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3726 +               for (i = 0; i < 16; i += 2)
3727 +                       fe_w32((i + 1) << 16 | i, fe_reg_table[FE_REG_FE_DMA_VID_BASE] + (i * 4));
3728 +
3729 +       if (priv->soc->fwd_config) {
3730 +               priv->soc->fwd_config(priv);
3731 +       } else {
3732 +               unsigned long sysclk = priv->sysclk;
3733 +
3734 +               if (!sysclk) {
3735 +                       netdev_err(dev, "unable to get clock\n");
3736 +                       return -EINVAL;
3737 +               }
3738 +
3739 +               sysclk /= FE_US_CYC_CNT_DIVISOR;
3740 +               sysclk <<= FE_US_CYC_CNT_SHIFT;
3741 +
3742 +               fe_w32((fe_r32(FE_FE_GLO_CFG) &
3743 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | priv->sysclk,
3744 +                       FE_FE_GLO_CFG);
3745 +
3746 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3747 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3748 +                       FE_GDMA1_FWD_CFG);
3749 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3750 +                       FE_CDMA_CSG_CFG);
3751 +               fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3752 +       }
3753 +
3754 +       fe_w32(1, FE_FE_RST_GL);
3755 +       fe_w32(0, FE_FE_RST_GL);
3756 +
3757 +       return 0;
3758 +}
3759 +
3760 +static int fe_open(struct net_device *dev)
3761 +{
3762 +       struct fe_priv *priv = netdev_priv(dev);
3763 +       unsigned long flags;
3764 +       u32 val;
3765 +
3766 +       spin_lock_irqsave(&priv->page_lock, flags);
3767 +       napi_enable(&priv->rx_napi);
3768 +       napi_enable(&priv->tx_napi);
3769 +
3770 +       val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3771 +       val |= priv->soc->pdma_glo_cfg;
3772 +       fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3773 +
3774 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3775 +
3776 +       if (priv->phy)
3777 +               priv->phy->start(priv);
3778 +
3779 +       if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3780 +               netif_carrier_on(dev);
3781 +
3782 +       netif_start_queue(dev);
3783 +       fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3784 +
3785 +       return 0;
3786 +}
3787 +
3788 +static int fe_stop(struct net_device *dev)
3789 +{
3790 +       struct fe_priv *priv = netdev_priv(dev);
3791 +       unsigned long flags;
3792 +
3793 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3794 +
3795 +       netif_stop_queue(dev);
3796 +
3797 +       if (priv->phy)
3798 +               priv->phy->stop(priv);
3799 +
3800 +       spin_lock_irqsave(&priv->page_lock, flags);
3801 +       napi_disable(&priv->rx_napi);
3802 +       napi_disable(&priv->tx_napi);
3803 +
3804 +       fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3805 +                    ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3806 +                    FE_REG_PDMA_GLO_CFG);
3807 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3808 +
3809 +       return 0;
3810 +}
3811 +
3812 +static int __init fe_init(struct net_device *dev)
3813 +{
3814 +       struct fe_priv *priv = netdev_priv(dev);
3815 +       struct device_node *port;
3816 +       int err;
3817 +
3818 +       BUG_ON(!priv->soc->reset_fe);
3819 +       priv->soc->reset_fe();
3820 +
3821 +       if (priv->soc->switch_init)
3822 +               priv->soc->switch_init(priv);
3823 +
3824 +       net_srandom(jiffies);
3825 +       memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3826 +       of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3827 +
3828 +       err = fe_mdio_init(priv);
3829 +       if (err)
3830 +               return err;
3831 +
3832 +       if (priv->phy) {
3833 +               err = priv->phy->connect(priv);
3834 +               if (err)
3835 +                       goto err_mdio_cleanup;
3836 +       }
3837 +
3838 +       if (priv->soc->port_init)
3839 +               for_each_child_of_node(priv->device->of_node, port)
3840 +                       if (of_device_is_compatible(port, "ralink,eth-port"))
3841 +                               priv->soc->port_init(priv, port);
3842 +
3843 +       err = fe_hw_init(dev);
3844 +       if (err)
3845 +               goto err_phy_disconnect;
3846 +
3847 +       return 0;
3848 +
3849 +err_phy_disconnect:
3850 +       if (priv->phy)
3851 +               priv->phy->disconnect(priv);
3852 +err_mdio_cleanup:
3853 +       fe_mdio_cleanup(priv);
3854 +
3855 +       return err;
3856 +}
3857 +
3858 +static void fe_uninit(struct net_device *dev)
3859 +{
3860 +       struct fe_priv *priv = netdev_priv(dev);
3861 +
3862 +       if (priv->phy)
3863 +               priv->phy->disconnect(priv);
3864 +       fe_mdio_cleanup(priv);
3865 +
3866 +       fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3867 +       free_irq(dev->irq, dev);
3868 +
3869 +       fe_free_dma(priv);
3870 +}
3871 +
3872 +static const struct net_device_ops fe_netdev_ops = {
3873 +       .ndo_init               = fe_init,
3874 +       .ndo_uninit             = fe_uninit,
3875 +       .ndo_open               = fe_open,
3876 +       .ndo_stop               = fe_stop,
3877 +       .ndo_start_xmit         = fe_start_xmit,
3878 +       .ndo_tx_timeout         = fe_tx_timeout,
3879 +       .ndo_set_mac_address    = fe_set_mac_address,
3880 +       .ndo_change_mtu         = eth_change_mtu,
3881 +       .ndo_validate_addr      = eth_validate_addr,
3882 +};
3883 +
3884 +static int fe_probe(struct platform_device *pdev)
3885 +{
3886 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3887 +       const struct of_device_id *match;
3888 +       struct fe_soc_data *soc = NULL;
3889 +       struct net_device *netdev;
3890 +       struct fe_priv *priv;
3891 +       struct clk *sysclk;
3892 +       int err;
3893 +
3894 +       match = of_match_device(of_fe_match, &pdev->dev);
3895 +       soc = (struct fe_soc_data *) match->data;
3896 +       if (soc->reg_table)
3897 +               fe_reg_table = soc->reg_table;
3898 +
3899 +       fe_base = devm_request_and_ioremap(&pdev->dev, res);
3900 +       if (!fe_base)
3901 +               return -ENOMEM;
3902 +
3903 +       netdev = alloc_etherdev(sizeof(struct fe_priv));
3904 +       if (!netdev) {
3905 +               dev_err(&pdev->dev, "alloc_etherdev failed\n");
3906 +               return -ENOMEM;
3907 +       }
3908 +
3909 +       strcpy(netdev->name, "eth%d");
3910 +       netdev->netdev_ops = &fe_netdev_ops;
3911 +       netdev->base_addr = (unsigned long) fe_base;
3912 +       netdev->watchdog_timeo = TX_TIMEOUT;
3913 +       netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3914 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3915 +               netdev->features |= NETIF_F_HW_VLAN_TX;
3916 +
3917 +       netdev->irq = platform_get_irq(pdev, 0);
3918 +       if (netdev->irq < 0) {
3919 +               dev_err(&pdev->dev, "no IRQ resource found\n");
3920 +               kfree(netdev);
3921 +               return -ENXIO;
3922 +       }
3923 +
3924 +       priv = netdev_priv(netdev);
3925 +       memset(priv, 0, sizeof(struct fe_priv));
3926 +       spin_lock_init(&priv->page_lock);
3927 +
3928 +       sysclk = devm_clk_get(&pdev->dev, NULL);
3929 +       if (!IS_ERR(sysclk))
3930 +               priv->sysclk = clk_get_rate(sysclk);
3931 +
3932 +       priv->netdev = netdev;
3933 +       priv->device = &pdev->dev;
3934 +       priv->soc = soc;
3935 +
3936 +       err = register_netdev(netdev);
3937 +       if (err) {
3938 +               dev_err(&pdev->dev, "error bringing up device\n");
3939 +               kfree(netdev);
3940 +               return err;
3941 +       }
3942 +
3943 +       netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
3944 +       netif_napi_add(netdev, &priv->tx_napi, fe_poll_tx, 8);
3945 +
3946 +        platform_set_drvdata(pdev, netdev);
3947 +
3948 +       netdev_info(netdev, "done loading\n");
3949 +
3950 +       return 0;
3951 +}
3952 +
3953 +static int fe_remove(struct platform_device *pdev)
3954 +{
3955 +        struct net_device *dev = platform_get_drvdata(pdev);
3956 +       struct fe_priv *priv = netdev_priv(dev);
3957 +
3958 +       netif_stop_queue(dev);
3959 +       netif_napi_del(&priv->rx_napi);
3960 +       netif_napi_del(&priv->tx_napi);
3961 +
3962 +       unregister_netdev(dev);
3963 +       free_netdev(dev);
3964 +
3965 +       return 0;
3966 +}
3967 +
3968 +static struct platform_driver fe_driver = {
3969 +       .probe = fe_probe,
3970 +       .remove = fe_remove,
3971 +       .driver = {
3972 +               .name = "ralink_soc_eth",
3973 +               .owner = THIS_MODULE,
3974 +               .of_match_table = of_fe_match,
3975 +       },
3976 +};
3977 +
3978 +static int __init init_rtfe(void)
3979 +{
3980 +       int ret;
3981 +
3982 +       ret = rtesw_init();
3983 +       if (ret)
3984 +               return ret;
3985 +
3986 +       ret = platform_driver_register(&fe_driver);
3987 +       if (ret)
3988 +               rtesw_exit();
3989 +
3990 +       return ret;
3991 +}
3992 +
3993 +static void __exit exit_rtfe(void)
3994 +{
3995 +       platform_driver_unregister(&fe_driver);
3996 +       rtesw_exit();
3997 +}
3998 +
3999 +module_init(init_rtfe);
4000 +module_exit(exit_rtfe);
4001 +
4002 +MODULE_LICENSE("GPL");
4003 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4004 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4005 diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.h b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4006 new file mode 100644
4007 index 0000000..0c769ef
4008 --- /dev/null
4009 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4010 @@ -0,0 +1,372 @@
4011 +/*
4012 + *   This program is free software; you can redistribute it and/or modify
4013 + *   it under the terms of the GNU General Public License as published by
4014 + *   the Free Software Foundation; version 2 of the License
4015 + *
4016 + *   This program is distributed in the hope that it will be useful,
4017 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4018 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4019 + *   GNU General Public License for more details.
4020 + *
4021 + *   You should have received a copy of the GNU General Public License
4022 + *   along with this program; if not, write to the Free Software
4023 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4024 + *
4025 + *   based on Ralink SDK3.3
4026 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4027 + */
4028 +
4029 +#ifndef FE_ETH_H
4030 +#define FE_ETH_H
4031 +
4032 +#include <linux/mii.h>
4033 +#include <linux/interrupt.h>
4034 +#include <linux/netdevice.h>
4035 +#include <linux/dma-mapping.h>
4036 +#include <linux/phy.h>
4037 +
4038 +
4039 +enum fe_reg {
4040 +       FE_REG_PDMA_GLO_CFG = 0,
4041 +       FE_REG_PDMA_RST_CFG,
4042 +       FE_REG_DLY_INT_CFG,
4043 +       FE_REG_TX_BASE_PTR0,
4044 +       FE_REG_TX_MAX_CNT0,
4045 +       FE_REG_TX_CTX_IDX0,
4046 +       FE_REG_RX_BASE_PTR0,
4047 +       FE_REG_RX_MAX_CNT0,
4048 +       FE_REG_RX_CALC_IDX0,
4049 +       FE_REG_FE_INT_ENABLE,
4050 +       FE_REG_FE_INT_STATUS,
4051 +       FE_REG_FE_DMA_VID_BASE,
4052 +       FE_REG_COUNT
4053 +};
4054 +
4055 +#define NUM_DMA_DESC           0x100
4056 +
4057 +#define FE_DELAY_EN_INT                0x80
4058 +#define FE_DELAY_MAX_INT       0x04
4059 +#define FE_DELAY_MAX_TOUT      0x04
4060 +#define FE_DELAY_CHAN          (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4061 +#define FE_DELAY_INIT          ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4062 +#define FE_PSE_FQFC_CFG_INIT   0x80504000
4063 +
4064 +/* interrupt bits */
4065 +#define FE_CNT_PPE_AF          BIT(31)
4066 +#define FE_CNT_GDM_AF          BIT(29)
4067 +#define FE_PSE_P2_FC           BIT(26)
4068 +#define FE_PSE_BUF_DROP                BIT(24)
4069 +#define FE_GDM_OTHER_DROP      BIT(23)
4070 +#define FE_PSE_P1_FC           BIT(22)
4071 +#define FE_PSE_P0_FC           BIT(21)
4072 +#define FE_PSE_FQ_EMPTY                BIT(20)
4073 +#define FE_GE1_STA_CHG         BIT(18)
4074 +#define FE_TX_COHERENT         BIT(17)
4075 +#define FE_RX_COHERENT         BIT(16)
4076 +#define FE_TX_DONE_INT3                BIT(11)
4077 +#define FE_TX_DONE_INT2                BIT(10)
4078 +#define FE_TX_DONE_INT1                BIT(9)
4079 +#define FE_TX_DONE_INT0                BIT(8)
4080 +#define FE_RX_DONE_INT0                BIT(2)
4081 +#define FE_TX_DLY_INT          BIT(1)
4082 +#define FE_RX_DLY_INT          BIT(0)
4083 +
4084 +#define RT5350_RX_DLY_INT      BIT(30)
4085 +#define RT5350_TX_DLY_INT      BIT(28)
4086 +
4087 +/* registers */
4088 +#define FE_FE_OFFSET           0x0000
4089 +#define FE_GDMA_OFFSET         0x0020
4090 +#define FE_PSE_OFFSET          0x0040
4091 +#define FE_GDMA2_OFFSET                0x0060
4092 +#define FE_CDMA_OFFSET         0x0080
4093 +#define FE_DMA_VID0            0x00a8
4094 +#define FE_PDMA_OFFSET         0x0100
4095 +#define FE_PPE_OFFSET          0x0200
4096 +#define FE_CMTABLE_OFFSET      0x0400
4097 +#define FE_POLICYTABLE_OFFSET  0x1000
4098 +
4099 +#define RT5350_PDMA_OFFSET     0x0800
4100 +#define RT5350_SDM_OFFSET      0x0c00
4101 +
4102 +#define FE_MDIO_ACCESS         (FE_FE_OFFSET + 0x00)
4103 +#define FE_MDIO_CFG            (FE_FE_OFFSET + 0x04)
4104 +#define FE_FE_GLO_CFG          (FE_FE_OFFSET + 0x08)
4105 +#define FE_FE_RST_GL           (FE_FE_OFFSET + 0x0C)
4106 +#define FE_FE_INT_STATUS       (FE_FE_OFFSET + 0x10)
4107 +#define FE_FE_INT_ENABLE       (FE_FE_OFFSET + 0x14)
4108 +#define FE_MDIO_CFG2           (FE_FE_OFFSET + 0x18)
4109 +#define FE_FOC_TS_T            (FE_FE_OFFSET + 0x1C)
4110 +
4111 +#define        FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
4112 +#define FE_GDMA1_SCH_CFG       (FE_GDMA_OFFSET + 0x04)
4113 +#define FE_GDMA1_SHPR_CFG      (FE_GDMA_OFFSET + 0x08)
4114 +#define FE_GDMA1_MAC_ADRL      (FE_GDMA_OFFSET + 0x0C)
4115 +#define FE_GDMA1_MAC_ADRH      (FE_GDMA_OFFSET + 0x10)
4116 +
4117 +#define        FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
4118 +#define FE_GDMA2_SCH_CFG       (FE_GDMA2_OFFSET + 0x04)
4119 +#define FE_GDMA2_SHPR_CFG      (FE_GDMA2_OFFSET + 0x08)
4120 +#define FE_GDMA2_MAC_ADRL      (FE_GDMA2_OFFSET + 0x0C)
4121 +#define FE_GDMA2_MAC_ADRH      (FE_GDMA2_OFFSET + 0x10)
4122 +
4123 +#define FE_PSE_FQ_CFG          (FE_PSE_OFFSET + 0x00)
4124 +#define FE_CDMA_FC_CFG         (FE_PSE_OFFSET + 0x04)
4125 +#define FE_GDMA1_FC_CFG                (FE_PSE_OFFSET + 0x08)
4126 +#define FE_GDMA2_FC_CFG                (FE_PSE_OFFSET + 0x0C)
4127 +
4128 +#define FE_CDMA_CSG_CFG                (FE_CDMA_OFFSET + 0x00)
4129 +#define FE_CDMA_SCH_CFG                (FE_CDMA_OFFSET + 0x04)
4130 +
4131 +#define MT7620A_GDMA_OFFSET            0x0600
4132 +#define        MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
4133 +#define MT7620A_FE_GDMA1_SCH_CFG       (MT7620A_GDMA_OFFSET + 0x04)
4134 +#define MT7620A_FE_GDMA1_SHPR_CFG      (MT7620A_GDMA_OFFSET + 0x08)
4135 +#define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
4136 +#define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
4137 +
4138 +#define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
4139 +#define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
4140 +#define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)
4141 +#define RT5350_TX_DTX_IDX0     (RT5350_PDMA_OFFSET + 0x0C)
4142 +#define RT5350_TX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x10)
4143 +#define RT5350_TX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x14)
4144 +#define RT5350_TX_CTX_IDX1     (RT5350_PDMA_OFFSET + 0x18)
4145 +#define RT5350_TX_DTX_IDX1     (RT5350_PDMA_OFFSET + 0x1C)
4146 +#define RT5350_TX_BASE_PTR2    (RT5350_PDMA_OFFSET + 0x20)
4147 +#define RT5350_TX_MAX_CNT2     (RT5350_PDMA_OFFSET + 0x24)
4148 +#define RT5350_TX_CTX_IDX2     (RT5350_PDMA_OFFSET + 0x28)
4149 +#define RT5350_TX_DTX_IDX2     (RT5350_PDMA_OFFSET + 0x2C)
4150 +#define RT5350_TX_BASE_PTR3    (RT5350_PDMA_OFFSET + 0x30)
4151 +#define RT5350_TX_MAX_CNT3     (RT5350_PDMA_OFFSET + 0x34)
4152 +#define RT5350_TX_CTX_IDX3     (RT5350_PDMA_OFFSET + 0x38)
4153 +#define RT5350_TX_DTX_IDX3     (RT5350_PDMA_OFFSET + 0x3C)
4154 +#define RT5350_RX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x100)
4155 +#define RT5350_RX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x104)
4156 +#define RT5350_RX_CALC_IDX0    (RT5350_PDMA_OFFSET + 0x108)
4157 +#define RT5350_RX_DRX_IDX0     (RT5350_PDMA_OFFSET + 0x10C)
4158 +#define RT5350_RX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x110)
4159 +#define RT5350_RX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x114)
4160 +#define RT5350_RX_CALC_IDX1    (RT5350_PDMA_OFFSET + 0x118)
4161 +#define RT5350_RX_DRX_IDX1     (RT5350_PDMA_OFFSET + 0x11C)
4162 +#define RT5350_PDMA_GLO_CFG    (RT5350_PDMA_OFFSET + 0x204)
4163 +#define RT5350_PDMA_RST_CFG    (RT5350_PDMA_OFFSET + 0x208)
4164 +#define RT5350_DLY_INT_CFG     (RT5350_PDMA_OFFSET + 0x20c)
4165 +#define RT5350_FE_INT_STATUS   (RT5350_PDMA_OFFSET + 0x220)
4166 +#define RT5350_FE_INT_ENABLE   (RT5350_PDMA_OFFSET + 0x228)
4167 +#define RT5350_PDMA_SCH_CFG    (RT5350_PDMA_OFFSET + 0x280)
4168 +
4169 +#define FE_PDMA_GLO_CFG                (FE_PDMA_OFFSET + 0x00)
4170 +#define FE_PDMA_RST_CFG                (FE_PDMA_OFFSET + 0x04)
4171 +#define FE_PDMA_SCH_CFG                (FE_PDMA_OFFSET + 0x08)
4172 +#define FE_DLY_INT_CFG         (FE_PDMA_OFFSET + 0x0C)
4173 +#define FE_TX_BASE_PTR0                (FE_PDMA_OFFSET + 0x10)
4174 +#define FE_TX_MAX_CNT0         (FE_PDMA_OFFSET + 0x14)
4175 +#define FE_TX_CTX_IDX0         (FE_PDMA_OFFSET + 0x18)
4176 +#define FE_TX_DTX_IDX0         (FE_PDMA_OFFSET + 0x1C)
4177 +#define FE_TX_BASE_PTR1                (FE_PDMA_OFFSET + 0x20)
4178 +#define FE_TX_MAX_CNT1         (FE_PDMA_OFFSET + 0x24)
4179 +#define FE_TX_CTX_IDX1         (FE_PDMA_OFFSET + 0x28)
4180 +#define FE_TX_DTX_IDX1         (FE_PDMA_OFFSET + 0x2C)
4181 +#define FE_RX_BASE_PTR0                (FE_PDMA_OFFSET + 0x30)
4182 +#define FE_RX_MAX_CNT0         (FE_PDMA_OFFSET + 0x34)
4183 +#define FE_RX_CALC_IDX0                (FE_PDMA_OFFSET + 0x38)
4184 +#define FE_RX_DRX_IDX0         (FE_PDMA_OFFSET + 0x3C)
4185 +#define FE_TX_BASE_PTR2                (FE_PDMA_OFFSET + 0x40)
4186 +#define FE_TX_MAX_CNT2         (FE_PDMA_OFFSET + 0x44)
4187 +#define FE_TX_CTX_IDX2         (FE_PDMA_OFFSET + 0x48)
4188 +#define FE_TX_DTX_IDX2         (FE_PDMA_OFFSET + 0x4C)
4189 +#define FE_TX_BASE_PTR3                (FE_PDMA_OFFSET + 0x50)
4190 +#define FE_TX_MAX_CNT3         (FE_PDMA_OFFSET + 0x54)
4191 +#define FE_TX_CTX_IDX3         (FE_PDMA_OFFSET + 0x58)
4192 +#define FE_TX_DTX_IDX3         (FE_PDMA_OFFSET + 0x5C)
4193 +#define FE_RX_BASE_PTR1                (FE_PDMA_OFFSET + 0x60)
4194 +#define FE_RX_MAX_CNT1         (FE_PDMA_OFFSET + 0x64)
4195 +#define FE_RX_CALC_IDX1                (FE_PDMA_OFFSET + 0x68)
4196 +#define FE_RX_DRX_IDX1         (FE_PDMA_OFFSET + 0x6C)
4197 +
4198 +#define RT5350_SDM_CFG         (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
4199 +#define RT5350_SDM_RRING       (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
4200 +#define RT5350_SDM_TRING       (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
4201 +#define RT5350_SDM_MAC_ADRL    (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
4202 +#define RT5350_SDM_MAC_ADRH    (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
4203 +#define RT5350_SDM_TPCNT       (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4204 +#define RT5350_SDM_TBCNT       (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4205 +#define RT5350_SDM_RPCNT       (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4206 +#define RT5350_SDM_RBCNT       (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4207 +#define RT5350_SDM_CS_ERR      (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4208 +
4209 +#define RT5350_SDM_ICS_EN      BIT(16)
4210 +#define RT5350_SDM_TCS_EN      BIT(17)
4211 +#define RT5350_SDM_UCS_EN      BIT(18)
4212 +
4213 +
4214 +/* MDIO_CFG register bits */
4215 +#define FE_MDIO_CFG_AUTO_POLL_EN       BIT(29)
4216 +#define FE_MDIO_CFG_GP1_BP_EN          BIT(16)
4217 +#define FE_MDIO_CFG_GP1_FRC_EN         BIT(15)
4218 +#define FE_MDIO_CFG_GP1_SPEED_10       (0 << 13)
4219 +#define FE_MDIO_CFG_GP1_SPEED_100      (1 << 13)
4220 +#define FE_MDIO_CFG_GP1_SPEED_1000     (2 << 13)
4221 +#define FE_MDIO_CFG_GP1_DUPLEX         BIT(12)
4222 +#define FE_MDIO_CFG_GP1_FC_TX          BIT(11)
4223 +#define FE_MDIO_CFG_GP1_FC_RX          BIT(10)
4224 +#define FE_MDIO_CFG_GP1_LNK_DWN                BIT(9)
4225 +#define FE_MDIO_CFG_GP1_AN_FAIL                BIT(8)
4226 +#define FE_MDIO_CFG_MDC_CLK_DIV_1      (0 << 6)
4227 +#define FE_MDIO_CFG_MDC_CLK_DIV_2      (1 << 6)
4228 +#define FE_MDIO_CFG_MDC_CLK_DIV_4      (2 << 6)
4229 +#define FE_MDIO_CFG_MDC_CLK_DIV_8      (3 << 6)
4230 +#define FE_MDIO_CFG_TURBO_MII_FREQ     BIT(5)
4231 +#define FE_MDIO_CFG_TURBO_MII_MODE     BIT(4)
4232 +#define FE_MDIO_CFG_RX_CLK_SKEW_0      (0 << 2)
4233 +#define FE_MDIO_CFG_RX_CLK_SKEW_200    (1 << 2)
4234 +#define FE_MDIO_CFG_RX_CLK_SKEW_400    (2 << 2)
4235 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV    (3 << 2)
4236 +#define FE_MDIO_CFG_TX_CLK_SKEW_0      0
4237 +#define FE_MDIO_CFG_TX_CLK_SKEW_200    1
4238 +#define FE_MDIO_CFG_TX_CLK_SKEW_400    2
4239 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV    3
4240 +
4241 +/* uni-cast port */
4242 +#define FE_GDM1_ICS_EN         BIT(22)
4243 +#define FE_GDM1_TCS_EN         BIT(21)
4244 +#define FE_GDM1_UCS_EN         BIT(20)
4245 +#define FE_GDM1_JMB_EN         BIT(19)
4246 +#define FE_GDM1_STRPCRC                BIT(16)
4247 +#define FE_GDM1_UFRC_P_CPU     (0 << 12)
4248 +#define FE_GDM1_UFRC_P_GDMA1   (1 << 12)
4249 +#define FE_GDM1_UFRC_P_PPE     (6 << 12)
4250 +
4251 +/* checksums */
4252 +#define FE_ICS_GEN_EN          BIT(2)
4253 +#define FE_UCS_GEN_EN          BIT(1)
4254 +#define FE_TCS_GEN_EN          BIT(0)
4255 +
4256 +/* dma ring */
4257 +#define FE_PST_DRX_IDX0                BIT(16)
4258 +#define FE_PST_DTX_IDX3                BIT(3)
4259 +#define FE_PST_DTX_IDX2                BIT(2)
4260 +#define FE_PST_DTX_IDX1                BIT(1)
4261 +#define FE_PST_DTX_IDX0                BIT(0)
4262 +
4263 +#define FE_TX_WB_DDONE         BIT(6)
4264 +#define FE_RX_DMA_BUSY         BIT(3)
4265 +#define FE_TX_DMA_BUSY         BIT(1)
4266 +#define FE_RX_DMA_EN           BIT(2)
4267 +#define FE_TX_DMA_EN           BIT(0)
4268 +
4269 +#define FE_PDMA_SIZE_4DWORDS   (0 << 4)
4270 +#define FE_PDMA_SIZE_8DWORDS   (1 << 4)
4271 +#define FE_PDMA_SIZE_16DWORDS  (2 << 4)
4272 +
4273 +#define FE_US_CYC_CNT_MASK     0xff
4274 +#define FE_US_CYC_CNT_SHIFT    0x8
4275 +#define FE_US_CYC_CNT_DIVISOR  1000000
4276 +
4277 +#define RX_DMA_PLEN0(_x)       (((_x) >> 16) & 0x3fff)
4278 +#define RX_DMA_LSO             BIT(30)
4279 +#define RX_DMA_DONE            BIT(31)
4280 +#define RX_DMA_L4VALID         BIT(30)
4281 +
4282 +struct fe_rx_dma {
4283 +       unsigned int rxd1;
4284 +       unsigned int rxd2;
4285 +       unsigned int rxd3;
4286 +       unsigned int rxd4;
4287 +} __packed __aligned(4);
4288 +
4289 +#define TX_DMA_PLEN0_MASK      ((0x3fff) << 16)
4290 +#define TX_DMA_PLEN0(_x)       (((_x) & 0x3fff) << 16)
4291 +#define TX_DMA_LSO             BIT(30)
4292 +#define TX_DMA_DONE            BIT(31)
4293 +#define TX_DMA_QN(_x)          ((_x) << 16)
4294 +#define TX_DMA_PN(_x)          ((_x) << 24)
4295 +#define TX_DMA_QN_MASK         TX_DMA_QN(0x7)
4296 +#define TX_DMA_PN_MASK         TX_DMA_PN(0x7)
4297 +#define TX_DMA_CHKSUM          (0x7 << 29)
4298 +
4299 +struct fe_tx_dma {
4300 +       unsigned int txd1;
4301 +       unsigned int txd2;
4302 +       unsigned int txd3;
4303 +       unsigned int txd4;
4304 +} __packed __aligned(4);
4305 +
4306 +struct fe_priv;
4307 +
4308 +struct fe_phy {
4309 +       struct phy_device       *phy[8];
4310 +       struct device_node      *phy_node[8];
4311 +       const __be32            *phy_fixed[8];
4312 +       int                     duplex[8];
4313 +       int                     speed[8];
4314 +       spinlock_t              lock;
4315 +
4316 +       int (*connect)(struct fe_priv *priv);
4317 +       void (*disconnect)(struct fe_priv *priv);
4318 +       void (*start)(struct fe_priv *priv);
4319 +       void (*stop)(struct fe_priv *priv);
4320 +};
4321 +
4322 +struct fe_soc_data
4323 +{
4324 +       unsigned char mac[6];
4325 +       const u32 *reg_table;
4326 +
4327 +       void (*reset_fe)(void);
4328 +       void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4329 +       void (*fwd_config)(struct fe_priv *priv);
4330 +       void (*tx_dma)(struct fe_priv *priv, int idx, int len);
4331 +       void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4332 +       int (*switch_init)(struct fe_priv *priv);
4333 +       void (*port_init)(struct fe_priv *priv, struct device_node *port);
4334 +       int (*has_carrier)(struct fe_priv *priv);
4335 +       int (*mdio_init)(struct fe_priv *priv);
4336 +       void (*mdio_cleanup)(struct fe_priv *priv);
4337 +       int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4338 +       int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4339 +       void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4340 +
4341 +       void *swpriv;
4342 +       u32 pdma_glo_cfg;
4343 +       u32 rx_dly_int;
4344 +       u32 tx_dly_int;
4345 +       u32 checksum_bit;
4346 +
4347 +       int min_pkt_len;
4348 +};
4349 +
4350 +struct fe_priv
4351 +{
4352 +       spinlock_t                      page_lock;
4353 +
4354 +       struct fe_soc_data              *soc;
4355 +       struct net_device               *netdev;
4356 +       struct device                   *device;
4357 +       unsigned long                   sysclk;
4358 +
4359 +       struct fe_rx_dma                *rx_dma;
4360 +       struct sk_buff                  *rx_skb[NUM_DMA_DESC];
4361 +        struct napi_struct             rx_napi;
4362 +       dma_addr_t                      rx_phys;
4363 +
4364 +       struct fe_tx_dma                *tx_dma;
4365 +       struct sk_buff                  *tx_skb[NUM_DMA_DESC];
4366 +        struct napi_struct             tx_napi;
4367 +       dma_addr_t                      tx_phys;
4368 +       unsigned int                    tx_free_idx;
4369 +
4370 +       struct fe_phy                   *phy;
4371 +       struct mii_bus                  *mii_bus;
4372 +       int                             mii_irq[PHY_MAX_ADDR];
4373 +
4374 +       int                             link[8];
4375 +};
4376 +
4377 +extern const struct of_device_id of_fe_match[];
4378 +
4379 +void fe_w32(u32 val, unsigned reg);
4380 +u32 fe_r32(unsigned reg);
4381 +
4382 +#endif /* FE_ETH_H */
4383 diff --git a/drivers/net/ethernet/ralink/soc_mt7620.c b/drivers/net/ethernet/ralink/soc_mt7620.c
4384 new file mode 100644
4385 index 0000000..55e303f
4386 --- /dev/null
4387 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
4388 @@ -0,0 +1,111 @@
4389 +/*
4390 + *   This program is free software; you can redistribute it and/or modify
4391 + *   it under the terms of the GNU General Public License as published by
4392 + *   the Free Software Foundation; version 2 of the License
4393 + *
4394 + *   This program is distributed in the hope that it will be useful,
4395 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4396 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4397 + *   GNU General Public License for more details.
4398 + *
4399 + *   You should have received a copy of the GNU General Public License
4400 + *   along with this program; if not, write to the Free Software
4401 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4402 + *
4403 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4404 + */
4405 +
4406 +#include <linux/module.h>
4407 +#include <linux/platform_device.h>
4408 +
4409 +#include <asm/mach-ralink/ralink_regs.h>
4410 +
4411 +#include "ralink_soc_eth.h"
4412 +#include "gsw_mt7620a.h"
4413 +
4414 +#define MT7620A_CDMA_CSG_CFG   0x400
4415 +#define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
4416 +#define MT7620A_DMA_2B_OFFSET  BIT(31)
4417 +#define MT7620A_RESET_FE       BIT(21)
4418 +#define MT7620A_RESET_ESW      BIT(23)
4419 +#define MT7620_L4_VALID                BIT(23)
4420 +
4421 +#define SYSC_REG_RESET_CTRL     0x34
4422 +#define MAX_RX_LENGTH           1536
4423 +
4424 +#define CDMA_ICS_EN            BIT(2)
4425 +#define CDMA_UCS_EN            BIT(1)
4426 +#define CDMA_TCS_EN            BIT(0)
4427 +
4428 +#define GDMA_ICS_EN            BIT(22)
4429 +#define GDMA_TCS_EN            BIT(21)
4430 +#define GDMA_UCS_EN            BIT(20)
4431 +
4432 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4433 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4434 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4435 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4436 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4437 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4438 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4439 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4440 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4441 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4442 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4443 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4444 +       [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4445 +};
4446 +
4447 +static void mt7620_fe_reset(void)
4448 +{
4449 +       rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4450 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4451 +}
4452 +
4453 +static void mt7620_fwd_config(struct fe_priv *priv)
4454 +{
4455 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4456 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4457 +       fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4458 +}
4459 +
4460 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len)
4461 +{
4462 +       if (len)
4463 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4464 +       else
4465 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4466 +}
4467 +
4468 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4469 +{
4470 +       priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4471 +}
4472 +
4473 +static struct fe_soc_data mt7620_data = {
4474 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4475 +       .reset_fe = mt7620_fe_reset,
4476 +       .set_mac = mt7620_set_mac,
4477 +       .fwd_config = mt7620_fwd_config,
4478 +       .tx_dma = mt7620_tx_dma,
4479 +       .rx_dma = mt7620_rx_dma,
4480 +       .switch_init = mt7620_gsw_probe,
4481 +       .port_init = mt7620_port_init,
4482 +       .min_pkt_len = 0,
4483 +       .reg_table = rt5350_reg_table,
4484 +       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4485 +       .rx_dly_int = RT5350_RX_DLY_INT,
4486 +       .tx_dly_int = RT5350_TX_DLY_INT,
4487 +       .checksum_bit = MT7620_L4_VALID,
4488 +       .has_carrier = mt7620a_has_carrier,
4489 +       .mdio_read = mt7620_mdio_read,
4490 +       .mdio_write = mt7620_mdio_write,
4491 +       .mdio_adjust_link = mt7620_mdio_link_adjust,
4492 +};
4493 +
4494 +const struct of_device_id of_fe_match[] = {
4495 +       { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4496 +       {},
4497 +};
4498 +
4499 +MODULE_DEVICE_TABLE(of, of_fe_match);
4500 diff --git a/drivers/net/ethernet/ralink/soc_rt2880.c b/drivers/net/ethernet/ralink/soc_rt2880.c
4501 new file mode 100644
4502 index 0000000..fdbd118
4503 --- /dev/null
4504 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4505 @@ -0,0 +1,51 @@
4506 +/*
4507 + *   This program is free software; you can redistribute it and/or modify
4508 + *   it under the terms of the GNU General Public License as published by
4509 + *   the Free Software Foundation; version 2 of the License
4510 + *
4511 + *   This program is distributed in the hope that it will be useful,
4512 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4513 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4514 + *   GNU General Public License for more details.
4515 + *
4516 + *   You should have received a copy of the GNU General Public License
4517 + *   along with this program; if not, write to the Free Software
4518 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4519 + *
4520 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4521 + */
4522 +
4523 +#include <linux/module.h>
4524 +
4525 +#include <asm/mach-ralink/ralink_regs.h>
4526 +
4527 +#include "ralink_soc_eth.h"
4528 +#include "mdio_rt2880.h"
4529 +
4530 +#define SYSC_REG_RESET_CTRL            0x034
4531 +#define RT2880_RESET_FE                        BIT(18)
4532 +
4533 +void rt2880_fe_reset(void)
4534 +{
4535 +       rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4536 +}
4537 +
4538 +struct fe_soc_data rt2880_data = {
4539 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4540 +       .reset_fe = rt2880_fe_reset,
4541 +       .min_pkt_len = 64,
4542 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4543 +       .checksum_bit = RX_DMA_L4VALID,
4544 +       .rx_dly_int = FE_RX_DLY_INT,
4545 +       .tx_dly_int = FE_TX_DLY_INT,
4546 +       .mdio_read = rt2880_mdio_read,
4547 +       .mdio_write = rt2880_mdio_write,
4548 +       .mdio_link_adjust = rt2880_mdio_link_adjust,
4549 +};
4550 +
4551 +const struct of_device_id of_fe_match[] = {
4552 +       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4553 +       {},
4554 +};
4555 +
4556 +MODULE_DEVICE_TABLE(of, of_fe_match);
4557 diff --git a/drivers/net/ethernet/ralink/soc_rt305x.c b/drivers/net/ethernet/ralink/soc_rt305x.c
4558 new file mode 100644
4559 index 0000000..c43d3f9
4560 --- /dev/null
4561 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4562 @@ -0,0 +1,102 @@
4563 +/*
4564 + *   This program is free software; you can redistribute it and/or modify
4565 + *   it under the terms of the GNU General Public License as published by
4566 + *   the Free Software Foundation; version 2 of the License
4567 + *
4568 + *   This program is distributed in the hope that it will be useful,
4569 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4570 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4571 + *   GNU General Public License for more details.
4572 + *
4573 + *   You should have received a copy of the GNU General Public License
4574 + *   along with this program; if not, write to the Free Software
4575 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4576 + *
4577 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4578 + */
4579 +
4580 +#include <linux/module.h>
4581 +
4582 +#include <asm/mach-ralink/ralink_regs.h>
4583 +
4584 +#include "ralink_soc_eth.h"
4585 +
4586 +#define RT305X_RESET_FE         BIT(21)
4587 +#define RT305X_RESET_ESW        BIT(23)
4588 +#define SYSC_REG_RESET_CTRL     0x034
4589 +
4590 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4591 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4592 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4593 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4594 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4595 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4596 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4597 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4598 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4599 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4600 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4601 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4602 +       [FE_REG_FE_DMA_VID_BASE] = 0,
4603 +};
4604 +
4605 +static void rt305x_fe_reset(void)
4606 +{
4607 +       rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4608 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4609 +}
4610 +
4611 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4612 +{
4613 +       unsigned long flags;
4614 +
4615 +       spin_lock_irqsave(&priv->page_lock, flags);
4616 +       fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4617 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4618 +               RT5350_SDM_MAC_ADRL);
4619 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4620 +}
4621 +
4622 +static void rt5350_fwd_config(struct fe_priv *priv)
4623 +{
4624 +       fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4625 +       fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4626 +               RT5350_SDM_CFG);
4627 +}
4628 +
4629 +static void rt5350_fe_reset(void)
4630 +{
4631 +       rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4632 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4633 +}
4634 +
4635 +static struct fe_soc_data rt3050_data = {
4636 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4637 +       .reset_fe = rt305x_fe_reset,
4638 +       .min_pkt_len = 64,
4639 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4640 +       .checksum_bit = RX_DMA_L4VALID,
4641 +       .rx_dly_int = FE_RX_DLY_INT,
4642 +       .tx_dly_int = FE_TX_DLY_INT,
4643 +};
4644 +
4645 +static struct fe_soc_data rt5350_data = {
4646 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4647 +       .reg_table = rt5350_reg_table,
4648 +       .reset_fe = rt5350_fe_reset,
4649 +       .set_mac = rt5350_set_mac,
4650 +       .fwd_config = rt5350_fwd_config,
4651 +       .min_pkt_len = 64,
4652 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4653 +       .checksum_bit = RX_DMA_L4VALID,
4654 +       .rx_dly_int = RT5350_RX_DLY_INT,
4655 +       .tx_dly_int = RT5350_TX_DLY_INT,
4656 +};
4657 +
4658 +const struct of_device_id of_fe_match[] = {
4659 +       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4660 +       { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4661 +       {},
4662 +};
4663 +
4664 +MODULE_DEVICE_TABLE(of, of_fe_match);
4665 diff --git a/drivers/net/ethernet/ralink/soc_rt3883.c b/drivers/net/ethernet/ralink/soc_rt3883.c
4666 new file mode 100644
4667 index 0000000..3886be1
4668 --- /dev/null
4669 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
4670 @@ -0,0 +1,59 @@
4671 +/*
4672 + *   This program is free software; you can redistribute it and/or modify
4673 + *   it under the terms of the GNU General Public License as published by
4674 + *   the Free Software Foundation; version 2 of the License
4675 + *
4676 + *   This program is distributed in the hope that it will be useful,
4677 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4678 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4679 + *   GNU General Public License for more details.
4680 + *
4681 + *   You should have received a copy of the GNU General Public License
4682 + *   along with this program; if not, write to the Free Software
4683 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4684 + *
4685 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4686 + */
4687 +
4688 +#include <linux/module.h>
4689 +
4690 +#include <asm/mach-ralink/ralink_regs.h>
4691 +
4692 +#include "ralink_soc_eth.h"
4693 +#include "mdio_rt2880.h"
4694 +
4695 +#define RT3883_SYSC_REG_RSTCTRL                0x34
4696 +#define RT3883_RSTCTRL_FE              BIT(21)
4697 +
4698 +static void rt3883_fe_reset(void)
4699 +{
4700 +       u32 t;
4701 +
4702 +       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
4703 +       t |= RT3883_RSTCTRL_FE;
4704 +       rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
4705 +
4706 +       t &= ~RT3883_RSTCTRL_FE;
4707 +       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
4708 +}
4709 +
4710 +static struct fe_soc_data rt3883_data = {
4711 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4712 +       .reset_fe = rt3883_fe_reset,
4713 +       .min_pkt_len = 64,
4714 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4715 +       .rx_dly_int = FE_RX_DLY_INT,
4716 +       .tx_dly_int = FE_TX_DLY_INT,
4717 +       .checksum_bit = RX_DMA_L4VALID,
4718 +       .mdio_read = rt2880_mdio_read,
4719 +       .mdio_write = rt2880_mdio_write,
4720 +       .mdio_link_adjust = rt2880_mdio_link_adjust,
4721 +};
4722 +
4723 +const struct of_device_id of_fe_match[] = {
4724 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
4725 +       {},
4726 +};
4727 +
4728 +MODULE_DEVICE_TABLE(of, of_fe_match);
4729 +
4730 --
4731 1.7.10.4
4732