target/linux/ramips/patches-3.8/0065-watchdog-adds-ralink-wdt.patch

   1 From 8eaa4bef40d38a4954389a2552504ea2d1c4a68a Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:23:07 +0200
   4 Subject: [PATCH 65/79] watchdog: adds ralink wdt
   5
   6 Adds the watchdog driver for ralink SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/ralink/mt7620.c     |    1 +
  11  drivers/watchdog/Kconfig      |    7 ++
  12  drivers/watchdog/Makefile     |    1 +
  13  drivers/watchdog/rt2880_wdt.c |  208 +++++++++++++++++++++++++++++++++++++++++
  14  4 files changed, 217 insertions(+)
  15  create mode 100644 drivers/watchdog/rt2880_wdt.c
  16
  17 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
  18 index 08c96db6..4956d96 100644
  19 --- a/arch/mips/ralink/mt7620.c
  20 +++ b/arch/mips/ralink/mt7620.c
  21 @@ -182,6 +182,7 @@ void __init ralink_clk_init(void)
  22
  23         ralink_clk_add("cpu", cpu_rate);
  24         ralink_clk_add("10000100.timer", 40000000);
  25 +       ralink_clk_add("10000120.watchdog", 40000000);
  26         ralink_clk_add("10000500.uart", 40000000);
  27         ralink_clk_add("10000b00.spi", 40000000);
  28         ralink_clk_add("10000c00.uartlite", 40000000);
  29 diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
  30 index 7f809fd..c8c7454 100644
  31 --- a/drivers/watchdog/Kconfig
  32 +++ b/drivers/watchdog/Kconfig
  33 @@ -1076,6 +1076,13 @@ config LANTIQ_WDT
  34         help
  35           Hardware driver for the Lantiq SoC Watchdog Timer.
  36
  37 +config RALINK_WDT
  38 +       tristate "Ralink SoC watchdog"
  39 +       select WATCHDOG_CORE
  40 +       depends on RALINK
  41 +       help
  42 +         Hardware driver for the Ralink SoC Watchdog Timer.
  43 +
  44  # PARISC Architecture
  45
  46  # POWERPC Architecture
  47 diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
  48 index 97bbdb3a..0203784 100644
  49 --- a/drivers/watchdog/Makefile
  50 +++ b/drivers/watchdog/Makefile
  51 @@ -132,6 +132,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
  52  obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
  53  octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
  54  obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
  55 +obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
  56
  57  # PARISC Architecture
  58
  59 diff --git a/drivers/watchdog/rt2880_wdt.c b/drivers/watchdog/rt2880_wdt.c
  60 new file mode 100644
  61 index 0000000..3df65a4
  62 --- /dev/null
  63 +++ b/drivers/watchdog/rt2880_wdt.c
  64 @@ -0,0 +1,208 @@
  65 +/*
  66 + * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
  67 + *
  68 + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  69 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  70 + *
  71 + * This driver was based on: drivers/watchdog/softdog.c
  72 + *
  73 + * This program is free software; you can redistribute it and/or modify it
  74 + * under the terms of the GNU General Public License version 2 as published
  75 + * by the Free Software Foundation.
  76 + */
  77 +
  78 +#include <linux/clk.h>
  79 +#include <linux/reset.h>
  80 +#include <linux/module.h>
  81 +#include <linux/kernel.h>
  82 +#include <linux/watchdog.h>
  83 +#include <linux/miscdevice.h>
  84 +#include <linux/moduleparam.h>
  85 +#include <linux/platform_device.h>
  86 +
  87 +#include <asm/mach-ralink/ralink_regs.h>
  88 +
  89 +#define SYSC_RSTSTAT                   0x38
  90 +#define WDT_RST_CAUSE                  BIT(1)
  91 +
  92 +#define RALINK_WDT_TIMEOUT             30
  93 +#define RALINK_WDT_PRESCALE            65536
  94 +
  95 +#define TIMER_REG_TMR1LOAD             0x00
  96 +#define TIMER_REG_TMR1CTL              0x08
  97 +
  98 +#define TMRSTAT_TMR1RST                        BIT(5)
  99 +
 100 +#define TMR1CTL_ENABLE                 BIT(7)
 101 +#define TMR1CTL_MODE_SHIFT             4
 102 +#define TMR1CTL_MODE_MASK              0x3
 103 +#define TMR1CTL_MODE_FREE_RUNNING      0x0
 104 +#define TMR1CTL_MODE_PERIODIC          0x1
 105 +#define TMR1CTL_MODE_TIMEOUT           0x2
 106 +#define TMR1CTL_MODE_WDT               0x3
 107 +#define TMR1CTL_PRESCALE_MASK          0xf
 108 +#define TMR1CTL_PRESCALE_65536         0xf
 109 +
 110 +static struct clk *rt288x_wdt_clk;
 111 +static unsigned long rt288x_wdt_freq;
 112 +static void __iomem *rt288x_wdt_base;
 113 +
 114 +static bool nowayout = WATCHDOG_NOWAYOUT;
 115 +module_param(nowayout, bool, 0);
 116 +MODULE_PARM_DESC(nowayout,
 117 +               "Watchdog cannot be stopped once started (default="
 118 +               __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 119 +
 120 +static inline void rt_wdt_w32(unsigned reg, u32 val)
 121 +{
 122 +       iowrite32(val, rt288x_wdt_base + reg);
 123 +}
 124 +
 125 +static inline u32 rt_wdt_r32(unsigned reg)
 126 +{
 127 +       return ioread32(rt288x_wdt_base + reg);
 128 +}
 129 +
 130 +static int rt288x_wdt_ping(struct watchdog_device *w)
 131 +{
 132 +        rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
 133 +
 134 +       return 0;
 135 +}
 136 +
 137 +static int rt288x_wdt_start(struct watchdog_device *w)
 138 +{
 139 +       u32 t;
 140 +
 141 +       t = rt_wdt_r32(TIMER_REG_TMR1CTL);
 142 +       t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
 143 +               TMR1CTL_PRESCALE_MASK);
 144 +       t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
 145 +               TMR1CTL_PRESCALE_65536);
 146 +       rt_wdt_w32(TIMER_REG_TMR1CTL, t);
 147 +
 148 +       rt288x_wdt_ping(w);
 149 +
 150 +       t = rt_wdt_r32(TIMER_REG_TMR1CTL);
 151 +       t |= TMR1CTL_ENABLE;
 152 +       rt_wdt_w32(TIMER_REG_TMR1CTL, t);
 153 +
 154 +       return 0;
 155 +}
 156 +
 157 +static int rt288x_wdt_stop(struct watchdog_device *w)
 158 +{
 159 +       u32 t;
 160 +
 161 +       rt288x_wdt_ping(w);
 162 +
 163 +       t = rt_wdt_r32(TIMER_REG_TMR1CTL);
 164 +       t &= ~TMR1CTL_ENABLE;
 165 +       rt_wdt_w32(TIMER_REG_TMR1CTL, t);
 166 +
 167 +       return 0;
 168 +}
 169 +
 170 +static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
 171 +{
 172 +       w->timeout = t;
 173 +       rt288x_wdt_ping(w);
 174 +
 175 +       return 0;
 176 +}
 177 +
 178 +static int rt288x_wdt_bootcause(void)
 179 +{
 180 +       if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
 181 +               return WDIOF_CARDRESET;
 182 +
 183 +       return 0;
 184 +}
 185 +
 186 +static struct watchdog_info rt288x_wdt_info = {
 187 +       .identity = "Ralink Watchdog",
 188 +       .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
 189 +};
 190 +
 191 +static struct watchdog_ops rt288x_wdt_ops = {
 192 +       .owner = THIS_MODULE,
 193 +       .start = rt288x_wdt_start,
 194 +       .stop = rt288x_wdt_stop,
 195 +       .ping = rt288x_wdt_ping,
 196 +       .set_timeout = rt288x_wdt_set_timeout,
 197 +};
 198 +
 199 +static struct watchdog_device rt288x_wdt_dev = {
 200 +       .info = &rt288x_wdt_info,
 201 +       .ops = &rt288x_wdt_ops,
 202 +       .min_timeout = 1,
 203 +};
 204 +
 205 +static int rt288x_wdt_probe(struct platform_device *pdev)
 206 +{
 207 +       struct resource *res;
 208 +       int ret;
 209 +
 210 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 211 +        rt288x_wdt_base = devm_request_and_ioremap(&pdev->dev, res);
 212 +       if (IS_ERR(rt288x_wdt_base))
 213 +               return PTR_ERR(rt288x_wdt_base);
 214 +
 215 +       rt288x_wdt_clk = devm_clk_get(&pdev->dev, NULL);
 216 +       if (IS_ERR(rt288x_wdt_clk))
 217 +               return PTR_ERR(rt288x_wdt_clk);
 218 +
 219 +       device_reset(&pdev->dev);
 220 +
 221 +       rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
 222 +
 223 +       rt288x_wdt_dev.dev = &pdev->dev;
 224 +       rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
 225 +
 226 +       rt288x_wdt_dev.timeout = RALINK_WDT_TIMEOUT;
 227 +       rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
 228 +
 229 +       watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
 230 +
 231 +       ret = watchdog_register_device(&rt288x_wdt_dev);
 232 +       if (!ret)
 233 +               dev_info(&pdev->dev, "Initialized\n");
 234 +
 235 +       return 0;
 236 +}
 237 +
 238 +static int rt288x_wdt_remove(struct platform_device *pdev)
 239 +{
 240 +       watchdog_unregister_device(&rt288x_wdt_dev);
 241 +
 242 +       return 0;
 243 +}
 244 +
 245 +static void rt288x_wdt_shutdown(struct platform_device *pdev)
 246 +{
 247 +       rt288x_wdt_stop(&rt288x_wdt_dev);
 248 +}
 249 +
 250 +static const struct of_device_id rt288x_wdt_match[] = {
 251 +       { .compatible = "ralink,rt2880-wdt" },
 252 +       {},
 253 +};
 254 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
 255 +
 256 +static struct platform_driver rt288x_wdt_driver = {
 257 +       .probe          = rt288x_wdt_probe,
 258 +       .remove         = rt288x_wdt_remove,
 259 +       .shutdown       = rt288x_wdt_shutdown,
 260 +       .driver         = {
 261 +               .name           = KBUILD_MODNAME,
 262 +               .owner          = THIS_MODULE,
 263 +               .of_match_table = rt288x_wdt_match,
 264 +       },
 265 +};
 266 +
 267 +module_platform_driver(rt288x_wdt_driver);
 268 +
 269 +MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
 270 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
 271 +MODULE_LICENSE("GPL v2");
 272 +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 273 --
 274 1.7.10.4
 275