target/linux/ramips/patches-3.8/0013-MIPS-add-irqdomain-support-for-the-CPU-IRQ-controlle.patch

   1 From 65e39f763eeca6fb93f48ed5a9b296277a543429 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Thu, 31 Jan 2013 12:20:43 +0000
   4 Subject: [PATCH 13/79] MIPS: add irqdomain support for the CPU IRQ controller
   5
   6 Add code to load a irq_domain for the MIPS IRQ controller from a devicetree
   7 file.
   8
   9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Acked-by: David Daney <david.daney@cavium.com>
  12 Patchwork: http://patchwork.linux-mips.org/patch/4902/
  13 ---
  14  arch/mips/include/asm/irq_cpu.h |    6 ++++++
  15  arch/mips/kernel/irq_cpu.c      |   42 +++++++++++++++++++++++++++++++++++++++
  16  2 files changed, 48 insertions(+)
  17
  18 diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
  19 index ef6a07c..3f11fdb 100644
  20 --- a/arch/mips/include/asm/irq_cpu.h
  21 +++ b/arch/mips/include/asm/irq_cpu.h
  22 @@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
  23  extern void rm7k_cpu_irq_init(void);
  24  extern void rm9k_cpu_irq_init(void);
  25
  26 +#ifdef CONFIG_IRQ_DOMAIN
  27 +struct device_node;
  28 +extern int mips_cpu_intc_init(struct device_node *of_node,
  29 +                             struct device_node *parent);
  30 +#endif
  31 +
  32  #endif /* _ASM_IRQ_CPU_H */
  33 diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
  34 index 972263b..49bc9ca 100644
  35 --- a/arch/mips/kernel/irq_cpu.c
  36 +++ b/arch/mips/kernel/irq_cpu.c
  37 @@ -31,6 +31,7 @@
  38  #include <linux/interrupt.h>
  39  #include <linux/kernel.h>
  40  #include <linux/irq.h>
  41 +#include <linux/irqdomain.h>
  42
  43  #include <asm/irq_cpu.h>
  44  #include <asm/mipsregs.h>
  45 @@ -113,3 +114,44 @@ void __init mips_cpu_irq_init(void)
  46                 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
  47                                          handle_percpu_irq);
  48  }
  49 +
  50 +#ifdef CONFIG_IRQ_DOMAIN
  51 +static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
  52 +                            irq_hw_number_t hw)
  53 +{
  54 +       static struct irq_chip *chip;
  55 +
  56 +       if (hw < 2 && cpu_has_mipsmt) {
  57 +               /* Software interrupts are used for MT/CMT IPI */
  58 +               chip = &mips_mt_cpu_irq_controller;
  59 +       } else {
  60 +               chip = &mips_cpu_irq_controller;
  61 +       }
  62 +
  63 +       irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
  64 +
  65 +       return 0;
  66 +}
  67 +
  68 +static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
  69 +       .map = mips_cpu_intc_map,
  70 +       .xlate = irq_domain_xlate_onecell,
  71 +};
  72 +
  73 +int __init mips_cpu_intc_init(struct device_node *of_node,
  74 +                             struct device_node *parent)
  75 +{
  76 +       struct irq_domain *domain;
  77 +
  78 +       /* Mask interrupts. */
  79 +       clear_c0_status(ST0_IM);
  80 +       clear_c0_cause(CAUSEF_IP);
  81 +
  82 +       domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
  83 +                                      &mips_cpu_intc_irq_domain_ops, NULL);
  84 +       if (!domain)
  85 +               panic("Failed to add irqdomain for MIPS CPU\n");
  86 +
  87 +       return 0;
  88 +}
  89 +#endif /* CONFIG_IRQ_DOMAIN */
  90 --
  91 1.7.10.4
  92