target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch

   1 From e410b0069ee7c318a5b556f39b8b16814330a208 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 24 Jan 2014 17:01:17 +0100
   4 Subject: [PATCH 15/57] MIPS: ralink: cleanup early_printk
   5
   6 Add support for the new MT7621/8 SoC and kill ifdefs.
   7 Cleanup some whitespace error while we are at it.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/ralink/early_printk.c |   45 ++++++++++++++++++++++++++-------------
  12  1 file changed, 30 insertions(+), 15 deletions(-)
  13
  14 --- a/arch/mips/ralink/early_printk.c
  15 +++ b/arch/mips/ralink/early_printk.c
  16 @@ -12,21 +12,26 @@
  17  #include <asm/addrspace.h>
  18
  19  #ifdef CONFIG_SOC_RT288X
  20 -#define EARLY_UART_BASE         0x300c00
  21 +#define EARLY_UART_BASE                0x300c00
  22 +#define CHIPID_BASE            0x300004
  23 +#elif defined(CONFIG_SOC_MT7621)
  24 +#define EARLY_UART_BASE                0x1E000c00
  25 +#define CHIPID_BASE            0x1E000004
  26  #else
  27 -#define EARLY_UART_BASE         0x10000c00
  28 +#define EARLY_UART_BASE                0x10000c00
  29 +#define CHIPID_BASE            0x10000004
  30  #endif
  31
  32 -#define UART_REG_RX             0x00
  33 -#define UART_REG_TX             0x04
  34 -#define UART_REG_IER            0x08
  35 -#define UART_REG_IIR            0x0c
  36 -#define UART_REG_FCR            0x10
  37 -#define UART_REG_LCR            0x14
  38 -#define UART_REG_MCR            0x18
  39 -#define UART_REG_LSR            0x1c
  40 +#define MT7628_CHIP_NAME1      0x20203832
  41 +
  42 +#define UART_REG_TX            0x04
  43 +#define UART_REG_LCR           0x0c
  44 +#define UART_REG_LSR           0x14
  45 +#define UART_REG_LSR_RT2880    0x1c
  46
  47  static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
  48 +static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
  49 +static int init_complete;
  50
  51  static inline void uart_w32(u32 val, unsigned reg)
  52  {
  53 @@ -38,11 +43,46 @@ static inline u32 uart_r32(unsigned reg)
  54         return __raw_readl(uart_membase + reg);
  55  }
  56
  57 +static inline int soc_is_mt7628(void)
  58 +{
  59 +       return IS_ENABLED(CONFIG_SOC_MT7620) &&
  60 +               (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
  61 +}
  62 +
  63 +static inline void find_uart_base(void)
  64 +{
  65 +       int i;
  66 +
  67 +       if (!soc_is_mt7628())
  68 +               return;
  69 +
  70 +       for (i = 0; i < 3; i++) {
  71 +               u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
  72 +
  73 +               if (!reg)
  74 +                       continue;
  75 +
  76 +               uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i));
  77 +               break;
  78 +       }
  79 +}
  80 +
  81  void prom_putchar(unsigned char ch)
  82  {
  83 -       while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
  84 -               ;
  85 -       uart_w32(ch, UART_REG_TX);
  86 -       while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
  87 -               ;
  88 +       if (!init_complete) {
  89 +               find_uart_base();
  90 +               init_complete = 1;
  91 +       }
  92 +
  93 +       if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
  94 +               uart_w32(ch, UART_TX);
  95 +               while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
  96 +                       ;
  97 +       } else {
  98 +               while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
  99 +                       ;
 100 +               uart_w32(ch, UART_REG_TX);
 101 +               while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
 102 +                       ;
 103 +       }
 104  }