target/linux/ramips/patches-3.10/0118-NET-MIPS-add-ralink-SoC-ethernet-driver.patch

   1 From b7d9374aee4b47a76dadaf1fe7f6838087c9c62d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:20:03 +0200
   4 Subject: [PATCH 118/133] NET: MIPS: add ralink SoC ethernet driver
   5
   6 Add support for Ralink FE and ESW.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
  11  arch/mips/ralink/rt305x.c                          |    1 +
  12  drivers/net/ethernet/Kconfig                       |    1 +
  13  drivers/net/ethernet/Makefile                      |    1 +
  14  drivers/net/ethernet/ralink/Kconfig                |   32 +
  15  drivers/net/ethernet/ralink/Makefile               |   18 +
  16  drivers/net/ethernet/ralink/esw_rt3052.c           | 1463 ++++++++++++++++++++
  17  drivers/net/ethernet/ralink/esw_rt3052.h           |   32 +
  18  drivers/net/ethernet/ralink/gsw_mt7620a.c          |  566 ++++++++
  19  drivers/net/ethernet/ralink/gsw_mt7620a.h          |   30 +
  20  drivers/net/ethernet/ralink/mdio.c                 |  244 ++++
  21  drivers/net/ethernet/ralink/mdio.h                 |   29 +
  22  drivers/net/ethernet/ralink/mdio_rt2880.c          |  232 ++++
  23  drivers/net/ethernet/ralink/mdio_rt2880.h          |   26 +
  24  drivers/net/ethernet/ralink/mt7530.c               |  467 +++++++
  25  drivers/net/ethernet/ralink/mt7530.h               |   20 +
  26  drivers/net/ethernet/ralink/ralink_soc_eth.c       |  845 +++++++++++
  27  drivers/net/ethernet/ralink/ralink_soc_eth.h       |  384 +++++
  28  drivers/net/ethernet/ralink/soc_mt7620.c           |  172 +++
  29  drivers/net/ethernet/ralink/soc_rt2880.c           |   51 +
  30  drivers/net/ethernet/ralink/soc_rt305x.c           |  113 ++
  31  drivers/net/ethernet/ralink/soc_rt3883.c           |   60 +
  32  22 files changed, 4814 insertions(+)
  33  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  34  create mode 100644 drivers/net/ethernet/ralink/Kconfig
  35  create mode 100644 drivers/net/ethernet/ralink/Makefile
  36  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
  37  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
  38  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
  39  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
  40  create mode 100644 drivers/net/ethernet/ralink/mdio.c
  41  create mode 100644 drivers/net/ethernet/ralink/mdio.h
  42  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
  43  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
  44  create mode 100644 drivers/net/ethernet/ralink/mt7530.c
  45  create mode 100644 drivers/net/ethernet/ralink/mt7530.h
  46  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
  47  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
  48  create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
  49  create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
  50  create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
  51  create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
  52
  53 --- /dev/null
  54 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  55 @@ -0,0 +1,27 @@
  56 +/*
  57 + *  Ralink RT305x SoC platform device registration
  58 + *
  59 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  60 + *
  61 + *  This program is free software; you can redistribute it and/or modify it
  62 + *  under the terms of the GNU General Public License version 2 as published
  63 + *  by the Free Software Foundation.
  64 + */
  65 +
  66 +#ifndef _RT305X_ESW_PLATFORM_H
  67 +#define _RT305X_ESW_PLATFORM_H
  68 +
  69 +enum {
  70 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
  71 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
  72 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
  73 +};
  74 +
  75 +struct rt305x_esw_platform_data
  76 +{
  77 +       u8 vlan_config;
  78 +       u32 reg_initval_fct2;
  79 +       u32 reg_initval_fpa2;
  80 +};
  81 +
  82 +#endif /* _RT305X_ESW_PLATFORM_H */
  83 --- a/arch/mips/ralink/rt305x.c
  84 +++ b/arch/mips/ralink/rt305x.c
  85 @@ -194,6 +194,7 @@ void __init ralink_clk_init(void)
  86         }
  87
  88         ralink_clk_add("cpu", cpu_rate);
  89 +       ralink_clk_add("sys", sys_rate);
  90         ralink_clk_add("10000b00.spi", sys_rate);
  91         ralink_clk_add("10000100.timer", wdt_rate);
  92         ralink_clk_add("10000120.watchdog", wdt_rate);
  93 --- a/drivers/net/ethernet/Kconfig
  94 +++ b/drivers/net/ethernet/Kconfig
  95 @@ -135,6 +135,7 @@ config ETHOC
  96  source "drivers/net/ethernet/packetengines/Kconfig"
  97  source "drivers/net/ethernet/pasemi/Kconfig"
  98  source "drivers/net/ethernet/qlogic/Kconfig"
  99 +source "drivers/net/ethernet/ralink/Kconfig"
 100  source "drivers/net/ethernet/realtek/Kconfig"
 101  source "drivers/net/ethernet/renesas/Kconfig"
 102  source "drivers/net/ethernet/rdc/Kconfig"
 103 --- a/drivers/net/ethernet/Makefile
 104 +++ b/drivers/net/ethernet/Makefile
 105 @@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
 106  obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
 107  obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
 108  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
 109 +obj-$(CONFIG_NET_RALINK) += ralink/
 110  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
 111  obj-$(CONFIG_SH_ETH) += renesas/
 112  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
 113 --- /dev/null
 114 +++ b/drivers/net/ethernet/ralink/Kconfig
 115 @@ -0,0 +1,32 @@
 116 +config NET_RALINK
 117 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
 118 +       depends on RALINK
 119 +       help
 120 +         This driver supports the ethernet mac inside the ralink wisocs
 121 +
 122 +if NET_RALINK
 123 +
 124 +config NET_RALINK_MDIO
 125 +       def_bool NET_RALINK
 126 +       depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
 127 +       select PHYLIB
 128 +
 129 +config NET_RALINK_MDIO_RT2880
 130 +       def_bool NET_RALINK
 131 +       depends on (SOC_RT288X || SOC_RT3883)
 132 +       select NET_RALINK_MDIO
 133 +
 134 +config NET_RALINK_ESW_RT3052
 135 +       def_bool NET_RALINK
 136 +       depends on SOC_RT305X
 137 +       select PHYLIB
 138 +       select SWCONFIG
 139 +
 140 +config NET_RALINK_GSW_MT7620
 141 +       def_bool NET_RALINK
 142 +       depends on SOC_MT7620
 143 +       select INET_LRO
 144 +       select NET_RALINK_MDIO
 145 +       select PHYLIB
 146 +       select SWCONFIG
 147 +endif
 148 --- /dev/null
 149 +++ b/drivers/net/ethernet/ralink/Makefile
 150 @@ -0,0 +1,18 @@
 151 +#
 152 +# Makefile for the Ralink SoCs built-in ethernet macs
 153 +#
 154 +
 155 +ralink-eth-y                                   += ralink_soc_eth.o
 156 +
 157 +ralink-eth-$(CONFIG_NET_RALINK_MDIO)           += mdio.o
 158 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)    += mdio_rt2880.o
 159 +
 160 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052)     += esw_rt3052.o
 161 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620)     += gsw_mt7620a.o mt7530.o
 162 +
 163 +ralink-eth-$(CONFIG_SOC_RT288X)                        += soc_rt2880.o
 164 +ralink-eth-$(CONFIG_SOC_RT305X)                        += soc_rt305x.o
 165 +ralink-eth-$(CONFIG_SOC_RT3883)                        += soc_rt3883.o
 166 +ralink-eth-$(CONFIG_SOC_MT7620)                        += soc_mt7620.o
 167 +
 168 +obj-$(CONFIG_NET_RALINK)                       += ralink-eth.o
 169 --- /dev/null
 170 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
 171 @@ -0,0 +1,1463 @@
 172 +/*
 173 + *   This program is free software; you can redistribute it and/or modify
 174 + *   it under the terms of the GNU General Public License as published by
 175 + *   the Free Software Foundation; version 2 of the License
 176 + *
 177 + *   This program is distributed in the hope that it will be useful,
 178 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 179 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 180 + *   GNU General Public License for more details.
 181 + *
 182 + *   You should have received a copy of the GNU General Public License
 183 + *   along with this program; if not, write to the Free Software
 184 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 185 + *
 186 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
 187 + */
 188 +
 189 +#include <linux/module.h>
 190 +#include <linux/kernel.h>
 191 +#include <linux/types.h>
 192 +#include <linux/dma-mapping.h>
 193 +#include <linux/init.h>
 194 +#include <linux/skbuff.h>
 195 +#include <linux/etherdevice.h>
 196 +#include <linux/ethtool.h>
 197 +#include <linux/platform_device.h>
 198 +#include <linux/of_device.h>
 199 +#include <linux/clk.h>
 200 +#include <linux/of_net.h>
 201 +#include <linux/of_mdio.h>
 202 +
 203 +#include <asm/mach-ralink/ralink_regs.h>
 204 +
 205 +#include "ralink_soc_eth.h"
 206 +
 207 +#include <linux/ioport.h>
 208 +#include <linux/switch.h>
 209 +#include <linux/mii.h>
 210 +
 211 +#include <ralink_regs.h>
 212 +#include <asm/mach-ralink/rt305x.h>
 213 +#include <asm/mach-ralink/rt305x_esw_platform.h>
 214 +
 215 +/*
 216 + * HW limitations for this switch:
 217 + * - No large frame support (PKT_MAX_LEN at most 1536)
 218 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
 219 + *   though this might be possible using the undocumented PPE.
 220 + */
 221 +
 222 +#define RT305X_ESW_REG_ISR             0x00
 223 +#define RT305X_ESW_REG_IMR             0x04
 224 +#define RT305X_ESW_REG_FCT0            0x08
 225 +#define RT305X_ESW_REG_PFC1            0x14
 226 +#define RT305X_ESW_REG_ATS             0x24
 227 +#define RT305X_ESW_REG_ATS0            0x28
 228 +#define RT305X_ESW_REG_ATS1            0x2c
 229 +#define RT305X_ESW_REG_ATS2            0x30
 230 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 231 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 232 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 233 +#define RT305X_ESW_REG_POA             0x80
 234 +#define RT305X_ESW_REG_FPA             0x84
 235 +#define RT305X_ESW_REG_SOCPC           0x8c
 236 +#define RT305X_ESW_REG_POC0            0x90
 237 +#define RT305X_ESW_REG_POC1            0x94
 238 +#define RT305X_ESW_REG_POC2            0x98
 239 +#define RT305X_ESW_REG_SGC             0x9c
 240 +#define RT305X_ESW_REG_STRT            0xa0
 241 +#define RT305X_ESW_REG_PCR0            0xc0
 242 +#define RT305X_ESW_REG_PCR1            0xc4
 243 +#define RT305X_ESW_REG_FPA2            0xc8
 244 +#define RT305X_ESW_REG_FCT2            0xcc
 245 +#define RT305X_ESW_REG_SGC2            0xe4
 246 +#define RT305X_ESW_REG_P0LED           0xa4
 247 +#define RT305X_ESW_REG_P1LED           0xa8
 248 +#define RT305X_ESW_REG_P2LED           0xac
 249 +#define RT305X_ESW_REG_P3LED           0xb0
 250 +#define RT305X_ESW_REG_P4LED           0xb4
 251 +#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
 252 +#define RT305X_ESW_REG_P1PC            0xec
 253 +#define RT305X_ESW_REG_P2PC            0xf0
 254 +#define RT305X_ESW_REG_P3PC            0xf4
 255 +#define RT305X_ESW_REG_P4PC            0xf8
 256 +#define RT305X_ESW_REG_P5PC            0xfc
 257 +
 258 +#define RT305X_ESW_LED_LINK            0
 259 +#define RT305X_ESW_LED_100M            1
 260 +#define RT305X_ESW_LED_DUPLEX          2
 261 +#define RT305X_ESW_LED_ACTIVITY                3
 262 +#define RT305X_ESW_LED_COLLISION       4
 263 +#define RT305X_ESW_LED_LINKACT         5
 264 +#define RT305X_ESW_LED_DUPLCOLL                6
 265 +#define RT305X_ESW_LED_10MACT          7
 266 +#define RT305X_ESW_LED_100MACT         8
 267 +/* Additional led states not in datasheet: */
 268 +#define RT305X_ESW_LED_BLINK           10
 269 +#define RT305X_ESW_LED_ON              12
 270 +
 271 +#define RT305X_ESW_LINK_S              25
 272 +#define RT305X_ESW_DUPLEX_S            9
 273 +#define RT305X_ESW_SPD_S               0
 274 +
 275 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
 276 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
 277 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
 278 +
 279 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
 280 +
 281 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
 282 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 283 +
 284 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
 285 +#define RT305X_ESW_PVIDC_PVID_S                12
 286 +
 287 +#define RT305X_ESW_VLANI_VID_M         0xfff
 288 +#define RT305X_ESW_VLANI_VID_S         12
 289 +
 290 +#define RT305X_ESW_VMSC_MSC_M          0xff
 291 +#define RT305X_ESW_VMSC_MSC_S          8
 292 +
 293 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
 294 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
 295 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
 296 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
 297 +
 298 +#define RT305X_ESW_POC0_EN_BP_S                0
 299 +#define RT305X_ESW_POC0_EN_FC_S                8
 300 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
 301 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
 302 +#define RT305X_ESW_POC0_DIS_PORT_S     23
 303 +
 304 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
 305 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
 306 +#define RT305X_ESW_POC2_ENAGING_S      8
 307 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
 308 +
 309 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
 310 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
 311 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
 312 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
 313 +
 314 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
 315 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
 316 +#define RT305X_ESW_PFC1_EN_TOS_S       24
 317 +
 318 +#define RT305X_ESW_VLAN_NONE           0xfff
 319 +
 320 +#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
 321 +#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
 322 +
 323 +#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
 324 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
 325 +
 326 +#define RT305X_ESW_POA_LINK_MASK       0x1f
 327 +#define RT305X_ESW_POA_LINK_SHIFT      25
 328 +
 329 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
 330 +#define RT305X_ESW_PORT0               0
 331 +#define RT305X_ESW_PORT1               1
 332 +#define RT305X_ESW_PORT2               2
 333 +#define RT305X_ESW_PORT3               3
 334 +#define RT305X_ESW_PORT4               4
 335 +#define RT305X_ESW_PORT5               5
 336 +#define RT305X_ESW_PORT6               6
 337 +
 338 +#define RT305X_ESW_PORTS_NONE          0
 339 +
 340 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
 341 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
 342 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
 343 +
 344 +#define RT305X_ESW_PORTS_INTERNAL                                      \
 345 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 346 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 347 +                BIT(RT305X_ESW_PORT4))
 348 +
 349 +#define RT305X_ESW_PORTS_NOCPU                                         \
 350 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 351 +
 352 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
 353 +
 354 +#define RT305X_ESW_PORTS_ALL                                           \
 355 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 356 +
 357 +#define RT305X_ESW_NUM_VLANS           16
 358 +#define RT305X_ESW_NUM_VIDS            4096
 359 +#define RT305X_ESW_NUM_PORTS           7
 360 +#define RT305X_ESW_NUM_LANWAN          6
 361 +#define RT305X_ESW_NUM_LEDS            5
 362 +
 363 +#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
 364 +#define RT5350_EWS_REG_LED_POLARITY    0x168
 365 +#define RT5350_RESET_EPHY              BIT(24)
 366 +#define SYSC_REG_RESET_CTRL            0x34
 367 +
 368 +enum {
 369 +       /* Global attributes. */
 370 +       RT305X_ESW_ATTR_ENABLE_VLAN,
 371 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 372 +       RT305X_ESW_ATTR_BC_STATUS,
 373 +       RT305X_ESW_ATTR_LED_FREQ,
 374 +       /* Port attributes. */
 375 +       RT305X_ESW_ATTR_PORT_DISABLE,
 376 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
 377 +       RT305X_ESW_ATTR_PORT_UNTAG,
 378 +       RT305X_ESW_ATTR_PORT_LED,
 379 +       RT305X_ESW_ATTR_PORT_LAN,
 380 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
 381 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
 382 +       RT5350_ESW_ATTR_PORT_TR_BAD,
 383 +       RT5350_ESW_ATTR_PORT_TR_GOOD,
 384 +};
 385 +
 386 +struct esw_port {
 387 +       bool    disable;
 388 +       bool    doubletag;
 389 +       bool    untag;
 390 +       u8      led;
 391 +       u16     pvid;
 392 +};
 393 +
 394 +struct esw_vlan {
 395 +       u8      ports;
 396 +       u16     vid;
 397 +};
 398 +
 399 +struct rt305x_esw {
 400 +       struct device           *dev;
 401 +       void __iomem            *base;
 402 +       int                     irq;
 403 +       const struct rt305x_esw_platform_data *pdata;
 404 +       /* Protects against concurrent register rmw operations. */
 405 +       spinlock_t              reg_rw_lock;
 406 +
 407 +       unsigned char           port_map;
 408 +       unsigned int            reg_initval_fct2;
 409 +       unsigned int            reg_initval_fpa2;
 410 +       unsigned int            reg_led_polarity;
 411 +
 412 +
 413 +       struct switch_dev       swdev;
 414 +       bool                    global_vlan_enable;
 415 +       bool                    alt_vlan_disable;
 416 +       int                     bc_storm_protect;
 417 +       int                     led_frequency;
 418 +       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 419 +       struct esw_port ports[RT305X_ESW_NUM_PORTS];
 420 +
 421 +};
 422 +
 423 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
 424 +{
 425 +       __raw_writel(val, esw->base + reg);
 426 +}
 427 +
 428 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
 429 +{
 430 +       return __raw_readl(esw->base + reg);
 431 +}
 432 +
 433 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 434 +                  unsigned long val)
 435 +{
 436 +       unsigned long t;
 437 +
 438 +       t = __raw_readl(esw->base + reg) & ~mask;
 439 +       __raw_writel(t | val, esw->base + reg);
 440 +}
 441 +
 442 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 443 +              unsigned long val)
 444 +{
 445 +       unsigned long flags;
 446 +
 447 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
 448 +       esw_rmw_raw(esw, reg, mask, val);
 449 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 450 +}
 451 +
 452 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 453 +                u32 write_data)
 454 +{
 455 +       unsigned long t_start = jiffies;
 456 +       int ret = 0;
 457 +
 458 +       while (1) {
 459 +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
 460 +                     RT305X_ESW_PCR1_WT_DONE))
 461 +                       break;
 462 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 463 +                       ret = 1;
 464 +                       goto out;
 465 +               }
 466 +       }
 467 +
 468 +       write_data &= 0xffff;
 469 +       esw_w32(esw,
 470 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 471 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 472 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 473 +                     RT305X_ESW_REG_PCR0);
 474 +
 475 +       t_start = jiffies;
 476 +       while (1) {
 477 +               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
 478 +                   RT305X_ESW_PCR1_WT_DONE)
 479 +                       break;
 480 +
 481 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 482 +                       ret = 1;
 483 +                       break;
 484 +               }
 485 +       }
 486 +out:
 487 +       if (ret)
 488 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 489 +       return ret;
 490 +}
 491 +
 492 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 493 +{
 494 +       unsigned s;
 495 +       unsigned val;
 496 +
 497 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 498 +       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 499 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 500 +
 501 +       return val;
 502 +}
 503 +
 504 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 505 +{
 506 +       unsigned s;
 507 +
 508 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 509 +       esw_rmw(esw,
 510 +                      RT305X_ESW_REG_VLANI(vlan / 2),
 511 +                      RT305X_ESW_VLANI_VID_M << s,
 512 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
 513 +}
 514 +
 515 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 516 +{
 517 +       unsigned s, val;
 518 +
 519 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 520 +       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
 521 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 522 +}
 523 +
 524 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 525 +{
 526 +       unsigned s;
 527 +
 528 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 529 +       esw_rmw(esw,
 530 +                      RT305X_ESW_REG_PVIDC(port / 2),
 531 +                      RT305X_ESW_PVIDC_PVID_M << s,
 532 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 533 +}
 534 +
 535 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 536 +{
 537 +       unsigned s, val;
 538 +
 539 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 540 +       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 541 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 542 +
 543 +       return val;
 544 +}
 545 +
 546 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 547 +{
 548 +       unsigned s;
 549 +
 550 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 551 +       esw_rmw(esw,
 552 +                      RT305X_ESW_REG_VMSC(vlan / 4),
 553 +                      RT305X_ESW_VMSC_MSC_M << s,
 554 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
 555 +}
 556 +
 557 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
 558 +{
 559 +       unsigned reg;
 560 +       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
 561 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
 562 +              RT305X_ESW_POC0_DIS_PORT_M;
 563 +}
 564 +
 565 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
 566 +{
 567 +       unsigned old_mask;
 568 +       unsigned enable_mask;
 569 +       unsigned changed;
 570 +       int i;
 571 +
 572 +       old_mask = esw_get_port_disable(esw);
 573 +       changed = old_mask ^ disable_mask;
 574 +       enable_mask = old_mask & disable_mask;
 575 +
 576 +       /* enable before writing to MII */
 577 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 578 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 579 +                       RT305X_ESW_POC0_DIS_PORT_S),
 580 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 581 +
 582 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
 583 +               if (!(changed & (1 << i)))
 584 +                       continue;
 585 +               if (disable_mask & (1 << i)) {
 586 +                       /* disable */
 587 +                       rt305x_mii_write(esw, i, MII_BMCR,
 588 +                                        BMCR_PDOWN);
 589 +               } else {
 590 +                       /* enable */
 591 +                       rt305x_mii_write(esw, i, MII_BMCR,
 592 +                                        BMCR_FULLDPLX |
 593 +                                        BMCR_ANENABLE |
 594 +                                        BMCR_ANRESTART |
 595 +                                        BMCR_SPEED100);
 596 +               }
 597 +       }
 598 +
 599 +       /* disable after writing to MII */
 600 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 601 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 602 +                       RT305X_ESW_POC0_DIS_PORT_S),
 603 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 604 +}
 605 +
 606 +static void esw_set_gsc(struct rt305x_esw *esw)
 607 +{
 608 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 609 +               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
 610 +               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
 611 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 612 +               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
 613 +               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
 614 +}
 615 +
 616 +static int esw_apply_config(struct switch_dev *dev);
 617 +
 618 +static void esw_hw_init(struct rt305x_esw *esw)
 619 +{
 620 +       int i;
 621 +       u8 port_disable = 0;
 622 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 623 +
 624 +       /* vodoo from original driver */
 625 +       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 626 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 627 +       /* Port priority 1 for all ports, vlan enabled. */
 628 +       esw_w32(esw, 0x00005555 |
 629 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 630 +                     RT305X_ESW_REG_PFC1);
 631 +
 632 +       /* Enable Back Pressure, and Flow Control */
 633 +       esw_w32(esw,
 634 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 635 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 636 +                     RT305X_ESW_REG_POC0);
 637 +
 638 +       /* Enable Aging, and VLAN TAG removal */
 639 +       esw_w32(esw,
 640 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 641 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 642 +                     RT305X_ESW_REG_POC2);
 643 +
 644 +       if (esw->reg_initval_fct2)
 645 +               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 646 +       else
 647 +               esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 648 +
 649 +       /*
 650 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
 651 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
 652 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
 653 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 654 +        * ports.
 655 +        */
 656 +       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 657 +
 658 +       /* Setup SoC Port control register */
 659 +       esw_w32(esw,
 660 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
 661 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 662 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 663 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 664 +                     RT305X_ESW_REG_SOCPC);
 665 +
 666 +       if (esw->reg_initval_fpa2)
 667 +               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 668 +       else
 669 +               esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 670 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
 671 +
 672 +       /* Force Link/Activity on ports */
 673 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 674 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 675 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 676 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 677 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 678 +
 679 +       /* Copy disabled port configuration from bootloader setup */
 680 +       port_disable = esw_get_port_disable(esw);
 681 +       for (i = 0; i < 6; i++)
 682 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 683 +
 684 +       if (soc_is_rt3352()) {
 685 +               /* reset EPHY */
 686 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 687 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 688 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 689 +
 690 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 691 +               for (i = 0; i < 5; i++) {
 692 +                       if (esw->ports[i].disable) {
 693 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 694 +                       } else {
 695 +                               rt305x_mii_write(esw, i, MII_BMCR,
 696 +                                        BMCR_FULLDPLX |
 697 +                                        BMCR_ANENABLE |
 698 +                                        BMCR_SPEED100);
 699 +                       }
 700 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 701 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 702 +                       /* TX100/TX10 AD/DA current bias */
 703 +                       rt305x_mii_write(esw, i, 29, 0x7016);
 704 +                       /* TX100 slew rate control */
 705 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 706 +               }
 707 +
 708 +               /* select global register */
 709 +               rt305x_mii_write(esw, 0, 31, 0x0);
 710 +               /* enlarge agcsel threshold 3 and threshold 2 */
 711 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 712 +               /* enlarge agcsel threshold 5 and threshold 4 */
 713 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 714 +               /* enlarge agcsel threshold  */
 715 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 716 +               rt305x_mii_write(esw, 0,12, 0x7eaa);
 717 +               /* longer TP_IDL tail length */
 718 +               rt305x_mii_write(esw, 0, 14, 0x65);
 719 +               /* increased squelch pulse count threshold. */
 720 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 721 +               /* set TX10 signal amplitude threshold to minimum */
 722 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 723 +               /* set squelch amplitude to higher threshold */
 724 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 725 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 726 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 727 +               /* set PLL/Receive bias current are calibrated */
 728 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 729 +               /* change PLL/Receive bias current to internal(RT3350) */
 730 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 731 +               /* change PLL bias current to internal(RT3052_MP3) */
 732 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 733 +               /* select local register */
 734 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 735 +       } else if (soc_is_rt5350()) {
 736 +               /* reset EPHY */
 737 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 738 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 739 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 740 +
 741 +               /* set the led polarity */
 742 +               esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
 743 +
 744 +               /* local registers */
 745 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 746 +               for (i = 0; i < 5; i++) {
 747 +                       if (esw->ports[i].disable) {
 748 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 749 +                       } else {
 750 +                               rt305x_mii_write(esw, i, MII_BMCR,
 751 +                                        BMCR_FULLDPLX |
 752 +                                        BMCR_ANENABLE |
 753 +                                        BMCR_SPEED100);
 754 +                       }
 755 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 756 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 757 +                       /* TX100/TX10 AD/DA current bias */
 758 +                       rt305x_mii_write(esw, i, 29, 0x7015);
 759 +                       /* TX100 slew rate control */
 760 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 761 +               }
 762 +
 763 +               /* global registers */
 764 +               rt305x_mii_write(esw, 0, 31, 0x0);
 765 +               /* enlarge agcsel threshold 3 and threshold 2 */
 766 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 767 +               /* enlarge agcsel threshold 5 and threshold 4 */
 768 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 769 +               /* enlarge agcsel threshold 6 */
 770 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 771 +               rt305x_mii_write(esw, 0, 12, 0x7eaa);
 772 +               /* longer TP_IDL tail length */
 773 +               rt305x_mii_write(esw, 0, 14, 0x65);
 774 +               /* increased squelch pulse count threshold. */
 775 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 776 +               /* set TX10 signal amplitude threshold to minimum */
 777 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 778 +               /* set squelch amplitude to higher threshold */
 779 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 780 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 781 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 782 +               /* set PLL/Receive bias current are calibrated */
 783 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 784 +               /* change PLL/Receive bias current to internal(RT3350) */
 785 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 786 +               /* change PLL bias current to internal(RT3052_MP3) */
 787 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 788 +               /* select local register */
 789 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 790 +       } else {
 791 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 792 +               for (i = 0; i < 5; i++) {
 793 +                       if (esw->ports[i].disable) {
 794 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 795 +                       } else {
 796 +                               rt305x_mii_write(esw, i, MII_BMCR,
 797 +                                        BMCR_FULLDPLX |
 798 +                                        BMCR_ANENABLE |
 799 +                                        BMCR_SPEED100);
 800 +                       }
 801 +                       /* TX10 waveform coefficient */
 802 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 803 +                       /* TX100/TX10 AD/DA current bias */
 804 +                       rt305x_mii_write(esw, i, 29, 0x7058);
 805 +                       /* TX100 slew rate control */
 806 +                       rt305x_mii_write(esw, i, 30, 0x0018);
 807 +               }
 808 +
 809 +               /* PHY IOT */
 810 +               /* select global register */
 811 +               rt305x_mii_write(esw, 0, 31, 0x0);
 812 +               /* tune TP_IDL tail and head waveform */
 813 +               rt305x_mii_write(esw, 0, 22, 0x052f);
 814 +               /* set TX10 signal amplitude threshold to minimum */
 815 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 816 +               /* set squelch amplitude to higher threshold */
 817 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 818 +               /* longer TP_IDL tail length */
 819 +               rt305x_mii_write(esw, 0, 14, 0x65);
 820 +               /* select local register */
 821 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 822 +       }
 823 +
 824 +       if (esw->port_map)
 825 +               port_map = esw->port_map;
 826 +       else
 827 +               port_map = RT305X_ESW_PMAP_LLLLLL;
 828 +
 829 +       /*
 830 +        * Unused HW feature, but still nice to be consistent here...
 831 +        * This is also exported to userspace ('lan' attribute) so it's
 832 +        * conveniently usable to decide which ports go into the wan vlan by
 833 +        * default.
 834 +        */
 835 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 836 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 837 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 838 +
 839 +       /* make the switch leds blink */
 840 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
 841 +               esw->ports[i].led = 0x05;
 842 +
 843 +       /* Apply the empty config. */
 844 +       esw_apply_config(&esw->swdev);
 845 +
 846 +       /* Only unmask the port change interrupt */
 847 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
 848 +}
 849 +
 850 +static irqreturn_t esw_interrupt(int irq, void *_esw)
 851 +{
 852 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
 853 +       u32 status;
 854 +
 855 +       status = esw_r32(esw, RT305X_ESW_REG_ISR);
 856 +       if (status & RT305X_ESW_PORT_ST_CHG) {
 857 +               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
 858 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
 859 +               link &= RT305X_ESW_POA_LINK_MASK;
 860 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
 861 +       }
 862 +       esw_w32(esw, status, RT305X_ESW_REG_ISR);
 863 +
 864 +       return IRQ_HANDLED;
 865 +}
 866 +
 867 +static int esw_apply_config(struct switch_dev *dev)
 868 +{
 869 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 870 +       int i;
 871 +       u8 disable = 0;
 872 +       u8 doubletag = 0;
 873 +       u8 en_vlan = 0;
 874 +       u8 untag = 0;
 875 +
 876 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 877 +               u32 vid, vmsc;
 878 +               if (esw->global_vlan_enable) {
 879 +                       vid = esw->vlans[i].vid;
 880 +                       vmsc = esw->vlans[i].ports;
 881 +               } else {
 882 +                       vid = RT305X_ESW_VLAN_NONE;
 883 +                       vmsc = RT305X_ESW_PORTS_NONE;
 884 +               }
 885 +               esw_set_vlan_id(esw, i, vid);
 886 +               esw_set_vmsc(esw, i, vmsc);
 887 +       }
 888 +
 889 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 890 +               u32 pvid;
 891 +               disable |= esw->ports[i].disable << i;
 892 +               if (esw->global_vlan_enable) {
 893 +                       doubletag |= esw->ports[i].doubletag << i;
 894 +                       en_vlan   |= 1                       << i;
 895 +                       untag     |= esw->ports[i].untag     << i;
 896 +                       pvid       = esw->ports[i].pvid;
 897 +               } else {
 898 +                       int x = esw->alt_vlan_disable ? 0 : 1;
 899 +                       doubletag |= x << i;
 900 +                       en_vlan   |= x << i;
 901 +                       untag     |= x << i;
 902 +                       pvid       = 0;
 903 +               }
 904 +               esw_set_pvid(esw, i, pvid);
 905 +               if (i < RT305X_ESW_NUM_LEDS)
 906 +                       esw_w32(esw, esw->ports[i].led,
 907 +                                     RT305X_ESW_REG_P0LED + 4*i);
 908 +       }
 909 +
 910 +       esw_set_gsc(esw);
 911 +       esw_set_port_disable(esw, disable);
 912 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 913 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 914 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
 915 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 916 +       esw_rmw(esw, RT305X_ESW_REG_PFC1,
 917 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 918 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 919 +       esw_rmw(esw, RT305X_ESW_REG_POC2,
 920 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 921 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
 922 +
 923 +       if (!esw->global_vlan_enable) {
 924 +               /*
 925 +                * Still need to put all ports into vlan 0 or they'll be
 926 +                * isolated.
 927 +                * NOTE: vlan 0 is special, no vlan tag is prepended
 928 +                */
 929 +               esw_set_vlan_id(esw, 0, 0);
 930 +               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 931 +       }
 932 +
 933 +       return 0;
 934 +}
 935 +
 936 +static int esw_reset_switch(struct switch_dev *dev)
 937 +{
 938 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 939 +
 940 +       esw->global_vlan_enable = 0;
 941 +       memset(esw->ports, 0, sizeof(esw->ports));
 942 +       memset(esw->vlans, 0, sizeof(esw->vlans));
 943 +       esw_hw_init(esw);
 944 +
 945 +       return 0;
 946 +}
 947 +
 948 +static int esw_get_vlan_enable(struct switch_dev *dev,
 949 +                          const struct switch_attr *attr,
 950 +                          struct switch_val *val)
 951 +{
 952 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 953 +
 954 +       val->value.i = esw->global_vlan_enable;
 955 +
 956 +       return 0;
 957 +}
 958 +
 959 +static int esw_set_vlan_enable(struct switch_dev *dev,
 960 +                          const struct switch_attr *attr,
 961 +                          struct switch_val *val)
 962 +{
 963 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 964 +
 965 +       esw->global_vlan_enable = val->value.i != 0;
 966 +
 967 +       return 0;
 968 +}
 969 +
 970 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
 971 +                               const struct switch_attr *attr,
 972 +                               struct switch_val *val)
 973 +{
 974 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 975 +
 976 +       val->value.i = esw->alt_vlan_disable;
 977 +
 978 +       return 0;
 979 +}
 980 +
 981 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
 982 +                               const struct switch_attr *attr,
 983 +                               struct switch_val *val)
 984 +{
 985 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 986 +
 987 +       esw->alt_vlan_disable = val->value.i != 0;
 988 +
 989 +       return 0;
 990 +}
 991 +
 992 +static int
 993 +rt305x_esw_set_bc_status(struct switch_dev *dev,
 994 +                       const struct switch_attr *attr,
 995 +                       struct switch_val *val)
 996 +{
 997 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 998 +
 999 +       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1000 +
1001 +       return 0;
1002 +}
1003 +
1004 +static int
1005 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1006 +                       const struct switch_attr *attr,
1007 +                       struct switch_val *val)
1008 +{
1009 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1010 +
1011 +       val->value.i = esw->bc_storm_protect;
1012 +
1013 +       return 0;
1014 +}
1015 +
1016 +static int
1017 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1018 +                       const struct switch_attr *attr,
1019 +                       struct switch_val *val)
1020 +{
1021 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1022 +
1023 +       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1024 +
1025 +       return 0;
1026 +}
1027 +
1028 +static int
1029 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1030 +                       const struct switch_attr *attr,
1031 +                       struct switch_val *val)
1032 +{
1033 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1034 +
1035 +       val->value.i = esw->led_frequency;
1036 +
1037 +       return 0;
1038 +}
1039 +
1040 +static int esw_get_port_link(struct switch_dev *dev,
1041 +                        int port,
1042 +                        struct switch_port_link *link)
1043 +{
1044 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1045 +       u32 speed, poa;
1046 +
1047 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1048 +               return -EINVAL;
1049 +
1050 +       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1051 +
1052 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1053 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1054 +       if (port < RT305X_ESW_NUM_LEDS) {
1055 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
1056 +       } else {
1057 +               if (port == RT305X_ESW_NUM_PORTS - 1)
1058 +                       poa >>= 1;
1059 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
1060 +       }
1061 +       switch (speed) {
1062 +       case 0:
1063 +               link->speed = SWITCH_PORT_SPEED_10;
1064 +               break;
1065 +       case 1:
1066 +               link->speed = SWITCH_PORT_SPEED_100;
1067 +               break;
1068 +       case 2:
1069 +       case 3: /* forced gige speed can be 2 or 3 */
1070 +               link->speed = SWITCH_PORT_SPEED_1000;
1071 +               break;
1072 +       default:
1073 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1074 +               break;
1075 +       }
1076 +
1077 +       return 0;
1078 +}
1079 +
1080 +static int esw_get_port_bool(struct switch_dev *dev,
1081 +                        const struct switch_attr *attr,
1082 +                        struct switch_val *val)
1083 +{
1084 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1085 +       int idx = val->port_vlan;
1086 +       u32 x, reg, shift;
1087 +
1088 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1089 +               return -EINVAL;
1090 +
1091 +       switch (attr->id) {
1092 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1093 +               reg = RT305X_ESW_REG_POC0;
1094 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
1095 +               break;
1096 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1097 +               reg = RT305X_ESW_REG_SGC2;
1098 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1099 +               break;
1100 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1101 +               reg = RT305X_ESW_REG_POC2;
1102 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
1103 +               break;
1104 +       case RT305X_ESW_ATTR_PORT_LAN:
1105 +               reg = RT305X_ESW_REG_SGC2;
1106 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1107 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1108 +                       return -EINVAL;
1109 +               break;
1110 +       default:
1111 +               return -EINVAL;
1112 +       }
1113 +
1114 +       x = esw_r32(esw, reg);
1115 +       val->value.i = (x >> (idx + shift)) & 1;
1116 +
1117 +       return 0;
1118 +}
1119 +
1120 +static int esw_set_port_bool(struct switch_dev *dev,
1121 +                        const struct switch_attr *attr,
1122 +                        struct switch_val *val)
1123 +{
1124 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1125 +       int idx = val->port_vlan;
1126 +
1127 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1128 +           val->value.i < 0 || val->value.i > 1)
1129 +               return -EINVAL;
1130 +
1131 +       switch (attr->id) {
1132 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1133 +               esw->ports[idx].disable = val->value.i;
1134 +               break;
1135 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1136 +               esw->ports[idx].doubletag = val->value.i;
1137 +               break;
1138 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1139 +               esw->ports[idx].untag = val->value.i;
1140 +               break;
1141 +       default:
1142 +               return -EINVAL;
1143 +       }
1144 +
1145 +       return 0;
1146 +}
1147 +
1148 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1149 +                                const struct switch_attr *attr,
1150 +                                struct switch_val *val)
1151 +{
1152 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1153 +       int idx = val->port_vlan;
1154 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1155 +       u32 reg;
1156 +
1157 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1158 +               return -EINVAL;
1159 +       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1160 +       val->value.i = (reg >> shift) & 0xffff;
1161 +
1162 +       return 0;
1163 +}
1164 +
1165 +static int
1166 +esw_get_port_tr_badgood(struct switch_dev *dev,
1167 +                                const struct switch_attr *attr,
1168 +                                struct switch_val *val)
1169 +{
1170 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1171 +
1172 +       int idx = val->port_vlan;
1173 +       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1174 +       u32 reg;
1175 +
1176 +       if (!soc_is_rt5350())
1177 +               return -EINVAL;
1178 +
1179 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1180 +               return -EINVAL;
1181 +
1182 +       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1183 +       val->value.i = (reg >> shift) & 0xffff;
1184 +
1185 +       return 0;
1186 +}
1187 +
1188 +static int esw_get_port_led(struct switch_dev *dev,
1189 +                       const struct switch_attr *attr,
1190 +                       struct switch_val *val)
1191 +{
1192 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1193 +       int idx = val->port_vlan;
1194 +
1195 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1196 +           idx >= RT305X_ESW_NUM_LEDS)
1197 +               return -EINVAL;
1198 +
1199 +       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1200 +
1201 +       return 0;
1202 +}
1203 +
1204 +static int esw_set_port_led(struct switch_dev *dev,
1205 +                       const struct switch_attr *attr,
1206 +                       struct switch_val *val)
1207 +{
1208 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1209 +       int idx = val->port_vlan;
1210 +
1211 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1212 +               return -EINVAL;
1213 +
1214 +       esw->ports[idx].led = val->value.i;
1215 +
1216 +       return 0;
1217 +}
1218 +
1219 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1220 +{
1221 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1222 +
1223 +       if (port >= RT305X_ESW_NUM_PORTS)
1224 +               return -EINVAL;
1225 +
1226 +       *val = esw_get_pvid(esw, port);
1227 +
1228 +       return 0;
1229 +}
1230 +
1231 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1232 +{
1233 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1234 +
1235 +       if (port >= RT305X_ESW_NUM_PORTS)
1236 +               return -EINVAL;
1237 +
1238 +       esw->ports[port].pvid = val;
1239 +
1240 +       return 0;
1241 +}
1242 +
1243 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1244 +{
1245 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1246 +       u32 vmsc, poc2;
1247 +       int vlan_idx = -1;
1248 +       int i;
1249 +
1250 +       val->len = 0;
1251 +
1252 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1253 +               return -EINVAL;
1254 +
1255 +       /* valid vlan? */
1256 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1257 +               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1258 +                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1259 +                       vlan_idx = i;
1260 +                       break;
1261 +               }
1262 +       }
1263 +
1264 +       if (vlan_idx == -1)
1265 +               return -EINVAL;
1266 +
1267 +       vmsc = esw_get_vmsc(esw, vlan_idx);
1268 +       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1269 +
1270 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1271 +               struct switch_port *p;
1272 +               int port_mask = 1 << i;
1273 +
1274 +               if (!(vmsc & port_mask))
1275 +                       continue;
1276 +
1277 +               p = &val->value.ports[val->len++];
1278 +               p->id = i;
1279 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1280 +                       p->flags = 0;
1281 +               else
1282 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1283 +       }
1284 +
1285 +       return 0;
1286 +}
1287 +
1288 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1289 +{
1290 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1291 +       int ports;
1292 +       int vlan_idx = -1;
1293 +       int i;
1294 +
1295 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1296 +           val->len > RT305X_ESW_NUM_PORTS)
1297 +               return -EINVAL;
1298 +
1299 +       /* one of the already defined vlans? */
1300 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1301 +               if (esw->vlans[i].vid == val->port_vlan &&
1302 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1303 +                       vlan_idx = i;
1304 +                       break;
1305 +               }
1306 +       }
1307 +
1308 +       /* select a free slot */
1309 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1310 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1311 +                       vlan_idx = i;
1312 +       }
1313 +
1314 +       /* bail if all slots are in use */
1315 +       if (vlan_idx == -1)
1316 +               return -EINVAL;
1317 +
1318 +       ports = RT305X_ESW_PORTS_NONE;
1319 +       for (i = 0; i < val->len; i++) {
1320 +               struct switch_port *p = &val->value.ports[i];
1321 +               int port_mask = 1 << p->id;
1322 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1323 +
1324 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1325 +                       return -EINVAL;
1326 +
1327 +               ports |= port_mask;
1328 +               esw->ports[p->id].untag = untagged;
1329 +       }
1330 +       esw->vlans[vlan_idx].ports = ports;
1331 +       if (ports == RT305X_ESW_PORTS_NONE)
1332 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1333 +       else
1334 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1335 +
1336 +       return 0;
1337 +}
1338 +
1339 +static const struct switch_attr esw_global[] = {
1340 +       {
1341 +               .type = SWITCH_TYPE_INT,
1342 +               .name = "enable_vlan",
1343 +               .description = "VLAN mode (1:enabled)",
1344 +               .max = 1,
1345 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1346 +               .get = esw_get_vlan_enable,
1347 +               .set = esw_set_vlan_enable,
1348 +       },
1349 +       {
1350 +               .type = SWITCH_TYPE_INT,
1351 +               .name = "alternate_vlan_disable",
1352 +               .description = "Use en_vlan instead of doubletag to disable"
1353 +                               " VLAN mode",
1354 +               .max = 1,
1355 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1356 +               .get = esw_get_alt_vlan_disable,
1357 +               .set = esw_set_alt_vlan_disable,
1358 +       },
1359 +       {
1360 +               .type = SWITCH_TYPE_INT,
1361 +               .name = "bc_storm_protect",
1362 +               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1363 +               .max = 3,
1364 +               .id = RT305X_ESW_ATTR_BC_STATUS,
1365 +               .get = rt305x_esw_get_bc_status,
1366 +               .set = rt305x_esw_set_bc_status,
1367 +       },
1368 +       {
1369 +               .type = SWITCH_TYPE_INT,
1370 +               .name = "led_frequency",
1371 +               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1372 +               .max = 3,
1373 +               .id = RT305X_ESW_ATTR_LED_FREQ,
1374 +               .get = rt305x_esw_get_led_freq,
1375 +               .set = rt305x_esw_set_led_freq,
1376 +       }
1377 +};
1378 +
1379 +static const struct switch_attr esw_port[] = {
1380 +       {
1381 +               .type = SWITCH_TYPE_INT,
1382 +               .name = "disable",
1383 +               .description = "Port state (1:disabled)",
1384 +               .max = 1,
1385 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1386 +               .get = esw_get_port_bool,
1387 +               .set = esw_set_port_bool,
1388 +       },
1389 +       {
1390 +               .type = SWITCH_TYPE_INT,
1391 +               .name = "doubletag",
1392 +               .description = "Double tagging for incoming vlan packets "
1393 +                               "(1:enabled)",
1394 +               .max = 1,
1395 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1396 +               .get = esw_get_port_bool,
1397 +               .set = esw_set_port_bool,
1398 +       },
1399 +       {
1400 +               .type = SWITCH_TYPE_INT,
1401 +               .name = "untag",
1402 +               .description = "Untag (1:strip outgoing vlan tag)",
1403 +               .max = 1,
1404 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1405 +               .get = esw_get_port_bool,
1406 +               .set = esw_set_port_bool,
1407 +       },
1408 +       {
1409 +               .type = SWITCH_TYPE_INT,
1410 +               .name = "led",
1411 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1412 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1413 +                               " 8:100mact, 10:blink, 11:off, 12:on)",
1414 +               .max = 15,
1415 +               .id = RT305X_ESW_ATTR_PORT_LED,
1416 +               .get = esw_get_port_led,
1417 +               .set = esw_set_port_led,
1418 +       },
1419 +       {
1420 +               .type = SWITCH_TYPE_INT,
1421 +               .name = "lan",
1422 +               .description = "HW port group (0:wan, 1:lan)",
1423 +               .max = 1,
1424 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1425 +               .get = esw_get_port_bool,
1426 +       },
1427 +       {
1428 +               .type = SWITCH_TYPE_INT,
1429 +               .name = "recv_bad",
1430 +               .description = "Receive bad packet counter",
1431 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1432 +               .get = esw_get_port_recv_badgood,
1433 +       },
1434 +       {
1435 +               .type = SWITCH_TYPE_INT,
1436 +               .name = "recv_good",
1437 +               .description = "Receive good packet counter",
1438 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1439 +               .get = esw_get_port_recv_badgood,
1440 +       },
1441 +       {
1442 +               .type = SWITCH_TYPE_INT,
1443 +               .name = "tr_bad",
1444 +
1445 +               .description = "Transmit bad packet counter. rt5350 only",
1446 +               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1447 +               .get = esw_get_port_tr_badgood,
1448 +       },
1449 +       {
1450 +               .type = SWITCH_TYPE_INT,
1451 +               .name = "tr_good",
1452 +
1453 +               .description = "Transmit good packet counter. rt5350 only",
1454 +               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1455 +               .get = esw_get_port_tr_badgood,
1456 +       },
1457 +};
1458 +
1459 +static const struct switch_attr esw_vlan[] = {
1460 +};
1461 +
1462 +static const struct switch_dev_ops esw_ops = {
1463 +       .attr_global = {
1464 +               .attr = esw_global,
1465 +               .n_attr = ARRAY_SIZE(esw_global),
1466 +       },
1467 +       .attr_port = {
1468 +               .attr = esw_port,
1469 +               .n_attr = ARRAY_SIZE(esw_port),
1470 +       },
1471 +       .attr_vlan = {
1472 +               .attr = esw_vlan,
1473 +               .n_attr = ARRAY_SIZE(esw_vlan),
1474 +       },
1475 +       .get_vlan_ports = esw_get_vlan_ports,
1476 +       .set_vlan_ports = esw_set_vlan_ports,
1477 +       .get_port_pvid = esw_get_port_pvid,
1478 +       .set_port_pvid = esw_set_port_pvid,
1479 +       .get_port_link = esw_get_port_link,
1480 +       .apply_config = esw_apply_config,
1481 +       .reset_switch = esw_reset_switch,
1482 +};
1483 +
1484 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1485 +       /* All ports are LAN ports. */
1486 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1487 +       .reg_initval_fct2       = 0x00d6500c,
1488 +       /*
1489 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1490 +        * turbo mii off, rgmi 3.3v off
1491 +        * port5: disabled
1492 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1493 +        */
1494 +       .reg_initval_fpa2       = 0x3f502b28,
1495 +};
1496 +
1497 +static const struct of_device_id ralink_esw_match[] = {
1498 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1499 +       {},
1500 +};
1501 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1502 +
1503 +static int esw_probe(struct platform_device *pdev)
1504 +{
1505 +       struct device_node *np = pdev->dev.of_node;
1506 +       const struct rt305x_esw_platform_data *pdata;
1507 +       const __be32 *port_map, *reg_init;
1508 +       struct rt305x_esw *esw;
1509 +       struct switch_dev *swdev;
1510 +       struct resource *res, *irq;
1511 +       int err;
1512 +
1513 +       pdata = pdev->dev.platform_data;
1514 +       if (!pdata) {
1515 +               const struct of_device_id *match;
1516 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1517 +               if (match)
1518 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1519 +       }
1520 +       if (!pdata)
1521 +               return -EINVAL;
1522 +
1523 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1524 +       if (!res) {
1525 +               dev_err(&pdev->dev, "no memory resource found\n");
1526 +               return -ENOMEM;
1527 +       }
1528 +
1529 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1530 +       if (!irq) {
1531 +               dev_err(&pdev->dev, "no irq resource found\n");
1532 +               return -ENOMEM;
1533 +       }
1534 +
1535 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1536 +       if (!esw) {
1537 +               dev_err(&pdev->dev, "no memory for private data\n");
1538 +               return -ENOMEM;
1539 +       }
1540 +
1541 +       esw->dev = &pdev->dev;
1542 +       esw->irq = irq->start;
1543 +       esw->base = ioremap(res->start, resource_size(res));
1544 +       if (!esw->base) {
1545 +               dev_err(&pdev->dev, "ioremap failed\n");
1546 +               err = -ENOMEM;
1547 +               goto free_esw;
1548 +       }
1549 +
1550 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1551 +        if (port_map)
1552 +               esw->port_map = be32_to_cpu(*port_map);
1553 +
1554 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1555 +        if (reg_init)
1556 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1557 +
1558 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1559 +        if (reg_init)
1560 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1561 +
1562 +       reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1563 +        if (reg_init)
1564 +               esw->reg_led_polarity = be32_to_cpu(*reg_init);
1565 +
1566 +       swdev = &esw->swdev;
1567 +       swdev->of_node = pdev->dev.of_node;
1568 +       swdev->name = "rt305x-esw";
1569 +       swdev->alias = "rt305x";
1570 +       swdev->cpu_port = RT305X_ESW_PORT6;
1571 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1572 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1573 +       swdev->ops = &esw_ops;
1574 +
1575 +       err = register_switch(swdev, NULL);
1576 +       if (err < 0) {
1577 +               dev_err(&pdev->dev, "register_switch failed\n");
1578 +               goto unmap_base;
1579 +       }
1580 +
1581 +       platform_set_drvdata(pdev, esw);
1582 +
1583 +       esw->pdata = pdata;
1584 +       spin_lock_init(&esw->reg_rw_lock);
1585 +
1586 +       esw_hw_init(esw);
1587 +
1588 +       esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1589 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1590 +       request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1591 +
1592 +       return 0;
1593 +
1594 +unmap_base:
1595 +       iounmap(esw->base);
1596 +free_esw:
1597 +       kfree(esw);
1598 +       return err;
1599 +}
1600 +
1601 +static int esw_remove(struct platform_device *pdev)
1602 +{
1603 +       struct rt305x_esw *esw;
1604 +
1605 +       esw = platform_get_drvdata(pdev);
1606 +       if (esw) {
1607 +               unregister_switch(&esw->swdev);
1608 +               platform_set_drvdata(pdev, NULL);
1609 +               iounmap(esw->base);
1610 +               kfree(esw);
1611 +       }
1612 +
1613 +       return 0;
1614 +}
1615 +
1616 +static struct platform_driver esw_driver = {
1617 +       .probe = esw_probe,
1618 +       .remove = esw_remove,
1619 +       .driver = {
1620 +               .name = "rt305x-esw",
1621 +               .owner = THIS_MODULE,
1622 +               .of_match_table = ralink_esw_match,
1623 +       },
1624 +};
1625 +
1626 +int __init rtesw_init(void)
1627 +{
1628 +       return platform_driver_register(&esw_driver);
1629 +}
1630 +
1631 +void rtesw_exit(void)
1632 +{
1633 +       platform_driver_unregister(&esw_driver);
1634 +}
1635 --- /dev/null
1636 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1637 @@ -0,0 +1,32 @@
1638 +/*
1639 + *   This program is free software; you can redistribute it and/or modify
1640 + *   it under the terms of the GNU General Public License as published by
1641 + *   the Free Software Foundation; version 2 of the License
1642 + *
1643 + *   This program is distributed in the hope that it will be useful,
1644 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1645 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1646 + *   GNU General Public License for more details.
1647 + *
1648 + *   You should have received a copy of the GNU General Public License
1649 + *   along with this program; if not, write to the Free Software
1650 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1651 + *
1652 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1653 + */
1654 +
1655 +#ifndef _RALINK_ESW_RT3052_H__
1656 +#define _RALINK_ESW_RT3052_H__
1657 +
1658 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1659 +
1660 +int __init rtesw_init(void);
1661 +void rtesw_exit(void);
1662 +
1663 +#else
1664 +
1665 +static inline int __init rtesw_init(void) { return 0; }
1666 +static inline void rtesw_exit(void) { }
1667 +
1668 +#endif
1669 +#endif
1670 --- /dev/null
1671 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1672 @@ -0,0 +1,566 @@
1673 +/*
1674 + *   This program is free software; you can redistribute it and/or modify
1675 + *   it under the terms of the GNU General Public License as published by
1676 + *   the Free Software Foundation; version 2 of the License
1677 + *
1678 + *   This program is distributed in the hope that it will be useful,
1679 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1680 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1681 + *   GNU General Public License for more details.
1682 + *
1683 + *   You should have received a copy of the GNU General Public License
1684 + *   along with this program; if not, write to the Free Software
1685 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1686 + *
1687 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1688 + */
1689 +
1690 +#include <linux/module.h>
1691 +#include <linux/kernel.h>
1692 +#include <linux/types.h>
1693 +#include <linux/dma-mapping.h>
1694 +#include <linux/init.h>
1695 +#include <linux/skbuff.h>
1696 +#include <linux/etherdevice.h>
1697 +#include <linux/ethtool.h>
1698 +#include <linux/platform_device.h>
1699 +#include <linux/of_device.h>
1700 +#include <linux/clk.h>
1701 +#include <linux/of_net.h>
1702 +#include <linux/of_mdio.h>
1703 +#include <linux/of_irq.h>
1704 +#include <linux/of_address.h>
1705 +#include <linux/switch.h>
1706 +
1707 +#include <asm/mach-ralink/ralink_regs.h>
1708 +
1709 +#include "ralink_soc_eth.h"
1710 +
1711 +#include <linux/ioport.h>
1712 +#include <linux/switch.h>
1713 +#include <linux/mii.h>
1714 +
1715 +#include <ralink_regs.h>
1716 +#include <asm/mach-ralink/mt7620.h>
1717 +
1718 +#include "ralink_soc_eth.h"
1719 +#include "gsw_mt7620a.h"
1720 +#include "mt7530.h"
1721 +#include "mdio.h"
1722 +
1723 +#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
1724 +
1725 +#define MT7620A_GSW_REG_PIAC   0x7004
1726 +
1727 +#define GSW_NUM_VLANS          16
1728 +#define GSW_NUM_VIDS           4096
1729 +#define GSW_NUM_PORTS          7
1730 +#define GSW_PORT6              6
1731 +
1732 +#define GSW_MDIO_ACCESS                BIT(31)
1733 +#define GSW_MDIO_READ          BIT(19)
1734 +#define GSW_MDIO_WRITE         BIT(18)
1735 +#define GSW_MDIO_START         BIT(16)
1736 +#define GSW_MDIO_ADDR_SHIFT    20
1737 +#define GSW_MDIO_REG_SHIFT     25
1738 +
1739 +#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
1740 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1741 +#define GSW_REG_SMACCR0                0x3fE4
1742 +#define GSW_REG_SMACCR1                0x3fE8
1743 +#define GSW_REG_CKGCR          0x3ff0
1744 +
1745 +#define GSW_REG_IMR            0x7008
1746 +#define GSW_REG_ISR            0x700c
1747 +
1748 +#define SYSC_REG_CFG1          0x14
1749 +
1750 +#define PORT_IRQ_ST_CHG                0x7f
1751 +
1752 +#define SYSCFG1                        0x14
1753 +
1754 +#define ESW_PHY_POLLING                0x7000
1755 +
1756 +#define        PMCR_IPG                BIT(18)
1757 +#define        PMCR_MAC_MODE           BIT(16)
1758 +#define        PMCR_FORCE              BIT(15)
1759 +#define        PMCR_TX_EN              BIT(14)
1760 +#define        PMCR_RX_EN              BIT(13)
1761 +#define        PMCR_BACKOFF            BIT(9)
1762 +#define        PMCR_BACKPRES           BIT(8)
1763 +#define        PMCR_RX_FC              BIT(5)
1764 +#define        PMCR_TX_FC              BIT(4)
1765 +#define        PMCR_SPEED(_x)          (_x << 2)
1766 +#define        PMCR_DUPLEX             BIT(1)
1767 +#define        PMCR_LINK               BIT(0)
1768 +
1769 +#define PHY_AN_EN              BIT(31)
1770 +#define PHY_PRE_EN             BIT(30)
1771 +#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
1772 +
1773 +enum {
1774 +       /* Global attributes. */
1775 +       GSW_ATTR_ENABLE_VLAN,
1776 +       /* Port attributes. */
1777 +       GSW_ATTR_PORT_UNTAG,
1778 +};
1779 +
1780 +enum {
1781 +       PORT4_EPHY = 0,
1782 +       PORT4_EXT,
1783 +};
1784 +
1785 +struct mt7620_gsw {
1786 +       struct device           *dev;
1787 +       void __iomem            *base;
1788 +       int                     irq;
1789 +       int                     port4;
1790 +       long unsigned int       autopoll;
1791 +};
1792 +
1793 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1794 +{
1795 +       iowrite32(val, gsw->base + reg);
1796 +}
1797 +
1798 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1799 +{
1800 +       return ioread32(gsw->base + reg);
1801 +}
1802 +
1803 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1804 +{
1805 +       unsigned long t_start = jiffies;
1806 +
1807 +       while (1) {
1808 +               if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1809 +                       return 0;
1810 +               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1811 +                       break;
1812 +               }
1813 +       }
1814 +
1815 +       printk(KERN_ERR "mdio: MDIO timeout\n");
1816 +       return -1;
1817 +}
1818 +
1819 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1820 +                               u32 write_data)
1821 +{
1822 +       if (mt7620_mii_busy_wait(gsw))
1823 +               return -1;
1824 +
1825 +       write_data &= 0xffff;
1826 +
1827 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1828 +               (phy_register << GSW_MDIO_REG_SHIFT) |
1829 +               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1830 +               MT7620A_GSW_REG_PIAC);
1831 +
1832 +       if (mt7620_mii_busy_wait(gsw))
1833 +               return -1;
1834 +
1835 +       return 0;
1836 +}
1837 +
1838 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1839 +{
1840 +       u32 d;
1841 +
1842 +       if (mt7620_mii_busy_wait(gsw))
1843 +               return 0xffff;
1844 +
1845 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1846 +               (phy_reg << GSW_MDIO_REG_SHIFT) |
1847 +               (phy_addr << GSW_MDIO_ADDR_SHIFT),
1848 +               MT7620A_GSW_REG_PIAC);
1849 +
1850 +       if (mt7620_mii_busy_wait(gsw))
1851 +               return 0xffff;
1852 +
1853 +       d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1854 +
1855 +       return d;
1856 +}
1857 +
1858 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1859 +{
1860 +       struct fe_priv *priv = bus->priv;
1861 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1862 +
1863 +       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1864 +}
1865 +
1866 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1867 +{
1868 +       struct fe_priv *priv = bus->priv;
1869 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1870 +
1871 +       return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1872 +}
1873 +
1874 +static unsigned char *fe_speed_str(int speed)
1875 +{
1876 +       switch (speed) {
1877 +       case 2:
1878 +       case SPEED_1000:
1879 +               return "1000";
1880 +       case 1:
1881 +       case SPEED_100:
1882 +               return "100";
1883 +       case 0:
1884 +       case SPEED_10:
1885 +               return "10";
1886 +       }
1887 +
1888 +       return "? ";
1889 +}
1890 +
1891 +int mt7620a_has_carrier(struct fe_priv *priv)
1892 +{
1893 +        struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1894 +       int i;
1895 +
1896 +       for (i = 0; i < GSW_PORT6; i++)
1897 +               if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1898 +                       return 1;
1899 +       return 0;
1900 +}
1901 +
1902 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1903 +{
1904 +       if (!priv->phy)
1905 +               return;
1906 +
1907 +       if (mt7620a_has_carrier(priv))
1908 +               netif_carrier_on(priv->netdev);
1909 +       else
1910 +               netif_carrier_off(priv->netdev);
1911 +}
1912 +
1913 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1914 +{
1915 +       if (priv->link[port])
1916 +               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1917 +                       port, fe_speed_str(priv->phy->speed[port]),
1918 +                       (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1919 +       else
1920 +               netdev_info(priv->netdev, "port %d link down\n", port);
1921 +       mt7620a_handle_carrier(priv);
1922 +}
1923 +
1924 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1925 +{
1926 +       struct fe_priv *priv = (struct fe_priv *) _priv;
1927 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1928 +       u32 status;
1929 +       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1930 +
1931 +       status = gsw_r32(gsw, GSW_REG_ISR);
1932 +       if (status & PORT_IRQ_ST_CHG)
1933 +               for (i = 0; i <= max; i++) {
1934 +                       u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1935 +                       int link = status & 0x1;
1936 +
1937 +                       if (link != priv->link[i]) {
1938 +                               if (link)
1939 +                                       netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1940 +                                                       i, fe_speed_str((status >> 2) & 3),
1941 +                                                       (status & 0x2) ? "Full" : "Half");
1942 +                               else
1943 +                                       netdev_info(priv->netdev, "port %d link down\n", i);
1944 +                       }
1945 +
1946 +                       priv->link[i] = link;
1947 +               }
1948 +       mt7620a_handle_carrier(priv);
1949 +
1950 +       gsw_w32(gsw, status, GSW_REG_ISR);
1951 +
1952 +       return IRQ_HANDLED;
1953 +}
1954 +
1955 +static int mt7620_is_bga(void)
1956 +{
1957 +       u32 bga = rt_sysc_r32(0x0c);
1958 +
1959 +       return (bga >> 16) & 1;
1960 +}
1961 +
1962 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1963 +{
1964 +       int phy;
1965 +       int lsb = -1, msb = 0;
1966 +
1967 +       for_each_set_bit(phy, &gsw->autopoll, 32) {
1968 +               if (lsb < 0)
1969 +                       lsb = phy;
1970 +               msb = phy;
1971 +       }
1972 +
1973 +       gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1974 +}
1975 +
1976 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1977 +{
1978 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1979 +       const __be32 *_id = of_get_property(np, "reg", NULL);
1980 +       int phy_mode, size, id;
1981 +       int shift = 12;
1982 +       u32 val, mask = 0;
1983 +       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
1984 +
1985 +       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
1986 +               if (_id)
1987 +                       pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
1988 +               else
1989 +                       pr_err("%s: invalid port id\n", np->name);
1990 +               return;
1991 +       }
1992 +
1993 +       id = be32_to_cpu(*_id);
1994 +
1995 +       if (id == 4)
1996 +               shift = 14;
1997 +
1998 +       priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
1999 +       if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2000 +               pr_err("%s: invalid fixed link property\n", np->name);
2001 +               priv->phy->phy_fixed[id] = NULL;
2002 +               return;
2003 +       }
2004 +
2005 +       phy_mode = of_get_phy_mode(np);
2006 +       switch (phy_mode) {
2007 +       case PHY_INTERFACE_MODE_RGMII:
2008 +               mask = 0;
2009 +               break;
2010 +       case PHY_INTERFACE_MODE_MII:
2011 +               mask = 1;
2012 +               break;
2013 +       case PHY_INTERFACE_MODE_RMII:
2014 +               mask = 2;
2015 +               break;
2016 +       default:
2017 +               dev_err(priv->device, "port %d - invalid phy mode\n", id);
2018 +               return;
2019 +       }
2020 +
2021 +       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2022 +       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2023 +               return;
2024 +
2025 +       val = rt_sysc_r32(SYSCFG1);
2026 +       val &= ~(3 << shift);
2027 +       val |= mask << shift;
2028 +       rt_sysc_w32(val, SYSCFG1);
2029 +
2030 +       if (priv->phy->phy_fixed[id]) {
2031 +               const __be32 *link = priv->phy->phy_fixed[id];
2032 +               int tx_fc, rx_fc;
2033 +               u32 val = 0;
2034 +
2035 +               priv->phy->speed[id] = be32_to_cpup(link++);
2036 +               tx_fc = be32_to_cpup(link++);
2037 +               rx_fc = be32_to_cpup(link++);
2038 +               priv->phy->duplex[id] = be32_to_cpup(link++);
2039 +               priv->link[id] = 1;
2040 +
2041 +               switch (priv->phy->speed[id]) {
2042 +               case SPEED_10:
2043 +                       val = 0;
2044 +                       break;
2045 +               case SPEED_100:
2046 +                       val = 1;
2047 +                       break;
2048 +               case SPEED_1000:
2049 +                       val = 2;
2050 +                       break;
2051 +               default:
2052 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2053 +                       priv->phy->phy_fixed[id] = 0;
2054 +                       return;
2055 +               }
2056 +               val = PMCR_SPEED(val);
2057 +               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2058 +                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2059 +               if (tx_fc)
2060 +                       val |= PMCR_TX_FC;
2061 +               if (rx_fc)
2062 +                       val |= PMCR_RX_FC;
2063 +               if (priv->phy->duplex[id])
2064 +                       val |= PMCR_DUPLEX;
2065 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2066 +               dev_info(priv->device, "using fixed link parameters\n");
2067 +               return;
2068 +       }
2069 +
2070 +       if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2071 +               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2072 +                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
2073 +
2074 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2075 +               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2076 +               gsw->autopoll |= BIT(id);
2077 +               gsw_auto_poll(gsw);
2078 +               return;
2079 +       }
2080 +}
2081 +
2082 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2083 +{
2084 +       u32 is_BGA = mt7620_is_bga();
2085 +
2086 +       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2087 +       gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2088 +
2089 +       /*correct  PHY  setting L3.0 BGA*/
2090 +       _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2091 +
2092 +       _mt7620_mii_write(gsw, 1, 17, 0x7444);
2093 +       if (is_BGA)
2094 +               _mt7620_mii_write(gsw, 1, 19, 0x0114);
2095 +       else
2096 +               _mt7620_mii_write(gsw, 1, 19, 0x0117);
2097 +
2098 +       _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2099 +       _mt7620_mii_write(gsw, 1, 25, 0x6212);
2100 +       _mt7620_mii_write(gsw, 1, 26, 0x0777);
2101 +       _mt7620_mii_write(gsw, 1, 29, 0x4000);
2102 +       _mt7620_mii_write(gsw, 1, 28, 0xc077);
2103 +       _mt7620_mii_write(gsw, 1, 24, 0x0000);
2104 +
2105 +       _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2106 +       _mt7620_mii_write(gsw, 1, 17, 0x4838);
2107 +
2108 +       _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2109 +       if (is_BGA) {
2110 +               _mt7620_mii_write(gsw, 1, 21, 0x0515);
2111 +               _mt7620_mii_write(gsw, 1, 22, 0x0053);
2112 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2113 +               _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2114 +               _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2115 +               _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2116 +       } else {
2117 +               _mt7620_mii_write(gsw, 1, 21, 0x0517);
2118 +               _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2119 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2120 +               _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2121 +               _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2122 +               _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2123 +       }
2124 +       _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2125 +       _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2126 +
2127 +       _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2128 +       _mt7620_mii_write(gsw, 0, 30, 0xa000);
2129 +       _mt7620_mii_write(gsw, 1, 30, 0xa000);
2130 +       _mt7620_mii_write(gsw, 2, 30, 0xa000);
2131 +       _mt7620_mii_write(gsw, 3, 30, 0xa000);
2132 +
2133 +       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2134 +       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2135 +       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2136 +       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2137 +       _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2138 +       _mt7620_mii_write(gsw, 0, 16, 0x1111);
2139 +       _mt7620_mii_write(gsw, 1, 16, 0x1010);
2140 +       _mt7620_mii_write(gsw, 2, 16, 0x1515);
2141 +       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2142 +
2143 +       /* CPU Port6 Force Link 1G, FC ON */
2144 +       gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2145 +       /* Set Port6 CPU Port */
2146 +       gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2147 +
2148 +       /* setup port 4 */
2149 +       if (gsw->port4 == PORT4_EPHY) {
2150 +               u32 val = rt_sysc_r32(SYSCFG1);
2151 +               val |= 3 << 14;
2152 +               rt_sysc_w32(val, SYSCFG1);
2153 +               _mt7620_mii_write(gsw, 4, 30, 0xa000);
2154 +               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2155 +               _mt7620_mii_write(gsw, 4, 16, 0x1313);
2156 +               pr_info("gsw: setting port4 to ephy mode\n");
2157 +       }
2158 +}
2159 +
2160 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2161 +{
2162 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2163 +       unsigned long flags;
2164 +
2165 +       spin_lock_irqsave(&priv->page_lock, flags);
2166 +       gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2167 +       gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2168 +               GSW_REG_SMACCR0);
2169 +       spin_unlock_irqrestore(&priv->page_lock, flags);
2170 +}
2171 +
2172 +static struct of_device_id gsw_match[] = {
2173 +       { .compatible = "ralink,mt7620a-gsw" },
2174 +       {}
2175 +};
2176 +
2177 +int mt7620_gsw_config(struct fe_priv *priv)
2178 +{
2179 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2180 +
2181 +       /* is the mt7530 internal or external */
2182 +       if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef))
2183 +               mt7530_probe(priv->device, NULL, priv->mii_bus);
2184 +       else
2185 +               mt7530_probe(priv->device, gsw->base, NULL);
2186 +
2187 +       return 0;
2188 +}
2189 +
2190 +int mt7620_gsw_probe(struct fe_priv *priv)
2191 +{
2192 +       struct mt7620_gsw *gsw;
2193 +       struct device_node *np;
2194 +       const char *port4 = NULL;
2195 +
2196 +       np = of_find_matching_node(NULL, gsw_match);
2197 +       if (!np) {
2198 +               dev_err(priv->device, "no gsw node found\n");
2199 +               return -EINVAL;
2200 +       }
2201 +       np = of_node_get(np);
2202 +
2203 +       gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2204 +       if (!gsw) {
2205 +               dev_err(priv->device, "no gsw memory for private data\n");
2206 +               return -ENOMEM;
2207 +       }
2208 +
2209 +       gsw->irq = irq_of_parse_and_map(np, 0);
2210 +       if (!gsw->irq) {
2211 +               dev_err(priv->device, "no gsw irq resource found\n");
2212 +               return -ENOMEM;
2213 +       }
2214 +
2215 +       gsw->base = of_iomap(np, 0);
2216 +       if (!gsw->base) {
2217 +               dev_err(priv->device, "gsw ioremap failed\n");
2218 +               return -ENOMEM;
2219 +       }
2220 +
2221 +       gsw->dev = priv->device;
2222 +       priv->soc->swpriv = gsw;
2223 +
2224 +       of_property_read_string(np, "ralink,port4", &port4);
2225 +       if (port4 && !strcmp(port4, "ephy"))
2226 +               gsw->port4 = PORT4_EPHY;
2227 +       else if (port4 && !strcmp(port4, "gmac"))
2228 +               gsw->port4 = PORT4_EXT;
2229 +       else
2230 +               WARN_ON(port4);
2231 +
2232 +       gsw_hw_init(gsw);
2233 +
2234 +       gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2235 +       request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2236 +
2237 +       return 0;
2238 +}
2239 --- /dev/null
2240 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2241 @@ -0,0 +1,30 @@
2242 +/*
2243 + *   This program is free software; you can redistribute it and/or modify
2244 + *   it under the terms of the GNU General Public License as published by
2245 + *   the Free Software Foundation; version 2 of the License
2246 + *
2247 + *   This program is distributed in the hope that it will be useful,
2248 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2249 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2250 + *   GNU General Public License for more details.
2251 + *
2252 + *   You should have received a copy of the GNU General Public License
2253 + *   along with this program; if not, write to the Free Software
2254 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2255 + *
2256 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2257 + */
2258 +
2259 +#ifndef _RALINK_GSW_MT7620_H__
2260 +#define _RALINK_GSW_MT7620_H__
2261 +
2262 +extern int mt7620_gsw_config(struct fe_priv *priv);
2263 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2264 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2265 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2266 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2267 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2268 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2269 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2270 +
2271 +#endif
2272 --- /dev/null
2273 +++ b/drivers/net/ethernet/ralink/mdio.c
2274 @@ -0,0 +1,244 @@
2275 +/*
2276 + *   This program is free software; you can redistribute it and/or modify
2277 + *   it under the terms of the GNU General Public License as published by
2278 + *   the Free Software Foundation; version 2 of the License
2279 + *
2280 + *   This program is distributed in the hope that it will be useful,
2281 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2282 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2283 + *   GNU General Public License for more details.
2284 + *
2285 + *   You should have received a copy of the GNU General Public License
2286 + *   along with this program; if not, write to the Free Software
2287 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2288 + *
2289 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2290 + */
2291 +
2292 +#include <linux/module.h>
2293 +#include <linux/kernel.h>
2294 +#include <linux/types.h>
2295 +#include <linux/dma-mapping.h>
2296 +#include <linux/init.h>
2297 +#include <linux/skbuff.h>
2298 +#include <linux/etherdevice.h>
2299 +#include <linux/ethtool.h>
2300 +#include <linux/platform_device.h>
2301 +#include <linux/phy.h>
2302 +#include <linux/of_device.h>
2303 +#include <linux/clk.h>
2304 +#include <linux/of_net.h>
2305 +#include <linux/of_mdio.h>
2306 +
2307 +#include "ralink_soc_eth.h"
2308 +#include "mdio.h"
2309 +
2310 +static int fe_mdio_reset(struct mii_bus *bus)
2311 +{
2312 +       /* TODO */
2313 +       return 0;
2314 +}
2315 +
2316 +static void fe_phy_link_adjust(struct net_device *dev)
2317 +{
2318 +       struct fe_priv *priv = netdev_priv(dev);
2319 +       unsigned long flags;
2320 +       int i;
2321 +
2322 +       spin_lock_irqsave(&priv->phy->lock, flags);
2323 +       for (i = 0; i < 8; i++) {
2324 +               if (priv->phy->phy_node[i]) {
2325 +                       struct phy_device *phydev = priv->phy->phy[i];
2326 +                       int status_change = 0;
2327 +
2328 +                       if (phydev->link)
2329 +                               if (priv->phy->duplex[i] != phydev->duplex ||
2330 +                                               priv->phy->speed[i] != phydev->speed)
2331 +                                       status_change = 1;
2332 +
2333 +                       if (phydev->link != priv->link[i])
2334 +                               status_change = 1;
2335 +
2336 +                       switch (phydev->speed) {
2337 +                       case SPEED_1000:
2338 +                       case SPEED_100:
2339 +                       case SPEED_10:
2340 +                               priv->link[i] = phydev->link;
2341 +                               priv->phy->duplex[i] = phydev->duplex;
2342 +                               priv->phy->speed[i] = phydev->speed;
2343 +
2344 +                               if (status_change && priv->soc->mdio_adjust_link)
2345 +                                       priv->soc->mdio_adjust_link(priv, i);
2346 +                               break;
2347 +                       }
2348 +               }
2349 +       }
2350 +}
2351 +
2352 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2353 +{
2354 +       const __be32 *_port = NULL;
2355 +       struct phy_device *phydev;
2356 +       int phy_mode, port;
2357 +
2358 +       _port = of_get_property(phy_node, "reg", NULL);
2359 +
2360 +       if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2361 +               pr_err("%s: invalid port id\n", phy_node->name);
2362 +               return -EINVAL;
2363 +       }
2364 +       port = be32_to_cpu(*_port);
2365 +       phy_mode = of_get_phy_mode(phy_node);
2366 +       if (phy_mode < 0) {
2367 +               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2368 +               priv->phy->phy_node[port] = NULL;
2369 +               return -EINVAL;
2370 +       }
2371 +
2372 +       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2373 +                               0, phy_mode);
2374 +       if (IS_ERR(phydev)) {
2375 +               dev_err(priv->device, "could not connect to PHY\n");
2376 +               priv->phy->phy_node[port] = NULL;
2377 +               return PTR_ERR(phydev);
2378 +       }
2379 +
2380 +       phydev->supported &= PHY_GBIT_FEATURES;
2381 +       phydev->advertising = phydev->supported;
2382 +       phydev->no_auto_carrier_off = 1;
2383 +
2384 +       dev_info(priv->device,
2385 +                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2386 +                port, dev_name(&phydev->dev), phydev->phy_id,
2387 +                phydev->drv->name);
2388 +
2389 +       priv->phy->phy[port] = phydev;
2390 +       priv->link[port] = 0;
2391 +
2392 +       return 0;
2393 +}
2394 +
2395 +static int fe_phy_connect(struct fe_priv *priv)
2396 +{
2397 +       return 0;
2398 +}
2399 +
2400 +static void fe_phy_disconnect(struct fe_priv *priv)
2401 +{
2402 +       unsigned long flags;
2403 +       int i;
2404 +
2405 +       for (i = 0; i < 8; i++)
2406 +               if (priv->phy->phy_fixed[i]) {
2407 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2408 +                       priv->link[i] = 0;
2409 +                       if (priv->soc->mdio_adjust_link)
2410 +                               priv->soc->mdio_adjust_link(priv, i);
2411 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2412 +               } else if (priv->phy->phy[i]) {
2413 +                       phy_disconnect(priv->phy->phy[i]);
2414 +               }
2415 +}
2416 +
2417 +static void fe_phy_start(struct fe_priv *priv)
2418 +{
2419 +       unsigned long flags;
2420 +       int i;
2421 +
2422 +       for (i = 0; i < 8; i++) {
2423 +               if (priv->phy->phy_fixed[i]) {
2424 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2425 +                       priv->link[i] = 1;
2426 +                       if (priv->soc->mdio_adjust_link)
2427 +                               priv->soc->mdio_adjust_link(priv, i);
2428 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2429 +               } else if (priv->phy->phy[i]) {
2430 +                       phy_start(priv->phy->phy[i]);
2431 +               }
2432 +       }
2433 +}
2434 +
2435 +static void fe_phy_stop(struct fe_priv *priv)
2436 +{
2437 +       unsigned long flags;
2438 +       int i;
2439 +
2440 +       for (i = 0; i < 8; i++)
2441 +               if (priv->phy->phy_fixed[i]) {
2442 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2443 +                       priv->link[i] = 0;
2444 +                       if (priv->soc->mdio_adjust_link)
2445 +                               priv->soc->mdio_adjust_link(priv, i);
2446 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2447 +               } else if (priv->phy->phy[i]) {
2448 +                       phy_stop(priv->phy->phy[i]);
2449 +               }
2450 +}
2451 +
2452 +static struct fe_phy phy_ralink = {
2453 +       .connect = fe_phy_connect,
2454 +       .disconnect = fe_phy_disconnect,
2455 +       .start = fe_phy_start,
2456 +       .stop = fe_phy_stop,
2457 +};
2458 +
2459 +int fe_mdio_init(struct fe_priv *priv)
2460 +{
2461 +       struct device_node *mii_np;
2462 +       int err;
2463 +
2464 +       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2465 +               return 0;
2466 +
2467 +       spin_lock_init(&phy_ralink.lock);
2468 +       priv->phy = &phy_ralink;
2469 +
2470 +       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2471 +       if (!mii_np) {
2472 +               dev_err(priv->device, "no %s child node found", "mdio-bus");
2473 +               return -ENODEV;
2474 +       }
2475 +
2476 +       if (!of_device_is_available(mii_np)) {
2477 +               err = 0;
2478 +               goto err_put_node;
2479 +       }
2480 +
2481 +       priv->mii_bus = mdiobus_alloc();
2482 +       if (priv->mii_bus == NULL) {
2483 +               err = -ENOMEM;
2484 +               goto err_put_node;
2485 +       }
2486 +
2487 +       priv->mii_bus->name = "mdio";
2488 +       priv->mii_bus->read = priv->soc->mdio_read;
2489 +       priv->mii_bus->write = priv->soc->mdio_write;
2490 +       priv->mii_bus->reset = fe_mdio_reset;
2491 +       priv->mii_bus->irq = priv->mii_irq;
2492 +       priv->mii_bus->priv = priv;
2493 +       priv->mii_bus->parent = priv->device;
2494 +
2495 +       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2496 +       err = of_mdiobus_register(priv->mii_bus, mii_np);
2497 +       if (err)
2498 +               goto err_free_bus;
2499 +
2500 +       return 0;
2501 +
2502 +err_free_bus:
2503 +       kfree(priv->mii_bus);
2504 +err_put_node:
2505 +       of_node_put(mii_np);
2506 +       priv->mii_bus = NULL;
2507 +       return err;
2508 +}
2509 +
2510 +void fe_mdio_cleanup(struct fe_priv *priv)
2511 +{
2512 +       if (!priv->mii_bus)
2513 +               return;
2514 +
2515 +       mdiobus_unregister(priv->mii_bus);
2516 +       of_node_put(priv->mii_bus->dev.of_node);
2517 +       kfree(priv->mii_bus);
2518 +}
2519 --- /dev/null
2520 +++ b/drivers/net/ethernet/ralink/mdio.h
2521 @@ -0,0 +1,29 @@
2522 +/*
2523 + *   This program is free software; you can redistribute it and/or modify
2524 + *   it under the terms of the GNU General Public License as published by
2525 + *   the Free Software Foundation; version 2 of the License
2526 + *
2527 + *   This program is distributed in the hope that it will be useful,
2528 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2529 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2530 + *   GNU General Public License for more details.
2531 + *
2532 + *   You should have received a copy of the GNU General Public License
2533 + *   along with this program; if not, write to the Free Software
2534 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2535 + *
2536 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2537 + */
2538 +
2539 +#ifndef _RALINK_MDIO_H__
2540 +#define _RALINK_MDIO_H__
2541 +
2542 +#ifdef CONFIG_NET_RALINK_MDIO
2543 +extern int fe_mdio_init(struct fe_priv *priv);
2544 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2545 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2546 +#else
2547 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2548 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2549 +#endif
2550 +#endif
2551 --- /dev/null
2552 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
2553 @@ -0,0 +1,232 @@
2554 +/*
2555 + *   This program is free software; you can redistribute it and/or modify
2556 + *   it under the terms of the GNU General Public License as published by
2557 + *   the Free Software Foundation; version 2 of the License
2558 + *
2559 + *   This program is distributed in the hope that it will be useful,
2560 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2561 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2562 + *   GNU General Public License for more details.
2563 + *
2564 + *   You should have received a copy of the GNU General Public License
2565 + *   along with this program; if not, write to the Free Software
2566 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2567 + *
2568 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2569 + */
2570 +
2571 +#include <linux/module.h>
2572 +#include <linux/kernel.h>
2573 +#include <linux/types.h>
2574 +#include <linux/dma-mapping.h>
2575 +#include <linux/init.h>
2576 +#include <linux/skbuff.h>
2577 +#include <linux/etherdevice.h>
2578 +#include <linux/ethtool.h>
2579 +#include <linux/platform_device.h>
2580 +#include <linux/phy.h>
2581 +#include <linux/of_device.h>
2582 +#include <linux/clk.h>
2583 +#include <linux/of_net.h>
2584 +#include <linux/of_mdio.h>
2585 +
2586 +#include "ralink_soc_eth.h"
2587 +#include "mdio_rt2880.h"
2588 +#include "mdio.h"
2589 +
2590 +#define FE_MDIO_RETRY  1000
2591 +
2592 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2593 +{
2594 +       switch (priv->phy->speed[0]) {
2595 +       case SPEED_1000:
2596 +               return "1000";
2597 +       case SPEED_100:
2598 +               return "100";
2599 +       case SPEED_10:
2600 +               return "10";
2601 +       }
2602 +
2603 +       return "?";
2604 +}
2605 +
2606 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2607 +{
2608 +       u32 mdio_cfg;
2609 +
2610 +       if (!priv->link[0]) {
2611 +               netif_carrier_off(priv->netdev);
2612 +               netdev_info(priv->netdev, "link down\n");
2613 +               return;
2614 +       }
2615 +
2616 +       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2617 +                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
2618 +                  FE_MDIO_CFG_GP1_FRC_EN;
2619 +
2620 +       if (priv->phy->duplex[0] == DUPLEX_FULL)
2621 +               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2622 +
2623 +       if (priv->phy->tx_fc[0])
2624 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2625 +
2626 +       if (priv->phy->rx_fc[0])
2627 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2628 +
2629 +       switch (priv->phy->speed[0]) {
2630 +       case SPEED_10:
2631 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2632 +               break;
2633 +       case SPEED_100:
2634 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2635 +               break;
2636 +       case SPEED_1000:
2637 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2638 +               break;
2639 +       default:
2640 +               BUG();
2641 +       }
2642 +
2643 +       fe_w32(mdio_cfg, FE_MDIO_CFG);
2644 +
2645 +       netif_carrier_on(priv->netdev);
2646 +       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2647 +                   rt2880_speed_str(priv),
2648 +                   (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2649 +}
2650 +
2651 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2652 +{
2653 +       int retries;
2654 +
2655 +       retries = FE_MDIO_RETRY;
2656 +       while (1) {
2657 +               u32 t;
2658 +
2659 +               t = fe_r32(FE_MDIO_ACCESS);
2660 +               if ((t & (0x1 << 31)) == 0)
2661 +                       return 0;
2662 +
2663 +               if (retries-- == 0)
2664 +                       break;
2665 +
2666 +               udelay(1);
2667 +       }
2668 +
2669 +       dev_err(priv->device, "MDIO operation timed out\n");
2670 +       return -ETIMEDOUT;
2671 +}
2672 +
2673 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2674 +{
2675 +       struct fe_priv *priv = bus->priv;
2676 +       int err;
2677 +       u32 t;
2678 +
2679 +       err = rt2880_mdio_wait_ready(priv);
2680 +       if (err)
2681 +               return 0xffff;
2682 +
2683 +       t = (phy_addr << 24) | (phy_reg << 16);
2684 +       fe_w32(t, FE_MDIO_ACCESS);
2685 +       t |= (1 << 31);
2686 +       fe_w32(t, FE_MDIO_ACCESS);
2687 +
2688 +       err = rt2880_mdio_wait_ready(priv);
2689 +       if (err)
2690 +               return 0xffff;
2691 +
2692 +       pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2693 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2694 +
2695 +       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2696 +}
2697 +
2698 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2699 +{
2700 +       struct fe_priv *priv = bus->priv;
2701 +       int err;
2702 +       u32 t;
2703 +
2704 +       pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2705 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2706 +
2707 +       err = rt2880_mdio_wait_ready(priv);
2708 +       if (err)
2709 +               return err;
2710 +
2711 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2712 +       fe_w32(t, FE_MDIO_ACCESS);
2713 +       t |= (1 << 31);
2714 +       fe_w32(t, FE_MDIO_ACCESS);
2715 +
2716 +       return rt2880_mdio_wait_ready(priv);
2717 +}
2718 +
2719 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2720 +{
2721 +       const __be32 *id = of_get_property(np, "reg", NULL);
2722 +       const __be32 *link;
2723 +       int size;
2724 +       int phy_mode;
2725 +
2726 +       if (!id || (be32_to_cpu(*id) != 0)) {
2727 +               pr_err("%s: invalid port id\n", np->name);
2728 +               return;
2729 +       }
2730 +
2731 +       priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2732 +       if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2733 +               pr_err("%s: invalid fixed link property\n", np->name);
2734 +               priv->phy->phy_fixed[0] = NULL;
2735 +               return;
2736 +       }
2737 +
2738 +       phy_mode = of_get_phy_mode(np);
2739 +       switch (phy_mode) {
2740 +       case PHY_INTERFACE_MODE_RGMII:
2741 +               break;
2742 +       case PHY_INTERFACE_MODE_MII:
2743 +               break;
2744 +       case PHY_INTERFACE_MODE_RMII:
2745 +               break;
2746 +       default:
2747 +               if (!priv->phy->phy_fixed[0])
2748 +                       dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2749 +               break;
2750 +       }
2751 +
2752 +       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2753 +       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2754 +               return;
2755 +
2756 +       if (priv->phy->phy_fixed[0]) {
2757 +               link = priv->phy->phy_fixed[0];
2758 +               priv->phy->speed[0] = be32_to_cpup(link++);
2759 +               priv->phy->duplex[0] = be32_to_cpup(link++);
2760 +               priv->phy->tx_fc[0] = be32_to_cpup(link++);
2761 +               priv->phy->rx_fc[0] = be32_to_cpup(link++);
2762 +
2763 +               priv->link[0] = 1;
2764 +               switch (priv->phy->speed[0]) {
2765 +               case SPEED_10:
2766 +                       break;
2767 +               case SPEED_100:
2768 +                       break;
2769 +               case SPEED_1000:
2770 +                       break;
2771 +               default:
2772 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2773 +                       priv->phy->phy_fixed[0] = 0;
2774 +                       return;
2775 +               }
2776 +               dev_info(priv->device, "using fixed link parameters\n");
2777 +               rt2880_mdio_link_adjust(priv, 0);
2778 +               return;
2779 +       }
2780 +       if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2781 +               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2782 +       }
2783 +
2784 +       return;
2785 +}
2786 --- /dev/null
2787 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
2788 @@ -0,0 +1,26 @@
2789 +/*
2790 + *   This program is free software; you can redistribute it and/or modify
2791 + *   it under the terms of the GNU General Public License as published by
2792 + *   the Free Software Foundation; version 2 of the License
2793 + *
2794 + *   This program is distributed in the hope that it will be useful,
2795 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2796 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2797 + *   GNU General Public License for more details.
2798 + *
2799 + *   You should have received a copy of the GNU General Public License
2800 + *   along with this program; if not, write to the Free Software
2801 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2802 + *
2803 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2804 + */
2805 +
2806 +#ifndef _RALINK_MDIO_RT2880_H__
2807 +#define _RALINK_MDIO_RT2880_H__
2808 +
2809 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2810 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2811 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2812 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2813 +
2814 +#endif
2815 --- /dev/null
2816 +++ b/drivers/net/ethernet/ralink/mt7530.c
2817 @@ -0,0 +1,579 @@
2818 +/*
2819 + * This program is free software; you can redistribute it and/or
2820 + * modify it under the terms of the GNU General Public License
2821 + * as published by the Free Software Foundation; either version 2
2822 + * of the License, or (at your option) any later version.
2823 + *
2824 + * This program is distributed in the hope that it will be useful,
2825 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2826 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2827 + * GNU General Public License for more details.
2828 + *
2829 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
2830 + */
2831 +
2832 +#include <linux/if.h>
2833 +#include <linux/module.h>
2834 +#include <linux/init.h>
2835 +#include <linux/list.h>
2836 +#include <linux/if_ether.h>
2837 +#include <linux/skbuff.h>
2838 +#include <linux/netdevice.h>
2839 +#include <linux/netlink.h>
2840 +#include <linux/bitops.h>
2841 +#include <net/genetlink.h>
2842 +#include <linux/switch.h>
2843 +#include <linux/delay.h>
2844 +#include <linux/phy.h>
2845 +#include <linux/netdevice.h>
2846 +#include <linux/etherdevice.h>
2847 +#include <linux/lockdep.h>
2848 +#include <linux/workqueue.h>
2849 +#include <linux/of_device.h>
2850 +
2851 +#include "mt7530.h"
2852 +
2853 +#define MT7530_CPU_PORT                6
2854 +#define MT7530_NUM_PORTS       8
2855 +#define MT7530_NUM_VLANS       16
2856 +#define MT7530_MAX_VID         4095
2857 +#define MT7530_MIN_VID         0
2858 +
2859 +/* registers */
2860 +#define REG_ESW_VLAN_VTCR              0x90
2861 +#define REG_ESW_VLAN_VAWD1             0x94
2862 +#define REG_ESW_VLAN_VAWD2             0x98
2863 +#define REG_ESW_VLAN_VTIM(x)   (0x100 + 4 * ((x) / 2))
2864 +
2865 +#define REG_ESW_VLAN_VAWD1_IVL_MAC     BIT(30)
2866 +#define REG_ESW_VLAN_VAWD1_VTAG_EN     BIT(28)
2867 +#define REG_ESW_VLAN_VAWD1_VALID       BIT(0)
2868 +
2869 +/* vlan egress mode */
2870 +enum {
2871 +       ETAG_CTRL_UNTAG = 0,
2872 +       ETAG_CTRL_TAG   = 2,
2873 +       ETAG_CTRL_SWAP  = 1,
2874 +       ETAG_CTRL_STACK = 3,
2875 +};
2876 +
2877 +#define REG_ESW_PORT_PCR(x)    (0x2004 | ((x) << 8))
2878 +#define REG_ESW_PORT_PVC(x)    (0x2010 | ((x) << 8))
2879 +#define REG_ESW_PORT_PPBV1(x)  (0x2014 | ((x) << 8))
2880 +enum {
2881 +       /* Global attributes. */
2882 +       MT7530_ATTR_ENABLE_VLAN,
2883 +};
2884 +
2885 +struct mt7530_port_entry {
2886 +       u16     pvid;
2887 +};
2888 +
2889 +struct mt7530_vlan_entry {
2890 +       u16     vid;
2891 +       u8      member;
2892 +       u8      etags;
2893 +};
2894 +
2895 +struct mt7530_priv {
2896 +       void __iomem            *base;
2897 +       struct mii_bus          *bus;
2898 +       struct switch_dev       swdev;
2899 +
2900 +       bool                    global_vlan_enable;
2901 +       struct mt7530_vlan_entry        vlan_entries[MT7530_NUM_VLANS];
2902 +       struct mt7530_port_entry        port_entries[MT7530_NUM_PORTS];
2903 +};
2904 +
2905 +struct mt7530_mapping {
2906 +       char    *name;
2907 +       u16     pvids[MT7530_NUM_PORTS];
2908 +       u8      members[MT7530_NUM_VLANS];
2909 +       u8      etags[MT7530_NUM_VLANS];
2910 +       u16     vids[MT7530_NUM_VLANS];
2911 +} mt7530_defaults[] = {
2912 +       {
2913 +               .name = "llllw",
2914 +               .pvids = { 1, 1, 1, 1, 2, 1, 1 },
2915 +               .members = { 0, 0x6f, 0x50 },
2916 +               .etags = { 0, 0x40, 0x40 },
2917 +               .vids = { 0, 1, 2 },
2918 +       }, {
2919 +               .name = "wllll",
2920 +               .pvids = { 2, 1, 1, 1, 1, 1, 1 },
2921 +               .members = { 0, 0x7e, 0x41 },
2922 +               .etags = { 0, 0x40, 0x40 },
2923 +               .vids = { 0, 1, 2 },
2924 +       },
2925 +};
2926 +
2927 +struct mt7530_mapping*
2928 +mt7530_find_mapping(struct device_node *np)
2929 +{
2930 +       const char *map;
2931 +       int i;
2932 +
2933 +       if (of_property_read_string(np, "ralink,port-map", &map))
2934 +               return NULL;
2935 +
2936 +       for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
2937 +               if (!strcmp(map, mt7530_defaults[i].name))
2938 +                       return &mt7530_defaults[i];
2939 +
2940 +       return NULL;
2941 +}
2942 +
2943 +static void
2944 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
2945 +{
2946 +       int i = 0;
2947 +
2948 +       mt7530->global_vlan_enable = 1;
2949 +
2950 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
2951 +               mt7530->port_entries[i].pvid = map->pvids[i];
2952 +
2953 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
2954 +               mt7530->vlan_entries[i].member = map->members[i];
2955 +               mt7530->vlan_entries[i].etags = map->etags[i];
2956 +               mt7530->vlan_entries[i].vid = map->vids[i];
2957 +       }
2958 +}
2959 +
2960 +static int
2961 +mt7530_reset_switch(struct switch_dev *dev)
2962 +{
2963 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
2964 +       int i;
2965 +
2966 +       memset(priv->port_entries, 0, sizeof(priv->port_entries));
2967 +       memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
2968 +
2969 +       /* set default vid of each vlan to the same number of vlan, so the vid
2970 +        * won't need be set explicitly.
2971 +        */
2972 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
2973 +               priv->vlan_entries[i].vid = i;
2974 +       }
2975 +
2976 +       return 0;
2977 +}
2978 +
2979 +static int
2980 +mt7530_get_vlan_enable(struct switch_dev *dev,
2981 +                          const struct switch_attr *attr,
2982 +                          struct switch_val *val)
2983 +{
2984 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
2985 +
2986 +       val->value.i = priv->global_vlan_enable;
2987 +
2988 +       return 0;
2989 +}
2990 +
2991 +static int
2992 +mt7530_set_vlan_enable(struct switch_dev *dev,
2993 +                          const struct switch_attr *attr,
2994 +                          struct switch_val *val)
2995 +{
2996 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
2997 +
2998 +       priv->global_vlan_enable = val->value.i != 0;
2999 +
3000 +       return 0;
3001 +}
3002 +
3003 +static u32
3004 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
3005 +{
3006 +       u32 val;
3007 +       if (priv->bus) {
3008 +               u16 high, low;
3009 +
3010 +               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3011 +               low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
3012 +               high = mdiobus_read(priv->bus, 0x1f, 0x10);
3013 +
3014 +               return (high << 16) | (low & 0xffff);
3015 +       }
3016 +
3017 +       val = ioread32(priv->base + reg);
3018 +       pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
3019 +
3020 +       return val;
3021 +}
3022 +
3023 +static void
3024 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
3025 +{
3026 +       if (priv->bus) {
3027 +               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3028 +               mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
3029 +               mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
3030 +               return;
3031 +       }
3032 +
3033 +       pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
3034 +       iowrite32(val, priv->base + reg);
3035 +}
3036 +
3037 +static void
3038 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
3039 +{
3040 +       int i;
3041 +
3042 +       mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
3043 +
3044 +       for (i = 0; i < 20; i++) {
3045 +               u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
3046 +
3047 +               if ((val & BIT(31)) == 0)
3048 +                       break;
3049 +
3050 +               udelay(1000);
3051 +       }
3052 +       if (i == 20)
3053 +               printk("mt7530: vtcr timeout\n");
3054 +}
3055 +
3056 +static int
3057 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
3058 +{
3059 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3060 +
3061 +       if (port >= MT7530_NUM_PORTS)
3062 +               return -EINVAL;
3063 +
3064 +       *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
3065 +       *val &= 0xfff;
3066 +
3067 +       return 0;
3068 +}
3069 +
3070 +static int
3071 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
3072 +{
3073 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3074 +
3075 +       if (port >= MT7530_NUM_PORTS)
3076 +               return -EINVAL;
3077 +
3078 +       if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
3079 +               return -EINVAL;
3080 +
3081 +       priv->port_entries[port].pvid = pvid;
3082 +
3083 +       return 0;
3084 +}
3085 +
3086 +static int
3087 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3088 +{
3089 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3090 +       u32 member;
3091 +       u32 etags;
3092 +       int i;
3093 +
3094 +       val->len = 0;
3095 +
3096 +       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
3097 +               return -EINVAL;
3098 +
3099 +       mt7530_vtcr(priv, 0, val->port_vlan);
3100 +
3101 +       member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
3102 +       member >>= 16;
3103 +       member &= 0xff;
3104 +
3105 +       etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
3106 +
3107 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
3108 +               struct switch_port *p;
3109 +               int etag;
3110 +
3111 +               if (!(member & BIT(i)))
3112 +                       continue;
3113 +
3114 +               p = &val->value.ports[val->len++];
3115 +               p->id = i;
3116 +
3117 +               etag = (etags >> (i * 2)) & 0x3;
3118 +
3119 +               if (etag == ETAG_CTRL_TAG)
3120 +                       p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
3121 +               else if (etag != ETAG_CTRL_UNTAG)
3122 +                       printk("vlan egress tag control neither untag nor tag.\n");
3123 +       }
3124 +
3125 +       return 0;
3126 +}
3127 +
3128 +static int
3129 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3130 +{
3131 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3132 +       u8 member = 0;
3133 +       u8 etags = 0;
3134 +       int i;
3135 +
3136 +       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
3137 +                       val->len > MT7530_NUM_PORTS)
3138 +               return -EINVAL;
3139 +
3140 +       for (i = 0; i < val->len; i++) {
3141 +               struct switch_port *p = &val->value.ports[i];
3142 +
3143 +               if (p->id >= MT7530_NUM_PORTS)
3144 +                       return -EINVAL;
3145 +
3146 +               member |= BIT(p->id);
3147 +
3148 +               if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
3149 +                       etags |= BIT(p->id);
3150 +       }
3151 +       priv->vlan_entries[val->port_vlan].member = member;
3152 +       priv->vlan_entries[val->port_vlan].etags = etags;
3153 +
3154 +       return 0;
3155 +}
3156 +
3157 +static int
3158 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
3159 +               struct switch_val *val)
3160 +{
3161 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3162 +       int vlan;
3163 +       u16 vid;
3164 +
3165 +       vlan = val->port_vlan;
3166 +       vid = (u16)val->value.i;
3167 +
3168 +       if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
3169 +               return -EINVAL;
3170 +
3171 +       if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
3172 +               return -EINVAL;
3173 +
3174 +       priv->vlan_entries[vlan].vid = vid;
3175 +       return 0;
3176 +}
3177 +
3178 +static int
3179 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
3180 +               struct switch_val *val)
3181 +{
3182 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3183 +       u32 vid;
3184 +       int vlan;
3185 +
3186 +       vlan = val->port_vlan;
3187 +
3188 +       vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
3189 +       if (vlan & 1)
3190 +               vid = vid >> 12;
3191 +       vid &= 0xfff;
3192 +
3193 +       val->value.i = vid;
3194 +       return 0;
3195 +}
3196 +
3197 +static int
3198 +mt7530_apply_config(struct switch_dev *dev)
3199 +{
3200 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3201 +       int i, j;
3202 +
3203 +       if (!priv->global_vlan_enable) {
3204 +               for (i = 0; i < MT7530_NUM_PORTS; i++)
3205 +                       mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0000);
3206 +
3207 +               for (i = 0; i < MT7530_NUM_PORTS; i++)
3208 +                       mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x8100000c);
3209 +
3210 +               return 0;
3211 +       }
3212 +
3213 +       /* set all ports as security mode */
3214 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
3215 +               mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
3216 +
3217 +       /* set all ports as user port */
3218 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
3219 +               mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x81000000);
3220 +
3221 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
3222 +               u16 vid = priv->vlan_entries[i].vid;
3223 +               u8 member = priv->vlan_entries[i].member;
3224 +               u8 etags = priv->vlan_entries[i].etags;
3225 +               u32 val;
3226 +
3227 +               /* vid of vlan */
3228 +               val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
3229 +               if (i % 2 == 0) {
3230 +                       val &= 0xfff000;
3231 +                       val |= vid;
3232 +               } else {
3233 +                       val &= 0xfff;
3234 +                       val |= (vid << 12);
3235 +               }
3236 +               mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
3237 +
3238 +               /* vlan port membership */
3239 +               if (member)
3240 +                       mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
3241 +                               REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
3242 +                               REG_ESW_VLAN_VAWD1_VALID);
3243 +               else
3244 +                       mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
3245 +
3246 +               /* egress mode */
3247 +               val = 0;
3248 +               for (j = 0; j < MT7530_NUM_PORTS; j++) {
3249 +                       if (etags & BIT(j))
3250 +                               val |= ETAG_CTRL_TAG << (j * 2);
3251 +                       else
3252 +                               val |= ETAG_CTRL_UNTAG << (j * 2);
3253 +               }
3254 +               mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
3255 +
3256 +               /* write to vlan table */
3257 +               mt7530_vtcr(priv, 1, i);
3258 +       }
3259 +
3260 +       /* Port Default PVID */
3261 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
3262 +               u32 val;
3263 +               val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
3264 +               val &= ~0xfff;
3265 +               val |= priv->port_entries[i].pvid;
3266 +               mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
3267 +       }
3268 +
3269 +       return 0;
3270 +}
3271 +
3272 +static int
3273 +mt7530_get_port_link(struct switch_dev *dev,  int port,
3274 +                       struct switch_port_link *link)
3275 +{
3276 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3277 +       u32 speed, pmsr;
3278 +
3279 +       if (port < 0 || port >= MT7530_NUM_PORTS)
3280 +               return -EINVAL;
3281 +
3282 +       pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
3283 +
3284 +       link->link = pmsr & 1;
3285 +       link->duplex = (pmsr >> 1) & 1;
3286 +       speed = (pmsr >> 2) & 3;
3287 +
3288 +       switch (speed) {
3289 +       case 0:
3290 +               link->speed = SWITCH_PORT_SPEED_10;
3291 +               break;
3292 +       case 1:
3293 +               link->speed = SWITCH_PORT_SPEED_100;
3294 +               break;
3295 +       case 2:
3296 +       case 3: /* forced gige speed can be 2 or 3 */
3297 +               link->speed = SWITCH_PORT_SPEED_1000;
3298 +               break;
3299 +       default:
3300 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
3301 +               break;
3302 +       }
3303 +
3304 +       return 0;
3305 +}
3306 +
3307 +static const struct switch_attr mt7530_global[] = {
3308 +       {
3309 +               .type = SWITCH_TYPE_INT,
3310 +               .name = "enable_vlan",
3311 +               .description = "VLAN mode (1:enabled)",
3312 +               .max = 1,
3313 +               .id = MT7530_ATTR_ENABLE_VLAN,
3314 +               .get = mt7530_get_vlan_enable,
3315 +               .set = mt7530_set_vlan_enable,
3316 +       },
3317 +};
3318 +
3319 +static const struct switch_attr mt7530_port[] = {
3320 +};
3321 +
3322 +static const struct switch_attr mt7530_vlan[] = {
3323 +       {
3324 +               .type = SWITCH_TYPE_INT,
3325 +               .name = "vid",
3326 +               .description = "VLAN ID (0-4094)",
3327 +               .set = mt7530_set_vid,
3328 +               .get = mt7530_get_vid,
3329 +               .max = 4094,
3330 +       },
3331 +};
3332 +
3333 +static const struct switch_dev_ops mt7530_ops = {
3334 +       .attr_global = {
3335 +               .attr = mt7530_global,
3336 +               .n_attr = ARRAY_SIZE(mt7530_global),
3337 +       },
3338 +       .attr_port = {
3339 +               .attr = mt7530_port,
3340 +               .n_attr = ARRAY_SIZE(mt7530_port),
3341 +       },
3342 +       .attr_vlan = {
3343 +               .attr = mt7530_vlan,
3344 +               .n_attr = ARRAY_SIZE(mt7530_vlan),
3345 +       },
3346 +       .get_vlan_ports = mt7530_get_vlan_ports,
3347 +       .set_vlan_ports = mt7530_set_vlan_ports,
3348 +       .get_port_pvid = mt7530_get_port_pvid,
3349 +       .set_port_pvid = mt7530_set_port_pvid,
3350 +       .get_port_link = mt7530_get_port_link,
3351 +       .apply_config = mt7530_apply_config,
3352 +       .reset_switch = mt7530_reset_switch,
3353 +};
3354 +
3355 +int
3356 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
3357 +{
3358 +       struct switch_dev *swdev;
3359 +       struct mt7530_priv *mt7530;
3360 +       struct mt7530_mapping *map;
3361 +       int ret;
3362 +
3363 +       if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
3364 +               return 0;
3365 +
3366 +       mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
3367 +       if (!mt7530)
3368 +               return -ENOMEM;
3369 +
3370 +       mt7530->base = base;
3371 +       mt7530->bus = bus;
3372 +       mt7530->global_vlan_enable = 1;
3373 +
3374 +       swdev = &mt7530->swdev;
3375 +       swdev->name = "mt7530";
3376 +       swdev->alias = "mt7530";
3377 +       swdev->cpu_port = MT7530_CPU_PORT;
3378 +       swdev->ports = MT7530_NUM_PORTS;
3379 +       swdev->vlans = MT7530_NUM_VLANS;
3380 +       swdev->ops = &mt7530_ops;
3381 +
3382 +       ret = register_switch(swdev, NULL);
3383 +       if (ret) {
3384 +               dev_err(dev, "failed to register mt7530\n");
3385 +               return ret;
3386 +       }
3387 +
3388 +       dev_info(dev, "loaded mt7530 driver\n");
3389 +
3390 +       map = mt7530_find_mapping(dev->of_node);
3391 +       if (map)
3392 +               mt7530_apply_mapping(mt7530, map);
3393 +       mt7530_apply_config(swdev);
3394 +
3395 +       return 0;
3396 +}
3397 --- /dev/null
3398 +++ b/drivers/net/ethernet/ralink/mt7530.h
3399 @@ -0,0 +1,20 @@
3400 +/*
3401 + * This program is free software; you can redistribute it and/or
3402 + * modify it under the terms of the GNU General Public License
3403 + * as published by the Free Software Foundation; either version 2
3404 + * of the License, or (at your option) any later version.
3405 + *
3406 + * This program is distributed in the hope that it will be useful,
3407 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3408 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3409 + * GNU General Public License for more details.
3410 + *
3411 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
3412 + */
3413 +
3414 +#ifndef _MT7530_H__
3415 +#define _MT7530_H__
3416 +
3417 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);
3418 +
3419 +#endif
3420 --- /dev/null
3421 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3422 @@ -0,0 +1,845 @@
3423 +/*
3424 + *   This program is free software; you can redistribute it and/or modify
3425 + *   it under the terms of the GNU General Public License as published by
3426 + *   the Free Software Foundation; version 2 of the License
3427 + *
3428 + *   This program is distributed in the hope that it will be useful,
3429 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3430 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3431 + *   GNU General Public License for more details.
3432 + *
3433 + *   You should have received a copy of the GNU General Public License
3434 + *   along with this program; if not, write to the Free Software
3435 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3436 + *
3437 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3438 + */
3439 +
3440 +#include <linux/module.h>
3441 +#include <linux/kernel.h>
3442 +#include <linux/types.h>
3443 +#include <linux/dma-mapping.h>
3444 +#include <linux/init.h>
3445 +#include <linux/skbuff.h>
3446 +#include <linux/etherdevice.h>
3447 +#include <linux/ethtool.h>
3448 +#include <linux/platform_device.h>
3449 +#include <linux/of_device.h>
3450 +#include <linux/clk.h>
3451 +#include <linux/of_net.h>
3452 +#include <linux/of_mdio.h>
3453 +#include <linux/if_vlan.h>
3454 +#include <linux/reset.h>
3455 +
3456 +#include <asm/mach-ralink/ralink_regs.h>
3457 +
3458 +#include "ralink_soc_eth.h"
3459 +#include "esw_rt3052.h"
3460 +#include "mdio.h"
3461 +
3462 +#define TX_TIMEOUT             (2 * HZ)
3463 +#define        MAX_RX_LENGTH           1536
3464 +#define DMA_DUMMY_DESC         0xffffffff
3465 +
3466 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3467 +       [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3468 +       [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3469 +       [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3470 +       [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3471 +       [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3472 +       [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3473 +       [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3474 +       [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3475 +       [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3476 +       [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3477 +       [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3478 +};
3479 +
3480 +static const u32 *fe_reg_table = fe_reg_table_default;
3481 +
3482 +static void __iomem *fe_base = 0;
3483 +
3484 +void fe_w32(u32 val, unsigned reg)
3485 +{
3486 +       __raw_writel(val, fe_base + reg);
3487 +}
3488 +
3489 +u32 fe_r32(unsigned reg)
3490 +{
3491 +       return __raw_readl(fe_base + reg);
3492 +}
3493 +
3494 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3495 +{
3496 +       fe_w32(val, fe_reg_table[reg]);
3497 +}
3498 +
3499 +static inline u32 fe_reg_r32(enum fe_reg reg)
3500 +{
3501 +       return fe_r32(fe_reg_table[reg]);
3502 +}
3503 +
3504 +static inline void fe_int_disable(u32 mask)
3505 +{
3506 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3507 +                    FE_REG_FE_INT_ENABLE);
3508 +       /* flush write */
3509 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3510 +}
3511 +
3512 +static inline void fe_int_enable(u32 mask)
3513 +{
3514 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3515 +                    FE_REG_FE_INT_ENABLE);
3516 +       /* flush write */
3517 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3518 +}
3519 +
3520 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3521 +{
3522 +       unsigned long flags;
3523 +
3524 +       spin_lock_irqsave(&priv->page_lock, flags);
3525 +       fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3526 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3527 +                    FE_GDMA1_MAC_ADRL);
3528 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3529 +}
3530 +
3531 +static int fe_set_mac_address(struct net_device *dev, void *p)
3532 +{
3533 +       int ret = eth_mac_addr(dev, p);
3534 +
3535 +       if (!ret) {
3536 +               struct fe_priv *priv = netdev_priv(dev);
3537 +
3538 +               if (priv->soc->set_mac)
3539 +                       priv->soc->set_mac(priv, dev->dev_addr);
3540 +               else
3541 +                       fe_hw_set_macaddr(priv, p);
3542 +       }
3543 +
3544 +       return ret;
3545 +}
3546 +
3547 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3548 +{
3549 +       struct sk_buff *skb;
3550 +
3551 +       skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3552 +       if (!skb)
3553 +               return NULL;
3554 +
3555 +       skb_reserve(skb, NET_IP_ALIGN);
3556 +
3557 +       return skb;
3558 +}
3559 +
3560 +static int fe_alloc_rx(struct fe_priv *priv)
3561 +{
3562 +       int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3563 +       int i;
3564 +
3565 +       priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3566 +                                       &priv->rx_phys, GFP_ATOMIC);
3567 +       if (!priv->rx_dma)
3568 +               return -ENOMEM;
3569 +
3570 +       memset(priv->rx_dma, 0, size);
3571 +
3572 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3573 +               priv->rx_skb[i] = fe_alloc_skb(priv);
3574 +               if (!priv->rx_skb[i])
3575 +                       return -ENOMEM;
3576 +       }
3577 +
3578 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3579 +               dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3580 +                                               priv->rx_skb[i]->data,
3581 +                                               MAX_RX_LENGTH,
3582 +                                               DMA_FROM_DEVICE);
3583 +               priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3584 +
3585 +               if (priv->soc->rx_dma)
3586 +                       priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3587 +               else
3588 +                       priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3589 +       }
3590 +       wmb();
3591 +
3592 +       fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3593 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3594 +       fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3595 +       fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3596 +
3597 +       return 0;
3598 +}
3599 +
3600 +static int fe_alloc_tx(struct fe_priv *priv)
3601 +{
3602 +       int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3603 +       int i;
3604 +
3605 +       priv->tx_free_idx = 0;
3606 +
3607 +       priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3608 +                                       &priv->tx_phys, GFP_ATOMIC);
3609 +       if (!priv->tx_dma)
3610 +               return -ENOMEM;
3611 +
3612 +       memset(priv->tx_dma, 0, size);
3613 +
3614 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3615 +               if (priv->soc->tx_dma) {
3616 +                       priv->soc->tx_dma(priv, i, NULL);
3617 +                       continue;
3618 +               }
3619 +
3620 +               priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3621 +               priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3622 +       }
3623 +
3624 +       fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3625 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3626 +       fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3627 +       fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3628 +
3629 +       return 0;
3630 +}
3631 +
3632 +static void fe_free_dma(struct fe_priv *priv)
3633 +{
3634 +       int i;
3635 +
3636 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3637 +               if (priv->rx_skb[i]) {
3638 +                       dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3639 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3640 +                       dev_kfree_skb_any(priv->rx_skb[i]);
3641 +                       priv->rx_skb[i] = NULL;
3642 +               }
3643 +
3644 +               if (priv->tx_skb[i]) {
3645 +                       dev_kfree_skb_any(priv->tx_skb[i]);
3646 +                       priv->tx_skb[i] = NULL;
3647 +               }
3648 +       }
3649 +
3650 +       if (priv->rx_dma) {
3651 +               int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3652 +               dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3653 +                                       priv->rx_phys);
3654 +       }
3655 +
3656 +       if (priv->tx_dma) {
3657 +               int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3658 +               dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3659 +                                       priv->tx_phys);
3660 +       }
3661 +
3662 +       netdev_reset_queue(priv->netdev);
3663 +}
3664 +
3665 +static void fe_start_tso(struct sk_buff *skb, struct net_device *dev, unsigned int nr_frags, int idx)
3666 +{
3667 +        struct fe_priv *priv = netdev_priv(dev);
3668 +       struct skb_frag_struct *frag;
3669 +       int i;
3670 +
3671 +       for (i = 0; i < nr_frags; i++) {
3672 +               dma_addr_t mapped_addr;
3673 +
3674 +               frag = &skb_shinfo(skb)->frags[i];
3675 +               mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
3676 +               if (i % 2) {
3677 +                       idx = (idx + 1) % NUM_DMA_DESC;
3678 +                       priv->tx_dma[idx].txd1 = mapped_addr;
3679 +                       if (i == nr_frags - 1)
3680 +                               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(frag->size);
3681 +                       else
3682 +                               priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(frag->size);
3683 +               } else {
3684 +                       priv->tx_dma[idx].txd3 = mapped_addr;
3685 +                       if (i == nr_frags - 1)
3686 +                               priv->tx_dma[idx].txd2 |= TX_DMA_LS1 | TX_DMA_PLEN1(frag->size);
3687 +                       else
3688 +                               priv->tx_dma[idx].txd2 |= TX_DMA_PLEN1(frag->size);
3689 +               }
3690 +       }
3691 +}
3692 +
3693 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3694 +{
3695 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3696 +       struct fe_priv *priv = netdev_priv(dev);
3697 +       dma_addr_t mapped_addr;
3698 +       u32 tx_next, tx, tx_num = 1;
3699 +       int i;
3700 +
3701 +       if (priv->soc->min_pkt_len) {
3702 +               if (skb->len < priv->soc->min_pkt_len) {
3703 +                       if (skb_padto(skb, priv->soc->min_pkt_len)) {
3704 +                               printk(KERN_ERR
3705 +                                      "fe_eth: skb_padto failed\n");
3706 +                               kfree_skb(skb);
3707 +                               return 0;
3708 +                       }
3709 +                       skb_put(skb, priv->soc->min_pkt_len - skb->len);
3710 +               }
3711 +       }
3712 +
3713 +       dev->trans_start = jiffies;
3714 +       mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3715 +                               skb->len, DMA_TO_DEVICE);
3716 +
3717 +       spin_lock(&priv->page_lock);
3718 +
3719 +       tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3720 +       if (priv->soc->tso && nr_frags)
3721 +               tx_num += nr_frags >> 1;
3722 +       tx_next = (tx + tx_num) % NUM_DMA_DESC;
3723 +       if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3724 +                       !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3725 +                       !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3726 +       {
3727 +               spin_unlock(&priv->page_lock);
3728 +               dev->stats.tx_dropped++;
3729 +               kfree_skb(skb);
3730 +
3731 +               return NETDEV_TX_OK;
3732 +       }
3733 +
3734 +       if (priv->soc->tso) {
3735 +               int t = tx_num;
3736 +
3737 +               priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = skb;
3738 +               while (--t)
3739 +                       priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = (struct sk_buff *) DMA_DUMMY_DESC;
3740 +       } else {
3741 +               priv->tx_skb[tx] = skb;
3742 +       }
3743 +       priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3744 +       wmb();
3745 +
3746 +       priv->tx_dma[tx].txd4 &= ~0x80;
3747 +       if (priv->soc->tx_dma)
3748 +               priv->soc->tx_dma(priv, tx, skb);
3749 +       else
3750 +               priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3751 +
3752 +       if (skb->ip_summed == CHECKSUM_PARTIAL)
3753 +               priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3754 +       else
3755 +               priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3756 +
3757 +       if (priv->soc->tso)
3758 +               fe_start_tso(skb, dev, nr_frags, tx);
3759 +
3760 +       if (priv->soc->tso && (skb_shinfo(skb)->gso_segs > 1)) {
3761 +               struct iphdr *iph = NULL;
3762 +               struct tcphdr *th = NULL;
3763 +               struct ipv6hdr *ip6h = NULL;
3764 +
3765 +               ip6h = (struct ipv6hdr *) skb_network_header(skb);
3766 +               iph = (struct iphdr *) skb_network_header(skb);
3767 +               if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
3768 +                       th = (struct tcphdr *)skb_transport_header(skb);
3769 +                       priv->tx_dma[tx].txd4 |= BIT(28);
3770 +                       th->check = htons(skb_shinfo(skb)->gso_size);
3771 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3772 +               } else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
3773 +                       th = (struct tcphdr *)skb_transport_header(skb);
3774 +                       priv->tx_dma[tx].txd4 |= BIT(28);
3775 +                       th->check = htons(skb_shinfo(skb)->gso_size);
3776 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3777 +               }
3778 +       }
3779 +
3780 +       for (i = 0; i < tx_num; i++)
3781 +               dma_cache_sync(NULL,  &priv->tx_dma[tx + i], sizeof(struct fe_tx_dma), DMA_TO_DEVICE);
3782 +
3783 +       dev->stats.tx_packets++;
3784 +       dev->stats.tx_bytes += skb->len;
3785 +
3786 +       wmb();
3787 +       fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3788 +       netdev_sent_queue(dev, skb->len);
3789 +
3790 +       spin_unlock(&priv->page_lock);
3791 +
3792 +       return NETDEV_TX_OK;
3793 +}
3794 +
3795 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3796 +{
3797 +       struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3798 +       int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3799 +       int complete = 0;
3800 +       int rx = 0;
3801 +
3802 +       while ((rx < budget) && !complete) {
3803 +               idx = (idx + 1) % NUM_DMA_DESC;
3804 +
3805 +               if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3806 +                       struct sk_buff *new_skb = fe_alloc_skb(priv);
3807 +
3808 +                       if (new_skb) {
3809 +                               int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3810 +                               dma_addr_t dma_addr;
3811 +
3812 +                               dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3813 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3814 +
3815 +                               skb_put(priv->rx_skb[idx], pktlen);
3816 +                               priv->rx_skb[idx]->dev = priv->netdev;
3817 +                               priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3818 +                               if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3819 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3820 +                               else
3821 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3822 +                               priv->netdev->stats.rx_packets++;
3823 +                               priv->netdev->stats.rx_bytes += pktlen;
3824 +
3825 +#ifdef CONFIG_INET_LRO
3826 +                               if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
3827 +                                       lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
3828 +                               else
3829 +#endif
3830 +                                       netif_receive_skb(priv->rx_skb[idx]);
3831 +
3832 +                               priv->rx_skb[idx] = new_skb;
3833 +
3834 +                               dma_addr = dma_map_single(&priv->netdev->dev,
3835 +                                                 new_skb->data,
3836 +                                                 MAX_RX_LENGTH,
3837 +                                                 DMA_FROM_DEVICE);
3838 +                               priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3839 +                               wmb();
3840 +                       } else {
3841 +                               priv->netdev->stats.rx_dropped++;
3842 +                       }
3843 +
3844 +                       if (priv->soc->rx_dma)
3845 +                               priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3846 +                       else
3847 +                               priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3848 +                       fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3849 +
3850 +                       rx++;
3851 +               } else {
3852 +                       complete = 1;
3853 +               }
3854 +       }
3855 +
3856 +#ifdef CONFIG_INET_LRO
3857 +       if (priv->soc->get_skb_header)
3858 +               lro_flush_all(&priv->lro_mgr);
3859 +#endif
3860 +       if (complete) {
3861 +               napi_complete(&priv->rx_napi);
3862 +               fe_int_enable(priv->soc->rx_dly_int);
3863 +       }
3864 +
3865 +       return rx;
3866 +}
3867 +
3868 +static void fe_tx_housekeeping(unsigned long ptr)
3869 +{
3870 +       struct net_device *dev = (struct net_device*)ptr;
3871 +       struct fe_priv *priv = netdev_priv(dev);
3872 +       unsigned int bytes_compl = 0;
3873 +       unsigned int pkts_compl = 0;
3874 +
3875 +       spin_lock(&priv->page_lock);
3876 +       while (1) {
3877 +               struct fe_tx_dma *txd;
3878 +
3879 +               txd = &priv->tx_dma[priv->tx_free_idx];
3880 +
3881 +               if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3882 +                       break;
3883 +
3884 +               if (priv->tx_skb[priv->tx_free_idx] != (struct sk_buff *) DMA_DUMMY_DESC) {
3885 +                       bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3886 +                       dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3887 +               }
3888 +               pkts_compl++;
3889 +               priv->tx_skb[priv->tx_free_idx] = NULL;
3890 +               priv->tx_free_idx++;
3891 +               if (priv->tx_free_idx >= NUM_DMA_DESC)
3892 +                       priv->tx_free_idx = 0;
3893 +       }
3894 +
3895 +       netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3896 +        spin_unlock(&priv->page_lock);
3897 +
3898 +       fe_int_enable(priv->soc->tx_dly_int);
3899 +}
3900 +
3901 +static void fe_tx_timeout(struct net_device *dev)
3902 +{
3903 +       struct fe_priv *priv = netdev_priv(dev);
3904 +
3905 +        tasklet_schedule(&priv->tx_tasklet);
3906 +       priv->netdev->stats.tx_errors++;
3907 +       netdev_err(dev, "transmit timed out, waking up the queue\n");
3908 +       netif_wake_queue(dev);
3909 +}
3910 +
3911 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3912 +{
3913 +       struct fe_priv *priv = netdev_priv(dev);
3914 +       unsigned int status;
3915 +       unsigned int mask;
3916 +
3917 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3918 +       mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3919 +
3920 +       if (!(status & mask))
3921 +               return IRQ_NONE;
3922 +
3923 +       if (status & priv->soc->rx_dly_int) {
3924 +               fe_int_disable(priv->soc->rx_dly_int);
3925 +               napi_schedule(&priv->rx_napi);
3926 +       }
3927 +
3928 +       if (status & priv->soc->tx_dly_int) {
3929 +               fe_int_disable(priv->soc->tx_dly_int);
3930 +               tasklet_schedule(&priv->tx_tasklet);
3931 +       }
3932 +
3933 +       fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3934 +
3935 +       return IRQ_HANDLED;
3936 +}
3937 +
3938 +static int fe_hw_init(struct net_device *dev)
3939 +{
3940 +       struct fe_priv *priv = netdev_priv(dev);
3941 +       int err;
3942 +
3943 +       err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3944 +                               dev_name(priv->device), dev);
3945 +       if (err)
3946 +               return err;
3947 +
3948 +       err = fe_alloc_rx(priv);
3949 +       if (!err)
3950 +               err = fe_alloc_tx(priv);
3951 +       if (err)
3952 +               return err;
3953 +
3954 +       if (priv->soc->set_mac)
3955 +               priv->soc->set_mac(priv, dev->dev_addr);
3956 +       else
3957 +               fe_hw_set_macaddr(priv, dev->dev_addr);
3958 +
3959 +       fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3960 +
3961 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3962 +
3963 +       tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3964 +
3965 +       if (priv->soc->fwd_config) {
3966 +               priv->soc->fwd_config(priv);
3967 +       } else {
3968 +               unsigned long sysclk = priv->sysclk;
3969 +
3970 +               if (!sysclk) {
3971 +                       netdev_err(dev, "unable to get clock\n");
3972 +                       return -EINVAL;
3973 +               }
3974 +
3975 +               sysclk /= FE_US_CYC_CNT_DIVISOR;
3976 +               sysclk <<= FE_US_CYC_CNT_SHIFT;
3977 +
3978 +               fe_w32((fe_r32(FE_FE_GLO_CFG) &
3979 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3980 +                       FE_FE_GLO_CFG);
3981 +
3982 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3983 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3984 +                       FE_GDMA1_FWD_CFG);
3985 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3986 +                       FE_CDMA_CSG_CFG);
3987 +               fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3988 +       }
3989 +
3990 +       fe_w32(1, FE_FE_RST_GL);
3991 +       fe_w32(0, FE_FE_RST_GL);
3992 +
3993 +       return 0;
3994 +}
3995 +
3996 +static int fe_open(struct net_device *dev)
3997 +{
3998 +       struct fe_priv *priv = netdev_priv(dev);
3999 +       unsigned long flags;
4000 +       u32 val;
4001 +
4002 +       spin_lock_irqsave(&priv->page_lock, flags);
4003 +       napi_enable(&priv->rx_napi);
4004 +
4005 +       val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
4006 +       val |= priv->soc->pdma_glo_cfg;
4007 +       fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
4008 +
4009 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4010 +
4011 +       if (priv->phy)
4012 +               priv->phy->start(priv);
4013 +
4014 +       if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
4015 +               netif_carrier_on(dev);
4016 +
4017 +       netif_start_queue(dev);
4018 +       fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4019 +
4020 +       return 0;
4021 +}
4022 +
4023 +static int fe_stop(struct net_device *dev)
4024 +{
4025 +       struct fe_priv *priv = netdev_priv(dev);
4026 +       unsigned long flags;
4027 +
4028 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4029 +
4030 +       netif_stop_queue(dev);
4031 +
4032 +       if (priv->phy)
4033 +               priv->phy->stop(priv);
4034 +
4035 +       spin_lock_irqsave(&priv->page_lock, flags);
4036 +       napi_disable(&priv->rx_napi);
4037 +
4038 +       fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4039 +                    ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
4040 +                    FE_REG_PDMA_GLO_CFG);
4041 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4042 +
4043 +       return 0;
4044 +}
4045 +
4046 +static int __init fe_init(struct net_device *dev)
4047 +{
4048 +       struct fe_priv *priv = netdev_priv(dev);
4049 +       struct device_node *port;
4050 +       int err;
4051 +
4052 +       BUG_ON(!priv->soc->reset_fe);
4053 +       priv->soc->reset_fe();
4054 +
4055 +       if (priv->soc->switch_init)
4056 +               priv->soc->switch_init(priv);
4057 +
4058 +       net_srandom(jiffies);
4059 +       memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
4060 +       of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
4061 +
4062 +       err = fe_mdio_init(priv);
4063 +       if (err)
4064 +               return err;
4065 +
4066 +       if (priv->phy) {
4067 +               err = priv->phy->connect(priv);
4068 +               if (err)
4069 +                       goto err_mdio_cleanup;
4070 +       }
4071 +
4072 +       if (priv->soc->port_init)
4073 +               for_each_child_of_node(priv->device->of_node, port)
4074 +                       if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
4075 +                               priv->soc->port_init(priv, port);
4076 +
4077 +       err = fe_hw_init(dev);
4078 +       if (err)
4079 +               goto err_phy_disconnect;
4080 +
4081 +       if (priv->soc->switch_config)
4082 +               priv->soc->switch_config(priv);
4083 +
4084 +       return 0;
4085 +
4086 +err_phy_disconnect:
4087 +       if (priv->phy)
4088 +               priv->phy->disconnect(priv);
4089 +err_mdio_cleanup:
4090 +       fe_mdio_cleanup(priv);
4091 +
4092 +       return err;
4093 +}
4094 +
4095 +static void fe_uninit(struct net_device *dev)
4096 +{
4097 +       struct fe_priv *priv = netdev_priv(dev);
4098 +
4099 +       tasklet_kill(&priv->tx_tasklet);
4100 +
4101 +       if (priv->phy)
4102 +               priv->phy->disconnect(priv);
4103 +       fe_mdio_cleanup(priv);
4104 +
4105 +       fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
4106 +       free_irq(dev->irq, dev);
4107 +
4108 +       fe_free_dma(priv);
4109 +}
4110 +
4111 +static const struct net_device_ops fe_netdev_ops = {
4112 +       .ndo_init               = fe_init,
4113 +       .ndo_uninit             = fe_uninit,
4114 +       .ndo_open               = fe_open,
4115 +       .ndo_stop               = fe_stop,
4116 +       .ndo_start_xmit         = fe_start_xmit,
4117 +       .ndo_tx_timeout         = fe_tx_timeout,
4118 +       .ndo_set_mac_address    = fe_set_mac_address,
4119 +       .ndo_change_mtu         = eth_change_mtu,
4120 +       .ndo_validate_addr      = eth_validate_addr,
4121 +};
4122 +
4123 +static int fe_probe(struct platform_device *pdev)
4124 +{
4125 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4126 +       const struct of_device_id *match;
4127 +       struct fe_soc_data *soc = NULL;
4128 +       struct net_device *netdev;
4129 +       struct fe_priv *priv;
4130 +       struct clk *sysclk;
4131 +       int err;
4132 +
4133 +       device_reset(&pdev->dev);
4134 +
4135 +       match = of_match_device(of_fe_match, &pdev->dev);
4136 +       soc = (struct fe_soc_data *) match->data;
4137 +
4138 +       if (soc->init_data)
4139 +               soc->init_data(soc);
4140 +       if (soc->reg_table)
4141 +               fe_reg_table = soc->reg_table;
4142 +
4143 +       fe_base = devm_request_and_ioremap(&pdev->dev, res);
4144 +       if (!fe_base)
4145 +               return -ENOMEM;
4146 +
4147 +       netdev = alloc_etherdev(sizeof(struct fe_priv));
4148 +       if (!netdev) {
4149 +               dev_err(&pdev->dev, "alloc_etherdev failed\n");
4150 +               return -ENOMEM;
4151 +       }
4152 +
4153 +       strcpy(netdev->name, "eth%d");
4154 +       netdev->netdev_ops = &fe_netdev_ops;
4155 +       netdev->base_addr = (unsigned long) fe_base;
4156 +       netdev->watchdog_timeo = TX_TIMEOUT;
4157 +       netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
4158 +
4159 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
4160 +               netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4161 +
4162 +       if (soc->tso) {
4163 +               dev_info(&pdev->dev, "Enabling TSO\n");
4164 +               netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
4165 +       }
4166 +       netdev->hw_features = netdev->features;
4167 +
4168 +       netdev->irq = platform_get_irq(pdev, 0);
4169 +       if (netdev->irq < 0) {
4170 +               dev_err(&pdev->dev, "no IRQ resource found\n");
4171 +               kfree(netdev);
4172 +               return -ENXIO;
4173 +       }
4174 +
4175 +       priv = netdev_priv(netdev);
4176 +       memset(priv, 0, sizeof(struct fe_priv));
4177 +       spin_lock_init(&priv->page_lock);
4178 +
4179 +       sysclk = devm_clk_get(&pdev->dev, NULL);
4180 +       if (!IS_ERR(sysclk))
4181 +               priv->sysclk = clk_get_rate(sysclk);
4182 +
4183 +       priv->netdev = netdev;
4184 +       priv->device = &pdev->dev;
4185 +       priv->soc = soc;
4186 +
4187 +       err = register_netdev(netdev);
4188 +       if (err) {
4189 +               dev_err(&pdev->dev, "error bringing up device\n");
4190 +               kfree(netdev);
4191 +               return err;
4192 +       }
4193 +       netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
4194 +
4195 +#ifdef CONFIG_INET_LRO
4196 +       if (priv->soc->get_skb_header) {
4197 +               priv->lro_mgr.dev = netdev;
4198 +               memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
4199 +               priv->lro_mgr.features = LRO_F_NAPI;
4200 +               priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
4201 +               priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
4202 +               priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
4203 +               priv->lro_mgr.max_aggr = 64;
4204 +               priv->lro_mgr.frag_align_pad = 0;
4205 +               priv->lro_mgr.lro_arr = priv->lro_arr;
4206 +               priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
4207 +       }
4208 +#endif
4209 +
4210 +       platform_set_drvdata(pdev, netdev);
4211 +
4212 +       netdev_info(netdev, "done loading\n");
4213 +
4214 +       return 0;
4215 +}
4216 +
4217 +static int fe_remove(struct platform_device *pdev)
4218 +{
4219 +        struct net_device *dev = platform_get_drvdata(pdev);
4220 +       struct fe_priv *priv = netdev_priv(dev);
4221 +
4222 +       netif_stop_queue(dev);
4223 +       netif_napi_del(&priv->rx_napi);
4224 +
4225 +       unregister_netdev(dev);
4226 +       free_netdev(dev);
4227 +
4228 +       return 0;
4229 +}
4230 +
4231 +static struct platform_driver fe_driver = {
4232 +       .probe = fe_probe,
4233 +       .remove = fe_remove,
4234 +       .driver = {
4235 +               .name = "ralink_soc_eth",
4236 +               .owner = THIS_MODULE,
4237 +               .of_match_table = of_fe_match,
4238 +       },
4239 +};
4240 +
4241 +static int __init init_rtfe(void)
4242 +{
4243 +       int ret;
4244 +
4245 +       ret = rtesw_init();
4246 +       if (ret)
4247 +               return ret;
4248 +
4249 +       ret = platform_driver_register(&fe_driver);
4250 +       if (ret)
4251 +               rtesw_exit();
4252 +
4253 +       return ret;
4254 +}
4255 +
4256 +static void __exit exit_rtfe(void)
4257 +{
4258 +       platform_driver_unregister(&fe_driver);
4259 +       rtesw_exit();
4260 +}
4261 +
4262 +module_init(init_rtfe);
4263 +module_exit(exit_rtfe);
4264 +
4265 +MODULE_LICENSE("GPL");
4266 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4267 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4268 --- /dev/null
4269 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4270 @@ -0,0 +1,384 @@
4271 +/*
4272 + *   This program is free software; you can redistribute it and/or modify
4273 + *   it under the terms of the GNU General Public License as published by
4274 + *   the Free Software Foundation; version 2 of the License
4275 + *
4276 + *   This program is distributed in the hope that it will be useful,
4277 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4278 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4279 + *   GNU General Public License for more details.
4280 + *
4281 + *   You should have received a copy of the GNU General Public License
4282 + *   along with this program; if not, write to the Free Software
4283 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4284 + *
4285 + *   based on Ralink SDK3.3
4286 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4287 + */
4288 +
4289 +#ifndef FE_ETH_H
4290 +#define FE_ETH_H
4291 +
4292 +#include <linux/mii.h>
4293 +#include <linux/interrupt.h>
4294 +#include <linux/netdevice.h>
4295 +#include <linux/dma-mapping.h>
4296 +#include <linux/phy.h>
4297 +#include <linux/inet_lro.h>
4298 +
4299 +
4300 +enum fe_reg {
4301 +       FE_REG_PDMA_GLO_CFG = 0,
4302 +       FE_REG_PDMA_RST_CFG,
4303 +       FE_REG_DLY_INT_CFG,
4304 +       FE_REG_TX_BASE_PTR0,
4305 +       FE_REG_TX_MAX_CNT0,
4306 +       FE_REG_TX_CTX_IDX0,
4307 +       FE_REG_RX_BASE_PTR0,
4308 +       FE_REG_RX_MAX_CNT0,
4309 +       FE_REG_RX_CALC_IDX0,
4310 +       FE_REG_FE_INT_ENABLE,
4311 +       FE_REG_FE_INT_STATUS,
4312 +       FE_REG_FE_DMA_VID_BASE,
4313 +       FE_REG_COUNT
4314 +};
4315 +
4316 +#define NUM_DMA_DESC           0x100
4317 +
4318 +#define FE_DELAY_EN_INT                0x80
4319 +#define FE_DELAY_MAX_INT       0x04
4320 +#define FE_DELAY_MAX_TOUT      0x04
4321 +#define FE_DELAY_CHAN          (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4322 +#define FE_DELAY_INIT          ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4323 +#define FE_PSE_FQFC_CFG_INIT   0x80504000
4324 +
4325 +/* interrupt bits */
4326 +#define FE_CNT_PPE_AF          BIT(31)
4327 +#define FE_CNT_GDM_AF          BIT(29)
4328 +#define FE_PSE_P2_FC           BIT(26)
4329 +#define FE_PSE_BUF_DROP                BIT(24)
4330 +#define FE_GDM_OTHER_DROP      BIT(23)
4331 +#define FE_PSE_P1_FC           BIT(22)
4332 +#define FE_PSE_P0_FC           BIT(21)
4333 +#define FE_PSE_FQ_EMPTY                BIT(20)
4334 +#define FE_GE1_STA_CHG         BIT(18)
4335 +#define FE_TX_COHERENT         BIT(17)
4336 +#define FE_RX_COHERENT         BIT(16)
4337 +#define FE_TX_DONE_INT3                BIT(11)
4338 +#define FE_TX_DONE_INT2                BIT(10)
4339 +#define FE_TX_DONE_INT1                BIT(9)
4340 +#define FE_TX_DONE_INT0                BIT(8)
4341 +#define FE_RX_DONE_INT0                BIT(2)
4342 +#define FE_TX_DLY_INT          BIT(1)
4343 +#define FE_RX_DLY_INT          BIT(0)
4344 +
4345 +#define RT5350_RX_DLY_INT      BIT(30)
4346 +#define RT5350_TX_DLY_INT      BIT(28)
4347 +
4348 +/* registers */
4349 +#define FE_FE_OFFSET           0x0000
4350 +#define FE_GDMA_OFFSET         0x0020
4351 +#define FE_PSE_OFFSET          0x0040
4352 +#define FE_GDMA2_OFFSET                0x0060
4353 +#define FE_CDMA_OFFSET         0x0080
4354 +#define FE_DMA_VID0            0x00a8
4355 +#define FE_PDMA_OFFSET         0x0100
4356 +#define FE_PPE_OFFSET          0x0200
4357 +#define FE_CMTABLE_OFFSET      0x0400
4358 +#define FE_POLICYTABLE_OFFSET  0x1000
4359 +
4360 +#define RT5350_PDMA_OFFSET     0x0800
4361 +#define RT5350_SDM_OFFSET      0x0c00
4362 +
4363 +#define FE_MDIO_ACCESS         (FE_FE_OFFSET + 0x00)
4364 +#define FE_MDIO_CFG            (FE_FE_OFFSET + 0x04)
4365 +#define FE_FE_GLO_CFG          (FE_FE_OFFSET + 0x08)
4366 +#define FE_FE_RST_GL           (FE_FE_OFFSET + 0x0C)
4367 +#define FE_FE_INT_STATUS       (FE_FE_OFFSET + 0x10)
4368 +#define FE_FE_INT_ENABLE       (FE_FE_OFFSET + 0x14)
4369 +#define FE_MDIO_CFG2           (FE_FE_OFFSET + 0x18)
4370 +#define FE_FOC_TS_T            (FE_FE_OFFSET + 0x1C)
4371 +
4372 +#define        FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
4373 +#define FE_GDMA1_SCH_CFG       (FE_GDMA_OFFSET + 0x04)
4374 +#define FE_GDMA1_SHPR_CFG      (FE_GDMA_OFFSET + 0x08)
4375 +#define FE_GDMA1_MAC_ADRL      (FE_GDMA_OFFSET + 0x0C)
4376 +#define FE_GDMA1_MAC_ADRH      (FE_GDMA_OFFSET + 0x10)
4377 +
4378 +#define        FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
4379 +#define FE_GDMA2_SCH_CFG       (FE_GDMA2_OFFSET + 0x04)
4380 +#define FE_GDMA2_SHPR_CFG      (FE_GDMA2_OFFSET + 0x08)
4381 +#define FE_GDMA2_MAC_ADRL      (FE_GDMA2_OFFSET + 0x0C)
4382 +#define FE_GDMA2_MAC_ADRH      (FE_GDMA2_OFFSET + 0x10)
4383 +
4384 +#define FE_PSE_FQ_CFG          (FE_PSE_OFFSET + 0x00)
4385 +#define FE_CDMA_FC_CFG         (FE_PSE_OFFSET + 0x04)
4386 +#define FE_GDMA1_FC_CFG                (FE_PSE_OFFSET + 0x08)
4387 +#define FE_GDMA2_FC_CFG                (FE_PSE_OFFSET + 0x0C)
4388 +
4389 +#define FE_CDMA_CSG_CFG                (FE_CDMA_OFFSET + 0x00)
4390 +#define FE_CDMA_SCH_CFG                (FE_CDMA_OFFSET + 0x04)
4391 +
4392 +#define MT7620A_GDMA_OFFSET            0x0600
4393 +#define        MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
4394 +#define MT7620A_FE_GDMA1_SCH_CFG       (MT7620A_GDMA_OFFSET + 0x04)
4395 +#define MT7620A_FE_GDMA1_SHPR_CFG      (MT7620A_GDMA_OFFSET + 0x08)
4396 +#define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
4397 +#define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
4398 +
4399 +#define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
4400 +#define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
4401 +#define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)
4402 +#define RT5350_TX_DTX_IDX0     (RT5350_PDMA_OFFSET + 0x0C)
4403 +#define RT5350_TX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x10)
4404 +#define RT5350_TX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x14)
4405 +#define RT5350_TX_CTX_IDX1     (RT5350_PDMA_OFFSET + 0x18)
4406 +#define RT5350_TX_DTX_IDX1     (RT5350_PDMA_OFFSET + 0x1C)
4407 +#define RT5350_TX_BASE_PTR2    (RT5350_PDMA_OFFSET + 0x20)
4408 +#define RT5350_TX_MAX_CNT2     (RT5350_PDMA_OFFSET + 0x24)
4409 +#define RT5350_TX_CTX_IDX2     (RT5350_PDMA_OFFSET + 0x28)
4410 +#define RT5350_TX_DTX_IDX2     (RT5350_PDMA_OFFSET + 0x2C)
4411 +#define RT5350_TX_BASE_PTR3    (RT5350_PDMA_OFFSET + 0x30)
4412 +#define RT5350_TX_MAX_CNT3     (RT5350_PDMA_OFFSET + 0x34)
4413 +#define RT5350_TX_CTX_IDX3     (RT5350_PDMA_OFFSET + 0x38)
4414 +#define RT5350_TX_DTX_IDX3     (RT5350_PDMA_OFFSET + 0x3C)
4415 +#define RT5350_RX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x100)
4416 +#define RT5350_RX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x104)
4417 +#define RT5350_RX_CALC_IDX0    (RT5350_PDMA_OFFSET + 0x108)
4418 +#define RT5350_RX_DRX_IDX0     (RT5350_PDMA_OFFSET + 0x10C)
4419 +#define RT5350_RX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x110)
4420 +#define RT5350_RX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x114)
4421 +#define RT5350_RX_CALC_IDX1    (RT5350_PDMA_OFFSET + 0x118)
4422 +#define RT5350_RX_DRX_IDX1     (RT5350_PDMA_OFFSET + 0x11C)
4423 +#define RT5350_PDMA_GLO_CFG    (RT5350_PDMA_OFFSET + 0x204)
4424 +#define RT5350_PDMA_RST_CFG    (RT5350_PDMA_OFFSET + 0x208)
4425 +#define RT5350_DLY_INT_CFG     (RT5350_PDMA_OFFSET + 0x20c)
4426 +#define RT5350_FE_INT_STATUS   (RT5350_PDMA_OFFSET + 0x220)
4427 +#define RT5350_FE_INT_ENABLE   (RT5350_PDMA_OFFSET + 0x228)
4428 +#define RT5350_PDMA_SCH_CFG    (RT5350_PDMA_OFFSET + 0x280)
4429 +
4430 +#define FE_PDMA_GLO_CFG                (FE_PDMA_OFFSET + 0x00)
4431 +#define FE_PDMA_RST_CFG                (FE_PDMA_OFFSET + 0x04)
4432 +#define FE_PDMA_SCH_CFG                (FE_PDMA_OFFSET + 0x08)
4433 +#define FE_DLY_INT_CFG         (FE_PDMA_OFFSET + 0x0C)
4434 +#define FE_TX_BASE_PTR0                (FE_PDMA_OFFSET + 0x10)
4435 +#define FE_TX_MAX_CNT0         (FE_PDMA_OFFSET + 0x14)
4436 +#define FE_TX_CTX_IDX0         (FE_PDMA_OFFSET + 0x18)
4437 +#define FE_TX_DTX_IDX0         (FE_PDMA_OFFSET + 0x1C)
4438 +#define FE_TX_BASE_PTR1                (FE_PDMA_OFFSET + 0x20)
4439 +#define FE_TX_MAX_CNT1         (FE_PDMA_OFFSET + 0x24)
4440 +#define FE_TX_CTX_IDX1         (FE_PDMA_OFFSET + 0x28)
4441 +#define FE_TX_DTX_IDX1         (FE_PDMA_OFFSET + 0x2C)
4442 +#define FE_RX_BASE_PTR0                (FE_PDMA_OFFSET + 0x30)
4443 +#define FE_RX_MAX_CNT0         (FE_PDMA_OFFSET + 0x34)
4444 +#define FE_RX_CALC_IDX0                (FE_PDMA_OFFSET + 0x38)
4445 +#define FE_RX_DRX_IDX0         (FE_PDMA_OFFSET + 0x3C)
4446 +#define FE_TX_BASE_PTR2                (FE_PDMA_OFFSET + 0x40)
4447 +#define FE_TX_MAX_CNT2         (FE_PDMA_OFFSET + 0x44)
4448 +#define FE_TX_CTX_IDX2         (FE_PDMA_OFFSET + 0x48)
4449 +#define FE_TX_DTX_IDX2         (FE_PDMA_OFFSET + 0x4C)
4450 +#define FE_TX_BASE_PTR3                (FE_PDMA_OFFSET + 0x50)
4451 +#define FE_TX_MAX_CNT3         (FE_PDMA_OFFSET + 0x54)
4452 +#define FE_TX_CTX_IDX3         (FE_PDMA_OFFSET + 0x58)
4453 +#define FE_TX_DTX_IDX3         (FE_PDMA_OFFSET + 0x5C)
4454 +#define FE_RX_BASE_PTR1                (FE_PDMA_OFFSET + 0x60)
4455 +#define FE_RX_MAX_CNT1         (FE_PDMA_OFFSET + 0x64)
4456 +#define FE_RX_CALC_IDX1                (FE_PDMA_OFFSET + 0x68)
4457 +#define FE_RX_DRX_IDX1         (FE_PDMA_OFFSET + 0x6C)
4458 +
4459 +#define RT5350_SDM_CFG         (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
4460 +#define RT5350_SDM_RRING       (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
4461 +#define RT5350_SDM_TRING       (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
4462 +#define RT5350_SDM_MAC_ADRL    (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
4463 +#define RT5350_SDM_MAC_ADRH    (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
4464 +#define RT5350_SDM_TPCNT       (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4465 +#define RT5350_SDM_TBCNT       (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4466 +#define RT5350_SDM_RPCNT       (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4467 +#define RT5350_SDM_RBCNT       (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4468 +#define RT5350_SDM_CS_ERR      (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4469 +
4470 +#define RT5350_SDM_ICS_EN      BIT(16)
4471 +#define RT5350_SDM_TCS_EN      BIT(17)
4472 +#define RT5350_SDM_UCS_EN      BIT(18)
4473 +
4474 +
4475 +/* MDIO_CFG register bits */
4476 +#define FE_MDIO_CFG_AUTO_POLL_EN       BIT(29)
4477 +#define FE_MDIO_CFG_GP1_BP_EN          BIT(16)
4478 +#define FE_MDIO_CFG_GP1_FRC_EN         BIT(15)
4479 +#define FE_MDIO_CFG_GP1_SPEED_10       (0 << 13)
4480 +#define FE_MDIO_CFG_GP1_SPEED_100      (1 << 13)
4481 +#define FE_MDIO_CFG_GP1_SPEED_1000     (2 << 13)
4482 +#define FE_MDIO_CFG_GP1_DUPLEX         BIT(12)
4483 +#define FE_MDIO_CFG_GP1_FC_TX          BIT(11)
4484 +#define FE_MDIO_CFG_GP1_FC_RX          BIT(10)
4485 +#define FE_MDIO_CFG_GP1_LNK_DWN                BIT(9)
4486 +#define FE_MDIO_CFG_GP1_AN_FAIL                BIT(8)
4487 +#define FE_MDIO_CFG_MDC_CLK_DIV_1      (0 << 6)
4488 +#define FE_MDIO_CFG_MDC_CLK_DIV_2      (1 << 6)
4489 +#define FE_MDIO_CFG_MDC_CLK_DIV_4      (2 << 6)
4490 +#define FE_MDIO_CFG_MDC_CLK_DIV_8      (3 << 6)
4491 +#define FE_MDIO_CFG_TURBO_MII_FREQ     BIT(5)
4492 +#define FE_MDIO_CFG_TURBO_MII_MODE     BIT(4)
4493 +#define FE_MDIO_CFG_RX_CLK_SKEW_0      (0 << 2)
4494 +#define FE_MDIO_CFG_RX_CLK_SKEW_200    (1 << 2)
4495 +#define FE_MDIO_CFG_RX_CLK_SKEW_400    (2 << 2)
4496 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV    (3 << 2)
4497 +#define FE_MDIO_CFG_TX_CLK_SKEW_0      0
4498 +#define FE_MDIO_CFG_TX_CLK_SKEW_200    1
4499 +#define FE_MDIO_CFG_TX_CLK_SKEW_400    2
4500 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV    3
4501 +
4502 +/* uni-cast port */
4503 +#define FE_GDM1_ICS_EN         BIT(22)
4504 +#define FE_GDM1_TCS_EN         BIT(21)
4505 +#define FE_GDM1_UCS_EN         BIT(20)
4506 +#define FE_GDM1_JMB_EN         BIT(19)
4507 +#define FE_GDM1_STRPCRC                BIT(16)
4508 +#define FE_GDM1_UFRC_P_CPU     (0 << 12)
4509 +#define FE_GDM1_UFRC_P_GDMA1   (1 << 12)
4510 +#define FE_GDM1_UFRC_P_PPE     (6 << 12)
4511 +
4512 +/* checksums */
4513 +#define FE_ICS_GEN_EN          BIT(2)
4514 +#define FE_UCS_GEN_EN          BIT(1)
4515 +#define FE_TCS_GEN_EN          BIT(0)
4516 +
4517 +/* dma ring */
4518 +#define FE_PST_DRX_IDX0                BIT(16)
4519 +#define FE_PST_DTX_IDX3                BIT(3)
4520 +#define FE_PST_DTX_IDX2                BIT(2)
4521 +#define FE_PST_DTX_IDX1                BIT(1)
4522 +#define FE_PST_DTX_IDX0                BIT(0)
4523 +
4524 +#define FE_TX_WB_DDONE         BIT(6)
4525 +#define FE_RX_DMA_BUSY         BIT(3)
4526 +#define FE_TX_DMA_BUSY         BIT(1)
4527 +#define FE_RX_DMA_EN           BIT(2)
4528 +#define FE_TX_DMA_EN           BIT(0)
4529 +
4530 +#define FE_PDMA_SIZE_4DWORDS   (0 << 4)
4531 +#define FE_PDMA_SIZE_8DWORDS   (1 << 4)
4532 +#define FE_PDMA_SIZE_16DWORDS  (2 << 4)
4533 +
4534 +#define FE_US_CYC_CNT_MASK     0xff
4535 +#define FE_US_CYC_CNT_SHIFT    0x8
4536 +#define FE_US_CYC_CNT_DIVISOR  1000000
4537 +
4538 +#define RX_DMA_PLEN0(_x)       (((_x) >> 16) & 0x3fff)
4539 +#define RX_DMA_LSO             BIT(30)
4540 +#define RX_DMA_DONE            BIT(31)
4541 +#define RX_DMA_L4VALID         BIT(30)
4542 +
4543 +struct fe_rx_dma {
4544 +       unsigned int rxd1;
4545 +       unsigned int rxd2;
4546 +       unsigned int rxd3;
4547 +       unsigned int rxd4;
4548 +} __packed __aligned(4);
4549 +
4550 +#define TX_DMA_PLEN0_MASK      ((0x3fff) << 16)
4551 +#define TX_DMA_PLEN0(_x)       (((_x) & 0x3fff) << 16)
4552 +#define TX_DMA_PLEN1(_x)       ((_x) & 0x3fff)
4553 +#define TX_DMA_LS1             BIT(14)
4554 +#define TX_DMA_LSO             BIT(30)
4555 +#define TX_DMA_DONE            BIT(31)
4556 +#define TX_DMA_QN(_x)          ((_x) << 16)
4557 +#define TX_DMA_PN(_x)          ((_x) << 24)
4558 +#define TX_DMA_QN_MASK         TX_DMA_QN(0x7)
4559 +#define TX_DMA_PN_MASK         TX_DMA_PN(0x7)
4560 +#define TX_DMA_CHKSUM          (0x7 << 29)
4561 +
4562 +struct fe_tx_dma {
4563 +       unsigned int txd1;
4564 +       unsigned int txd2;
4565 +       unsigned int txd3;
4566 +       unsigned int txd4;
4567 +} __packed __aligned(4);
4568 +
4569 +struct fe_priv;
4570 +
4571 +struct fe_phy {
4572 +       struct phy_device       *phy[8];
4573 +       struct device_node      *phy_node[8];
4574 +       const __be32            *phy_fixed[8];
4575 +       int                     duplex[8];
4576 +       int                     speed[8];
4577 +       int                     tx_fc[8];
4578 +       int                     rx_fc[8];
4579 +       spinlock_t              lock;
4580 +
4581 +       int (*connect)(struct fe_priv *priv);
4582 +       void (*disconnect)(struct fe_priv *priv);
4583 +       void (*start)(struct fe_priv *priv);
4584 +       void (*stop)(struct fe_priv *priv);
4585 +};
4586 +
4587 +struct fe_soc_data
4588 +{
4589 +       unsigned char mac[6];
4590 +       const u32 *reg_table;
4591 +
4592 +       void (*init_data)(struct fe_soc_data *data);
4593 +       void (*reset_fe)(void);
4594 +       void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4595 +       void (*fwd_config)(struct fe_priv *priv);
4596 +       void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
4597 +       void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4598 +       int (*switch_init)(struct fe_priv *priv);
4599 +       int (*switch_config)(struct fe_priv *priv);
4600 +       void (*port_init)(struct fe_priv *priv, struct device_node *port);
4601 +       int (*has_carrier)(struct fe_priv *priv);
4602 +       int (*mdio_init)(struct fe_priv *priv);
4603 +       void (*mdio_cleanup)(struct fe_priv *priv);
4604 +       int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4605 +       int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4606 +       void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4607 +       int (*get_skb_header)(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv);
4608 +
4609 +       void *swpriv;
4610 +       u32 pdma_glo_cfg;
4611 +       u32 rx_dly_int;
4612 +       u32 tx_dly_int;
4613 +       u32 checksum_bit;
4614 +       u32 tso;
4615 +
4616 +       int min_pkt_len;
4617 +};
4618 +
4619 +struct fe_priv
4620 +{
4621 +       spinlock_t                      page_lock;
4622 +
4623 +       struct fe_soc_data              *soc;
4624 +       struct net_device               *netdev;
4625 +       struct device                   *device;
4626 +       unsigned long                   sysclk;
4627 +
4628 +       struct fe_rx_dma                *rx_dma;
4629 +        struct napi_struct             rx_napi;
4630 +       struct sk_buff                  *rx_skb[NUM_DMA_DESC];
4631 +       dma_addr_t                      rx_phys;
4632 +
4633 +       struct fe_tx_dma                *tx_dma;
4634 +       struct tasklet_struct           tx_tasklet;
4635 +       struct sk_buff                  *tx_skb[NUM_DMA_DESC];
4636 +       dma_addr_t                      tx_phys;
4637 +       unsigned int                    tx_free_idx;
4638 +
4639 +       struct fe_phy                   *phy;
4640 +       struct mii_bus                  *mii_bus;
4641 +       int                             mii_irq[PHY_MAX_ADDR];
4642 +
4643 +       int                             link[8];
4644 +
4645 +       struct net_lro_mgr              lro_mgr;
4646 +       struct net_lro_desc             lro_arr[8];
4647 +};
4648 +
4649 +extern const struct of_device_id of_fe_match[];
4650 +
4651 +void fe_w32(u32 val, unsigned reg);
4652 +u32 fe_r32(unsigned reg);
4653 +
4654 +#endif /* FE_ETH_H */
4655 --- /dev/null
4656 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
4657 @@ -0,0 +1,172 @@
4658 +/*
4659 + *   This program is free software; you can redistribute it and/or modify
4660 + *   it under the terms of the GNU General Public License as published by
4661 + *   the Free Software Foundation; version 2 of the License
4662 + *
4663 + *   This program is distributed in the hope that it will be useful,
4664 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4665 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4666 + *   GNU General Public License for more details.
4667 + *
4668 + *   You should have received a copy of the GNU General Public License
4669 + *   along with this program; if not, write to the Free Software
4670 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4671 + *
4672 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4673 + */
4674 +
4675 +#include <linux/module.h>
4676 +#include <linux/platform_device.h>
4677 +#include <linux/if_vlan.h>
4678 +
4679 +#include <asm/mach-ralink/ralink_regs.h>
4680 +
4681 +#include <mt7620.h>
4682 +#include "ralink_soc_eth.h"
4683 +#include "gsw_mt7620a.h"
4684 +
4685 +#define MT7620A_CDMA_CSG_CFG   0x400
4686 +#define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
4687 +#define MT7620A_DMA_2B_OFFSET  BIT(31)
4688 +#define MT7620A_RESET_FE       BIT(21)
4689 +#define MT7620A_RESET_ESW      BIT(23)
4690 +#define MT7620_L4_VALID                BIT(23)
4691 +
4692 +#define SYSC_REG_RESET_CTRL     0x34
4693 +#define MAX_RX_LENGTH           1536
4694 +
4695 +#define CDMA_ICS_EN            BIT(2)
4696 +#define CDMA_UCS_EN            BIT(1)
4697 +#define CDMA_TCS_EN            BIT(0)
4698 +
4699 +#define GDMA_ICS_EN            BIT(22)
4700 +#define GDMA_TCS_EN            BIT(21)
4701 +#define GDMA_UCS_EN            BIT(20)
4702 +
4703 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4704 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4705 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4706 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4707 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4708 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4709 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4710 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4711 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4712 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4713 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4714 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4715 +       [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4716 +};
4717 +
4718 +static void mt7620_fe_reset(void)
4719 +{
4720 +       rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4721 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4722 +}
4723 +
4724 +static void mt7620_fwd_config(struct fe_priv *priv)
4725 +{
4726 +       int i;
4727 +
4728 +       /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
4729 +       for (i = 0; i < 16; i += 2)
4730 +               fe_w32(((i + 1) << 16) + i, MT7620_DMA_VID + (i * 2));
4731 +
4732 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4733 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4734 +       fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4735 +}
4736 +
4737 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
4738 +{
4739 +       unsigned int nr_frags = 0;
4740 +       unsigned int len = 0;
4741 +
4742 +       if (skb) {
4743 +               nr_frags = skb_shinfo(skb)->nr_frags;
4744 +               len = skb->len - skb->data_len;
4745 +       }
4746 +
4747 +       if (!skb)
4748 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4749 +       else if (!nr_frags)
4750 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4751 +       else
4752 +               priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(len);
4753 +
4754 +       if(skb && vlan_tx_tag_present(skb))
4755 +               priv->tx_dma[idx].txd4 = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
4756 +       else
4757 +               priv->tx_dma[idx].txd4 = 0;
4758 +}
4759 +
4760 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4761 +{
4762 +       priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4763 +}
4764 +
4765 +#ifdef CONFIG_INET_LRO
4766 +static int
4767 +mt7620_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
4768 +                       u64 *hdr_flags, void *_priv)
4769 +{
4770 +       struct iphdr *iph = NULL;
4771 +       int vhdr_len = 0;
4772 +
4773 +       /*
4774 +        * Make sure that this packet is Ethernet II, is not VLAN
4775 +        * tagged, is IPv4, has a valid IP header, and is TCP.
4776 +        */
4777 +       if (skb->protocol == 0x0081)
4778 +               vhdr_len = VLAN_HLEN;
4779 +
4780 +       iph = (struct iphdr *)(skb->data + vhdr_len);
4781 +       if(iph->protocol != IPPROTO_TCP)
4782 +               return -1;
4783 +
4784 +       *iphdr = iph;
4785 +       *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
4786 +       *hdr_flags = LRO_IPV4 | LRO_TCP;
4787 +
4788 +       return 0;
4789 +}
4790 +#endif
4791 +
4792 +static void mt7620_init_data(struct fe_soc_data *data)
4793 +{
4794 +       if (mt7620_get_eco() >= 5)
4795 +               data->tso = 1;
4796 +}
4797 +
4798 +static struct fe_soc_data mt7620_data = {
4799 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4800 +       .init_data = mt7620_init_data,
4801 +       .reset_fe = mt7620_fe_reset,
4802 +       .set_mac = mt7620_set_mac,
4803 +       .fwd_config = mt7620_fwd_config,
4804 +       .tx_dma = mt7620_tx_dma,
4805 +       .rx_dma = mt7620_rx_dma,
4806 +       .switch_init = mt7620_gsw_probe,
4807 +       .switch_config = mt7620_gsw_config,
4808 +       .port_init = mt7620_port_init,
4809 +       .min_pkt_len = 0,
4810 +       .reg_table = rt5350_reg_table,
4811 +       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4812 +       .rx_dly_int = RT5350_RX_DLY_INT,
4813 +       .tx_dly_int = RT5350_TX_DLY_INT,
4814 +       .checksum_bit = MT7620_L4_VALID,
4815 +       .has_carrier = mt7620a_has_carrier,
4816 +       .mdio_read = mt7620_mdio_read,
4817 +       .mdio_write = mt7620_mdio_write,
4818 +       .mdio_adjust_link = mt7620_mdio_link_adjust,
4819 +#ifdef CONFIG_INET_LRO
4820 +       .get_skb_header = mt7620_get_skb_header,
4821 +#endif
4822 +};
4823 +
4824 +const struct of_device_id of_fe_match[] = {
4825 +       { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4826 +       {},
4827 +};
4828 +
4829 +MODULE_DEVICE_TABLE(of, of_fe_match);
4830 --- /dev/null
4831 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4832 @@ -0,0 +1,52 @@
4833 +/*
4834 + *   This program is free software; you can redistribute it and/or modify
4835 + *   it under the terms of the GNU General Public License as published by
4836 + *   the Free Software Foundation; version 2 of the License
4837 + *
4838 + *   This program is distributed in the hope that it will be useful,
4839 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4840 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4841 + *   GNU General Public License for more details.
4842 + *
4843 + *   You should have received a copy of the GNU General Public License
4844 + *   along with this program; if not, write to the Free Software
4845 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4846 + *
4847 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4848 + */
4849 +
4850 +#include <linux/module.h>
4851 +
4852 +#include <asm/mach-ralink/ralink_regs.h>
4853 +
4854 +#include "ralink_soc_eth.h"
4855 +#include "mdio_rt2880.h"
4856 +
4857 +#define SYSC_REG_RESET_CTRL            0x034
4858 +#define RT2880_RESET_FE                        BIT(18)
4859 +
4860 +void rt2880_fe_reset(void)
4861 +{
4862 +       rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4863 +}
4864 +
4865 +struct fe_soc_data rt2880_data = {
4866 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4867 +       .reset_fe = rt2880_fe_reset,
4868 +       .min_pkt_len = 64,
4869 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4870 +       .checksum_bit = RX_DMA_L4VALID,
4871 +       .rx_dly_int = FE_RX_DLY_INT,
4872 +       .tx_dly_int = FE_TX_DLY_INT,
4873 +       .mdio_read = rt2880_mdio_read,
4874 +       .mdio_write = rt2880_mdio_write,
4875 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
4876 +       .port_init = rt2880_port_init,
4877 +};
4878 +
4879 +const struct of_device_id of_fe_match[] = {
4880 +       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4881 +       {},
4882 +};
4883 +
4884 +MODULE_DEVICE_TABLE(of, of_fe_match);
4885 --- /dev/null
4886 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4887 @@ -0,0 +1,113 @@
4888 +/*
4889 + *   This program is free software; you can redistribute it and/or modify
4890 + *   it under the terms of the GNU General Public License as published by
4891 + *   the Free Software Foundation; version 2 of the License
4892 + *
4893 + *   This program is distributed in the hope that it will be useful,
4894 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4895 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4896 + *   GNU General Public License for more details.
4897 + *
4898 + *   You should have received a copy of the GNU General Public License
4899 + *   along with this program; if not, write to the Free Software
4900 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4901 + *
4902 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4903 + */
4904 +
4905 +#include <linux/module.h>
4906 +
4907 +#include <asm/mach-ralink/ralink_regs.h>
4908 +
4909 +#include "ralink_soc_eth.h"
4910 +
4911 +#define RT305X_RESET_FE         BIT(21)
4912 +#define RT305X_RESET_ESW        BIT(23)
4913 +#define SYSC_REG_RESET_CTRL     0x034
4914 +
4915 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4916 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4917 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4918 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4919 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4920 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4921 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4922 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4923 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4924 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4925 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4926 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4927 +       [FE_REG_FE_DMA_VID_BASE] = 0,
4928 +};
4929 +
4930 +static void rt305x_fe_reset(void)
4931 +{
4932 +       rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4933 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4934 +}
4935 +
4936 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4937 +{
4938 +       unsigned long flags;
4939 +
4940 +       spin_lock_irqsave(&priv->page_lock, flags);
4941 +       fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4942 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4943 +               RT5350_SDM_MAC_ADRL);
4944 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4945 +}
4946 +
4947 +static void rt5350_fwd_config(struct fe_priv *priv)
4948 +{
4949 +       unsigned long sysclk = priv->sysclk;
4950 +
4951 +       if (sysclk) {
4952 +               sysclk /= FE_US_CYC_CNT_DIVISOR;
4953 +               sysclk <<= FE_US_CYC_CNT_SHIFT;
4954 +
4955 +               fe_w32((fe_r32(FE_FE_GLO_CFG) &
4956 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4957 +                       FE_FE_GLO_CFG);
4958 +       }
4959 +
4960 +       fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4961 +       fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4962 +               RT5350_SDM_CFG);
4963 +}
4964 +
4965 +static void rt5350_fe_reset(void)
4966 +{
4967 +       rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4968 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4969 +}
4970 +
4971 +static struct fe_soc_data rt3050_data = {
4972 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4973 +       .reset_fe = rt305x_fe_reset,
4974 +       .min_pkt_len = 64,
4975 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4976 +       .checksum_bit = RX_DMA_L4VALID,
4977 +       .rx_dly_int = FE_RX_DLY_INT,
4978 +       .tx_dly_int = FE_TX_DLY_INT,
4979 +};
4980 +
4981 +static struct fe_soc_data rt5350_data = {
4982 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4983 +       .reg_table = rt5350_reg_table,
4984 +       .reset_fe = rt5350_fe_reset,
4985 +       .set_mac = rt5350_set_mac,
4986 +       .fwd_config = rt5350_fwd_config,
4987 +       .min_pkt_len = 64,
4988 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4989 +       .checksum_bit = RX_DMA_L4VALID,
4990 +       .rx_dly_int = RT5350_RX_DLY_INT,
4991 +       .tx_dly_int = RT5350_TX_DLY_INT,
4992 +};
4993 +
4994 +const struct of_device_id of_fe_match[] = {
4995 +       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4996 +       { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4997 +       {},
4998 +};
4999 +
5000 +MODULE_DEVICE_TABLE(of, of_fe_match);
5001 --- /dev/null
5002 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
5003 @@ -0,0 +1,60 @@
5004 +/*
5005 + *   This program is free software; you can redistribute it and/or modify
5006 + *   it under the terms of the GNU General Public License as published by
5007 + *   the Free Software Foundation; version 2 of the License
5008 + *
5009 + *   This program is distributed in the hope that it will be useful,
5010 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5011 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5012 + *   GNU General Public License for more details.
5013 + *
5014 + *   You should have received a copy of the GNU General Public License
5015 + *   along with this program; if not, write to the Free Software
5016 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5017 + *
5018 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5019 + */
5020 +
5021 +#include <linux/module.h>
5022 +
5023 +#include <asm/mach-ralink/ralink_regs.h>
5024 +
5025 +#include "ralink_soc_eth.h"
5026 +#include "mdio_rt2880.h"
5027 +
5028 +#define RT3883_SYSC_REG_RSTCTRL                0x34
5029 +#define RT3883_RSTCTRL_FE              BIT(21)
5030 +
5031 +static void rt3883_fe_reset(void)
5032 +{
5033 +       u32 t;
5034 +
5035 +       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
5036 +       t |= RT3883_RSTCTRL_FE;
5037 +       rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
5038 +
5039 +       t &= ~RT3883_RSTCTRL_FE;
5040 +       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
5041 +}
5042 +
5043 +static struct fe_soc_data rt3883_data = {
5044 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5045 +       .reset_fe = rt3883_fe_reset,
5046 +       .min_pkt_len = 64,
5047 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5048 +       .rx_dly_int = FE_RX_DLY_INT,
5049 +       .tx_dly_int = FE_TX_DLY_INT,
5050 +       .checksum_bit = RX_DMA_L4VALID,
5051 +       .mdio_read = rt2880_mdio_read,
5052 +       .mdio_write = rt2880_mdio_write,
5053 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
5054 +       .port_init = rt2880_port_init,
5055 +};
5056 +
5057 +const struct of_device_id of_fe_match[] = {
5058 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
5059 +       {},
5060 +};
5061 +
5062 +MODULE_DEVICE_TABLE(of, of_fe_match);
5063 +