1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
4 * $Date: 2008-12-15 06:51:32 $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
37 #include <linux/list.h>
38 #include <linux/usb.h>
39 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
40 #include <linux/usb/hcd.h>
42 #include <../drivers/usb/core/hcd.h>
45 struct dwc_otg_device;
47 #include "dwc_otg_cil.h"
52 * This file contains the structures, constants, and interfaces for
53 * the Host Contoller Driver (HCD).
55 * The Host Controller Driver (HCD) is responsible for translating requests
56 * from the USB Driver into the appropriate actions on the DWC_otg controller.
57 * It isolates the USBD from the specifics of the controller by providing an
62 * Phases for control transfers.
64 typedef enum dwc_otg_control_phase {
65 DWC_OTG_CONTROL_SETUP,
67 DWC_OTG_CONTROL_STATUS
68 } dwc_otg_control_phase_e;
70 /** Transaction types. */
71 typedef enum dwc_otg_transaction_type {
72 DWC_OTG_TRANSACTION_NONE,
73 DWC_OTG_TRANSACTION_PERIODIC,
74 DWC_OTG_TRANSACTION_NON_PERIODIC,
75 DWC_OTG_TRANSACTION_ALL
76 } dwc_otg_transaction_type_e;
79 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
80 * interrupt, or isochronous transfer. A single QTD is created for each URB
81 * (of one of these types) submitted to the HCD. The transfer associated with
82 * a QTD may require one or multiple transactions.
84 * A QTD is linked to a Queue Head, which is entered in either the
85 * non-periodic or periodic schedule for execution. When a QTD is chosen for
86 * execution, some or all of its transactions may be executed. After
87 * execution, the state of the QTD is updated. The QTD may be retired if all
88 * its transactions are complete or if an error occurred. Otherwise, it
89 * remains in the schedule so more transactions can be executed later.
91 typedef struct dwc_otg_qtd {
93 * Determines the PID of the next data packet for the data phase of
94 * control transfers. Ignored for other transfer types.<br>
95 * One of the following values:
96 * - DWC_OTG_HC_PID_DATA0
97 * - DWC_OTG_HC_PID_DATA1
101 /** Current phase for control transfers (Setup, Data, or Status). */
102 dwc_otg_control_phase_e control_phase;
104 /** Keep track of the current split type
105 * for FS/LS endpoints on a HS Hub */
106 uint8_t complete_split;
108 /** How many bytes transferred during SSPLIT OUT */
109 uint32_t ssplit_out_xfer_count;
112 * Holds the number of bus errors that have occurred for a transaction
113 * within this transfer.
118 * Index of the next frame descriptor for an isochronous transfer. A
119 * frame descriptor describes the buffer position and length of the
120 * data to be transferred in the next scheduled (micro)frame of an
121 * isochronous transfer. It also holds status for that transaction.
122 * The frame index starts at 0.
124 int isoc_frame_index;
126 /** Position of the ISOC split on full/low speed */
127 uint8_t isoc_split_pos;
129 /** Position of the ISOC split in the buffer for the current frame */
130 uint16_t isoc_split_offset;
132 /** URB for this transfer */
135 /** This list of QTDs */
136 struct list_head qtd_list_entry;
141 * A Queue Head (QH) holds the static characteristics of an endpoint and
142 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
143 * be entered in either the non-periodic or periodic schedule.
145 typedef struct dwc_otg_qh {
148 * One of the following values:
149 * - USB_ENDPOINT_XFER_CONTROL
150 * - USB_ENDPOINT_XFER_ISOC
151 * - USB_ENDPOINT_XFER_BULK
152 * - USB_ENDPOINT_XFER_INT
157 /** wMaxPacketSize Field of Endpoint Descriptor. */
161 * Determines the PID of the next data packet for non-control
162 * transfers. Ignored for control transfers.<br>
163 * One of the following values:
164 * - DWC_OTG_HC_PID_DATA0
165 * - DWC_OTG_HC_PID_DATA1
169 /** Ping state if 1. */
173 * List of QTDs for this QH.
175 struct list_head qtd_list;
177 /** Host channel currently processing transfers for this QH. */
180 /** QTD currently assigned to a host channel for this QH. */
181 dwc_otg_qtd_t *qtd_in_process;
183 /** Full/low speed endpoint on high-speed hub requires split. */
186 /** @name Periodic schedule information */
189 /** Bandwidth in microseconds per (micro)frame. */
192 /** Interval between transfers in (micro)frames. */
196 * (micro)frame to initialize a periodic transfer. The transfer
197 * executes in the following (micro)frame.
199 uint16_t sched_frame;
201 /** (micro)frame at which last start split was initialized. */
202 uint16_t start_split_frame;
206 /** Entry for QH in either the periodic or non-periodic schedule. */
207 struct list_head qh_list_entry;
209 /* For non-dword aligned buffer support */
210 uint8_t *dw_align_buf;
211 dma_addr_t dw_align_buf_dma;
215 * This structure holds the state of the HCD, including the non-periodic and
216 * periodic schedules.
218 typedef struct dwc_otg_hcd {
219 /** The DWC otg device pointer */
220 struct dwc_otg_device *otg_dev;
222 /** DWC OTG Core Interface Layer */
223 dwc_otg_core_if_t *core_if;
225 /** Internal DWC HCD Flags */
226 volatile union dwc_otg_hcd_internal_flags {
229 unsigned port_connect_status_change : 1;
230 unsigned port_connect_status : 1;
231 unsigned port_reset_change : 1;
232 unsigned port_enable_change : 1;
233 unsigned port_suspend_change : 1;
234 unsigned port_over_current_change : 1;
235 unsigned reserved : 27;
240 * Inactive items in the non-periodic schedule. This is a list of
241 * Queue Heads. Transfers associated with these Queue Heads are not
242 * currently assigned to a host channel.
244 struct list_head non_periodic_sched_inactive;
247 * Active items in the non-periodic schedule. This is a list of
248 * Queue Heads. Transfers associated with these Queue Heads are
249 * currently assigned to a host channel.
251 struct list_head non_periodic_sched_active;
254 * Pointer to the next Queue Head to process in the active
255 * non-periodic schedule.
257 struct list_head *non_periodic_qh_ptr;
260 * Inactive items in the periodic schedule. This is a list of QHs for
261 * periodic transfers that are _not_ scheduled for the next frame.
262 * Each QH in the list has an interval counter that determines when it
263 * needs to be scheduled for execution. This scheduling mechanism
264 * allows only a simple calculation for periodic bandwidth used (i.e.
265 * must assume that all periodic transfers may need to execute in the
266 * same frame). However, it greatly simplifies scheduling and should
267 * be sufficient for the vast majority of OTG hosts, which need to
268 * connect to a small number of peripherals at one time.
270 * Items move from this list to periodic_sched_ready when the QH
271 * interval counter is 0 at SOF.
273 struct list_head periodic_sched_inactive;
276 * List of periodic QHs that are ready for execution in the next
277 * frame, but have not yet been assigned to host channels.
279 * Items move from this list to periodic_sched_assigned as host
280 * channels become available during the current frame.
282 struct list_head periodic_sched_ready;
285 * List of periodic QHs to be executed in the next frame that are
286 * assigned to host channels.
288 * Items move from this list to periodic_sched_queued as the
289 * transactions for the QH are queued to the DWC_otg controller.
291 struct list_head periodic_sched_assigned;
294 * List of periodic QHs that have been queued for execution.
296 * Items move from this list to either periodic_sched_inactive or
297 * periodic_sched_ready when the channel associated with the transfer
298 * is released. If the interval for the QH is 1, the item moves to
299 * periodic_sched_ready because it must be rescheduled for the next
300 * frame. Otherwise, the item moves to periodic_sched_inactive.
302 struct list_head periodic_sched_queued;
305 * Total bandwidth claimed so far for periodic transfers. This value
306 * is in microseconds per (micro)frame. The assumption is that all
307 * periodic transfers may occur in the same (micro)frame.
309 uint16_t periodic_usecs;
312 * Frame number read from the core at SOF. The value ranges from 0 to
313 * DWC_HFNUM_MAX_FRNUM.
315 uint16_t frame_number;
318 * Free host channels in the controller. This is a list of
321 struct list_head free_hc_list;
324 * Number of host channels assigned to periodic transfers. Currently
325 * assuming that there is a dedicated host channel for each periodic
326 * transaction and at least one host channel available for
327 * non-periodic transactions.
329 int periodic_channels;
332 * Number of host channels assigned to non-periodic transfers.
334 int non_periodic_channels;
337 * Array of pointers to the host channel descriptors. Allows accessing
338 * a host channel descriptor given the host channel number. This is
339 * useful in interrupt handlers.
341 dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
344 * Buffer to use for any data received during the status phase of a
345 * control transfer. Normally no data is transferred during the status
346 * phase. This buffer is used as a bit bucket.
351 * DMA address for status_buf.
353 dma_addr_t status_buf_dma;
354 #define DWC_OTG_HCD_STATUS_BUF_SIZE 64
357 * Structure to allow starting the HCD in a non-interrupt context
358 * during an OTG role change.
360 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
361 struct work_struct start_work;
363 struct delayed_work start_work;
367 * Connection timer. An OTG host must display a message if the device
368 * does not connect. Started when the VBus power is turned on via
369 * sysfs attribute "buspower".
371 struct timer_list conn_timer;
373 /* Tasket to do a reset */
374 struct tasklet_struct *reset_tasklet;
380 uint32_t frrem_samples;
381 uint64_t frrem_accum;
383 uint32_t hfnum_7_samples_a;
384 uint64_t hfnum_7_frrem_accum_a;
385 uint32_t hfnum_0_samples_a;
386 uint64_t hfnum_0_frrem_accum_a;
387 uint32_t hfnum_other_samples_a;
388 uint64_t hfnum_other_frrem_accum_a;
390 uint32_t hfnum_7_samples_b;
391 uint64_t hfnum_7_frrem_accum_b;
392 uint32_t hfnum_0_samples_b;
393 uint64_t hfnum_0_frrem_accum_b;
394 uint32_t hfnum_other_samples_b;
395 uint64_t hfnum_other_frrem_accum_b;
399 /** Gets the dwc_otg_hcd from a struct usb_hcd */
400 static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
402 return (dwc_otg_hcd_t *)(hcd->hcd_priv);
405 /** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
406 static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
408 return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
411 /** @name HCD Create/Destroy Functions */
413 extern int dwc_otg_hcd_init(struct device *dev);
414 extern void dwc_otg_hcd_remove(struct device *dev);
417 /** @name Linux HC Driver API Functions */
420 extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
421 extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
422 extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
423 extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
424 extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
426 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
432 extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
433 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
435 struct urb *urb, int status);
436 extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
437 struct usb_host_endpoint *ep);
438 extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd
439 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
440 , struct pt_regs *regs
443 extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
445 extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
454 /** @name Transaction Execution Functions */
456 extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
457 extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
458 dwc_otg_transaction_type_e tr_type);
459 extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
463 /** @name Interrupt Handler Functions */
465 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
466 extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
467 extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
468 extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
469 extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
470 extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
471 extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
472 extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
473 extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
474 extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
475 extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
476 extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
477 extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
481 /** @name Schedule Queue Functions */
484 /* Implemented in dwc_otg_hcd_queue.c */
485 extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
486 extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
487 extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
488 extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
489 extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
490 extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
492 /** Remove and free a QH */
493 static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
496 dwc_otg_hcd_qh_remove(hcd, qh);
497 dwc_otg_hcd_qh_free(hcd, qh);
500 /** Allocates memory for a QH structure.
501 * @return Returns the memory allocate or NULL on error. */
502 static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
504 return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
507 extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
508 extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
509 extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
511 /** Allocates memory for a QTD structure.
512 * @return Returns the memory allocate or NULL on error. */
513 static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
515 return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
518 /** Frees the memory for a QTD structure. QTD should already be removed from
520 * @param[in] qtd QTD to free.*/
521 static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
526 /** Removes a QTD from list.
527 * @param[in] hcd HCD instance.
528 * @param[in] qtd QTD to remove from list. */
529 static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
532 SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
533 list_del(&qtd->qtd_list_entry);
534 SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
537 /** Remove and free a QTD */
538 static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
540 dwc_otg_hcd_qtd_remove(hcd, qtd);
541 dwc_otg_hcd_qtd_free(qtd);
547 /** @name Internal Functions */
549 dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
550 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
551 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
554 /** Gets the usb_host_endpoint associated with an URB. */
555 static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
557 struct usb_device *dev = urb->dev;
558 int ep_num = usb_pipeendpoint(urb->pipe);
560 if (usb_pipein(urb->pipe))
561 return dev->ep_in[ep_num];
563 return dev->ep_out[ep_num];
567 * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
568 * qualified with its direction (possible 32 endpoints per device).
570 #define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
571 ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
573 /** Gets the QH that contains the list_head */
574 #define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
576 /** Gets the QTD that contains the list_head */
577 #define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
579 /** Check if QH is non-periodic */
580 #define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
581 (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
583 /** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
584 #define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
586 /** Packet size for any kind of endpoint descriptor */
587 #define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
590 * Returns true if _frame1 is less than or equal to _frame2. The comparison is
591 * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
592 * frame number when the max frame number is reached.
594 static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
596 return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
597 (DWC_HFNUM_MAX_FRNUM >> 1);
601 * Returns true if _frame1 is greater than _frame2. The comparison is done
602 * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
603 * number when the max frame number is reached.
605 static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
607 return (frame1 != frame2) &&
608 (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
609 (DWC_HFNUM_MAX_FRNUM >> 1));
613 * Increments _frame by the amount specified by _inc. The addition is done
614 * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
616 static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
618 return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
621 static inline uint16_t dwc_full_frame_num(uint16_t frame)
623 return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
626 static inline uint16_t dwc_micro_frame_num(uint16_t frame)
633 * Macro to sample the remaining PHY clocks left in the current frame. This
634 * may be used during debugging to determine the average time it takes to
635 * execute sections of code. There are two possible sample points, "a" and
636 * "b", so the _letter argument must be one of these values.
638 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
639 * example, "cat /sys/devices/lm0/hcd_frrem".
641 #define dwc_sample_frrem(_hcd, _qh, _letter) \
643 hfnum_data_t hfnum; \
644 dwc_otg_qtd_t *qtd; \
645 qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
646 if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
647 hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
648 switch (hfnum.b.frnum & 0x7) { \
650 _hcd->hfnum_7_samples_##_letter++; \
651 _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
654 _hcd->hfnum_0_samples_##_letter++; \
655 _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
658 _hcd->hfnum_other_samples_##_letter++; \
659 _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
665 #define dwc_sample_frrem(_hcd, _qh, _letter)
668 #endif /* DWC_DEVICE_ONLY */