target/linux/ramips/files-3.7/drivers/spi/spi-ramips.c

   1 /*
   2  * ramips_spi.c -- Ralink RT288x/RT305x SPI controller driver
   3  *
   4  * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
   5  * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/delay.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/spi/spi.h>
  20
  21 #define DRIVER_NAME                     "ramips-spi"
  22 #define RALINK_NUM_CHIPSELECTS          1 /* only one slave is supported*/
  23 #define RALINK_SPI_WAIT_RDY_MAX_LOOP    2000 /* in usec */
  24
  25 #define RAMIPS_SPI_STAT                 0x00
  26 #define RAMIPS_SPI_CFG                  0x10
  27 #define RAMIPS_SPI_CTL                  0x14
  28 #define RAMIPS_SPI_DATA                 0x20
  29
  30 /* SPISTAT register bit field */
  31 #define SPISTAT_BUSY                    BIT(0)
  32
  33 /* SPICFG register bit field */
  34 #define SPICFG_LSBFIRST                 0
  35 #define SPICFG_MSBFIRST                 BIT(8)
  36 #define SPICFG_SPICLKPOL                BIT(6)
  37 #define SPICFG_RXCLKEDGE_FALLING        BIT(5)
  38 #define SPICFG_TXCLKEDGE_FALLING        BIT(4)
  39 #define SPICFG_SPICLK_PRESCALE_MASK     0x7
  40 #define SPICFG_SPICLK_DIV2              0
  41 #define SPICFG_SPICLK_DIV4              1
  42 #define SPICFG_SPICLK_DIV8              2
  43 #define SPICFG_SPICLK_DIV16             3
  44 #define SPICFG_SPICLK_DIV32             4
  45 #define SPICFG_SPICLK_DIV64             5
  46 #define SPICFG_SPICLK_DIV128            6
  47 #define SPICFG_SPICLK_DISABLE           7
  48
  49 /* SPICTL register bit field */
  50 #define SPICTL_HIZSDO                   BIT(3)
  51 #define SPICTL_STARTWR                  BIT(2)
  52 #define SPICTL_STARTRD                  BIT(1)
  53 #define SPICTL_SPIENA                   BIT(0)
  54
  55 #ifdef DEBUG
  56 #define spi_debug(args...) printk(args)
  57 #else
  58 #define spi_debug(args...)
  59 #endif
  60
  61 struct ramips_spi {
  62         struct work_struct      work;
  63
  64         /* Lock access to transfer list.*/
  65         spinlock_t              lock;
  66
  67         struct list_head        msg_queue;
  68         struct spi_master       *master;
  69         void __iomem            *base;
  70         unsigned int            sys_freq;
  71         unsigned int            speed;
  72
  73         struct clk              *clk;
  74 };
  75
  76 static struct workqueue_struct *ramips_spi_wq;
  77
  78 static inline struct ramips_spi *ramips_spidev_to_rs(struct spi_device *spi)
  79 {
  80         return spi_master_get_devdata(spi->master);
  81 }
  82
  83 static inline u32 ramips_spi_read(struct ramips_spi *rs, u32 reg)
  84 {
  85         return ioread32(rs->base + reg);
  86 }
  87
  88 static inline void ramips_spi_write(struct ramips_spi *rs, u32 reg, u32 val)
  89 {
  90         iowrite32(val, rs->base + reg);
  91 }
  92
  93 static inline void ramips_spi_setbits(struct ramips_spi *rs, u32 reg, u32 mask)
  94 {
  95         void __iomem *addr = rs->base + reg;
  96         u32 val;
  97
  98         val = ioread32(addr);
  99         val |= mask;
 100         iowrite32(val, addr);
 101 }
 102
 103 static inline void ramips_spi_clrbits(struct ramips_spi *rs, u32 reg, u32 mask)
 104 {
 105         void __iomem *addr = rs->base + reg;
 106         u32 val;
 107
 108         val = ioread32(addr);
 109         val &= ~mask;
 110         iowrite32(val, addr);
 111 }
 112
 113 static int ramips_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 114 {
 115         struct ramips_spi *rs = ramips_spidev_to_rs(spi);
 116         u32 rate;
 117         u32 prescale;
 118         u32 reg;
 119
 120         spi_debug("%s: speed:%u\n", __func__, speed);
 121
 122         /*
 123          * the supported rates are: 2,4,8...128
 124          * round up as we look for equal or less speed
 125          */
 126         rate = DIV_ROUND_UP(rs->sys_freq, speed);
 127         spi_debug("%s: rate-1:%u\n", __func__, rate);
 128         rate = roundup_pow_of_two(rate);
 129         spi_debug("%s: rate-2:%u\n", __func__, rate);
 130
 131         /* check if requested speed is too small */
 132         if (rate > 128)
 133                 return -EINVAL;
 134
 135         if (rate < 2)
 136                 rate = 2;
 137
 138         /* Convert the rate to SPI clock divisor value. */
 139         prescale = ilog2(rate/2);
 140         spi_debug("%s: prescale:%u\n", __func__, prescale);
 141
 142         reg = ramips_spi_read(rs, RAMIPS_SPI_CFG);
 143         reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
 144         ramips_spi_write(rs, RAMIPS_SPI_CFG, reg);
 145         rs->speed = speed;
 146         return 0;
 147 }
 148
 149 /*
 150  * called only when no transfer is active on the bus
 151  */
 152 static int
 153 ramips_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 154 {
 155         struct ramips_spi *rs = ramips_spidev_to_rs(spi);
 156         unsigned int speed = spi->max_speed_hz;
 157         int     rc;
 158         unsigned int bits_per_word = 8;
 159
 160         if ((t != NULL) && t->speed_hz)
 161                 speed = t->speed_hz;
 162
 163         if ((t != NULL) && t->bits_per_word)
 164                 bits_per_word = t->bits_per_word;
 165
 166         if (rs->speed != speed) {
 167                 spi_debug("%s: speed_hz:%u\n", __func__, speed);
 168                 rc = ramips_spi_baudrate_set(spi, speed);
 169                 if (rc)
 170                         return rc;
 171         }
 172
 173         if (bits_per_word != 8) {
 174                 spi_debug("%s: bad bits_per_word: %u\n", __func__,
 175                           bits_per_word);
 176                 return -EINVAL;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static void ramips_spi_set_cs(struct ramips_spi *rs, int enable)
 183 {
 184         if (enable)
 185                 ramips_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 186         else
 187                 ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 188 }
 189
 190 static inline int ramips_spi_wait_till_ready(struct ramips_spi *rs)
 191 {
 192         int i;
 193
 194         for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
 195                 u32 status;
 196
 197                 status = ramips_spi_read(rs, RAMIPS_SPI_STAT);
 198                 if ((status & SPISTAT_BUSY) == 0)
 199                         return 0;
 200
 201                 udelay(1);
 202         }
 203
 204         return -ETIMEDOUT;
 205 }
 206
 207 static unsigned int
 208 ramips_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 209 {
 210         struct ramips_spi *rs = ramips_spidev_to_rs(spi);
 211         unsigned count = 0;
 212         u8 *rx = xfer->rx_buf;
 213         const u8 *tx = xfer->tx_buf;
 214         int err;
 215
 216         spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
 217                   (tx != NULL) ? "tx" : "  ",
 218                   (rx != NULL) ? "rx" : "  ");
 219
 220         if (tx) {
 221                 for (count = 0; count < xfer->len; count++) {
 222                         ramips_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
 223                         ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 224                         err = ramips_spi_wait_till_ready(rs);
 225                         if (err) {
 226                                 dev_err(&spi->dev, "TX failed, err=%d\n", err);
 227                                 goto out;
 228                         }
 229                 }
 230         }
 231
 232         if (rx) {
 233                 for (count = 0; count < xfer->len; count++) {
 234                         ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 235                         err = ramips_spi_wait_till_ready(rs);
 236                         if (err) {
 237                                 dev_err(&spi->dev, "RX failed, err=%d\n", err);
 238                                 goto out;
 239                         }
 240                         rx[count] = (u8) ramips_spi_read(rs, RAMIPS_SPI_DATA);
 241                 }
 242         }
 243
 244 out:
 245         return count;
 246 }
 247
 248 static void ramips_spi_work(struct work_struct *work)
 249 {
 250         struct ramips_spi *rs =
 251                 container_of(work, struct ramips_spi, work);
 252
 253         spin_lock_irq(&rs->lock);
 254         while (!list_empty(&rs->msg_queue)) {
 255                 struct spi_message *m;
 256                 struct spi_device *spi;
 257                 struct spi_transfer *t = NULL;
 258                 int par_override = 0;
 259                 int status = 0;
 260                 int cs_active = 0;
 261
 262                 m = container_of(rs->msg_queue.next, struct spi_message,
 263                                  queue);
 264
 265                 list_del_init(&m->queue);
 266                 spin_unlock_irq(&rs->lock);
 267
 268                 spi = m->spi;
 269
 270                 /* Load defaults */
 271                 status = ramips_spi_setup_transfer(spi, NULL);
 272
 273                 if (status < 0)
 274                         goto msg_done;
 275
 276                 list_for_each_entry(t, &m->transfers, transfer_list) {
 277                         if (par_override || t->speed_hz || t->bits_per_word) {
 278                                 par_override = 1;
 279                                 status = ramips_spi_setup_transfer(spi, t);
 280                                 if (status < 0)
 281                                         break;
 282                                 if (!t->speed_hz && !t->bits_per_word)
 283                                         par_override = 0;
 284                         }
 285
 286                         if (!cs_active) {
 287                                 ramips_spi_set_cs(rs, 1);
 288                                 cs_active = 1;
 289                         }
 290
 291                         if (t->len)
 292                                 m->actual_length +=
 293                                         ramips_spi_write_read(spi, t);
 294
 295                         if (t->delay_usecs)
 296                                 udelay(t->delay_usecs);
 297
 298                         if (t->cs_change) {
 299                                 ramips_spi_set_cs(rs, 0);
 300                                 cs_active = 0;
 301                         }
 302                 }
 303
 304 msg_done:
 305                 if (cs_active)
 306                         ramips_spi_set_cs(rs, 0);
 307
 308                 m->status = status;
 309                 m->complete(m->context);
 310
 311                 spin_lock_irq(&rs->lock);
 312         }
 313
 314         spin_unlock_irq(&rs->lock);
 315 }
 316
 317 static int ramips_spi_setup(struct spi_device *spi)
 318 {
 319         struct ramips_spi *rs = ramips_spidev_to_rs(spi);
 320
 321         if ((spi->max_speed_hz == 0) ||
 322             (spi->max_speed_hz > (rs->sys_freq / 2)))
 323                 spi->max_speed_hz = (rs->sys_freq / 2);
 324
 325         if (spi->max_speed_hz < (rs->sys_freq/128)) {
 326                 dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
 327                         spi->max_speed_hz);
 328                 return -EINVAL;
 329         }
 330
 331         if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
 332                 dev_err(&spi->dev,
 333                         "setup: requested bits per words - os wrong %d bpw\n",
 334                         spi->bits_per_word);
 335                 return -EINVAL;
 336         }
 337
 338         if (spi->bits_per_word == 0)
 339                 spi->bits_per_word = 8;
 340
 341         /*
 342          * baudrate & width will be set ramips_spi_setup_transfer
 343          */
 344         return 0;
 345 }
 346
 347 static int ramips_spi_transfer(struct spi_device *spi, struct spi_message *m)
 348 {
 349         struct ramips_spi *rs;
 350         struct spi_transfer *t = NULL;
 351         unsigned long flags;
 352
 353         m->actual_length = 0;
 354         m->status = 0;
 355
 356         /* reject invalid messages and transfers */
 357         if (list_empty(&m->transfers) || !m->complete)
 358                 return -EINVAL;
 359
 360         rs = ramips_spidev_to_rs(spi);
 361
 362         list_for_each_entry(t, &m->transfers, transfer_list) {
 363                 unsigned int bits_per_word = spi->bits_per_word;
 364
 365                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 366                         dev_err(&spi->dev,
 367                                 "message rejected : "
 368                                 "invalid transfer data buffers\n");
 369                         goto msg_rejected;
 370                 }
 371
 372                 if (t->bits_per_word)
 373                         bits_per_word = t->bits_per_word;
 374
 375                 if (bits_per_word != 8) {
 376                         dev_err(&spi->dev,
 377                                 "message rejected : "
 378                                 "invalid transfer bits_per_word (%d bits)\n",
 379                                 bits_per_word);
 380                         goto msg_rejected;
 381                 }
 382
 383                 if (t->speed_hz && t->speed_hz < (rs->sys_freq/128)) {
 384                         dev_err(&spi->dev,
 385                                 "message rejected : "
 386                                 "device min speed (%d Hz) exceeds "
 387                                 "required transfer speed (%d Hz)\n",
 388                                 (rs->sys_freq/128), t->speed_hz);
 389                         goto msg_rejected;
 390                 }
 391         }
 392
 393
 394         spin_lock_irqsave(&rs->lock, flags);
 395         list_add_tail(&m->queue, &rs->msg_queue);
 396         queue_work(ramips_spi_wq, &rs->work);
 397         spin_unlock_irqrestore(&rs->lock, flags);
 398
 399         return 0;
 400 msg_rejected:
 401         /* Message rejected and not queued */
 402         m->status = -EINVAL;
 403         if (m->complete)
 404                 m->complete(m->context);
 405         return -EINVAL;
 406 }
 407
 408 static void __init ramips_spi_reset(struct ramips_spi *rs)
 409 {
 410         ramips_spi_write(rs, RAMIPS_SPI_CFG,
 411                          SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
 412                          SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
 413         ramips_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 414 }
 415
 416 static int __init ramips_spi_probe(struct platform_device *pdev)
 417 {
 418         struct spi_master *master;
 419         struct ramips_spi *rs;
 420         struct resource *r;
 421         int status = 0;
 422
 423         master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 424         if (master == NULL) {
 425                 dev_dbg(&pdev->dev, "master allocation failed\n");
 426                 return -ENOMEM;
 427         }
 428
 429         if (pdev->id != -1)
 430                 master->bus_num = pdev->id;
 431
 432         /* we support only mode 0, and no options */
 433         master->mode_bits = 0;
 434
 435         master->setup = ramips_spi_setup;
 436         master->transfer = ramips_spi_transfer;
 437         master->num_chipselect = RALINK_NUM_CHIPSELECTS;
 438
 439         dev_set_drvdata(&pdev->dev, master);
 440
 441         rs = spi_master_get_devdata(master);
 442         rs->master = master;
 443
 444         rs->clk = clk_get(NULL, "sys");
 445         if (IS_ERR(rs->clk)) {
 446                 status = PTR_ERR(rs->clk);
 447                 dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 448                         status);
 449                 goto out_put_master;
 450         }
 451
 452         status = clk_enable(rs->clk);
 453         if (status)
 454                 goto out_put_clk;
 455
 456         rs->sys_freq = clk_get_rate(rs->clk);
 457         spi_debug("%s: sys_freq: %ld\n", __func__, rs->sys_freq);
 458
 459         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 460         if (r == NULL) {
 461                 status = -ENODEV;
 462                 goto out_disable_clk;
 463         }
 464
 465         if (!request_mem_region(r->start, (r->end - r->start) + 1,
 466                                 dev_name(&pdev->dev))) {
 467                 status = -EBUSY;
 468                 goto out_disable_clk;
 469         }
 470
 471         rs->base = ioremap(r->start, resource_size(r));
 472         if (rs->base == NULL) {
 473                 dev_err(&pdev->dev, "ioremap failed\n");
 474                 status = -ENOMEM;
 475                 goto out_rel_mem;
 476         }
 477
 478         INIT_WORK(&rs->work, ramips_spi_work);
 479
 480         spin_lock_init(&rs->lock);
 481         INIT_LIST_HEAD(&rs->msg_queue);
 482
 483         ramips_spi_reset(rs);
 484
 485         status = spi_register_master(master);
 486         if (status)
 487                 goto out_unmap_base;
 488
 489         return 0;
 490
 491 out_unmap_base:
 492         iounmap(rs->base);
 493 out_rel_mem:
 494         release_mem_region(r->start, (r->end - r->start) + 1);
 495 out_disable_clk:
 496         clk_disable(rs->clk);
 497 out_put_clk:
 498         clk_put(rs->clk);
 499 out_put_master:
 500         spi_master_put(master);
 501         return status;
 502 }
 503
 504 static int ramips_spi_remove(struct platform_device *pdev)
 505 {
 506         struct spi_master *master;
 507         struct ramips_spi *rs;
 508         struct resource *r;
 509
 510         master = dev_get_drvdata(&pdev->dev);
 511         rs = spi_master_get_devdata(master);
 512
 513         cancel_work_sync(&rs->work);
 514
 515         iounmap(rs->base);
 516         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 517         release_mem_region(r->start, (r->end - r->start) + 1);
 518
 519         clk_disable(rs->clk);
 520         clk_put(rs->clk);
 521         spi_unregister_master(master);
 522
 523         return 0;
 524 }
 525
 526 MODULE_ALIAS("platform:" DRIVER_NAME);
 527
 528 static struct platform_driver ramips_spi_driver = {
 529         .driver = {
 530                 .name   = DRIVER_NAME,
 531                 .owner  = THIS_MODULE,
 532         },
 533         .remove         = ramips_spi_remove,
 534 };
 535
 536 static int __init ramips_spi_init(void)
 537 {
 538         ramips_spi_wq = create_singlethread_workqueue(
 539                                 ramips_spi_driver.driver.name);
 540         if (ramips_spi_wq == NULL)
 541                 return -ENOMEM;
 542
 543         return platform_driver_probe(&ramips_spi_driver, ramips_spi_probe);
 544 }
 545 module_init(ramips_spi_init);
 546
 547 static void __exit ramips_spi_exit(void)
 548 {
 549         flush_workqueue(ramips_spi_wq);
 550         platform_driver_unregister(&ramips_spi_driver);
 551
 552         destroy_workqueue(ramips_spi_wq);
 553 }
 554 module_exit(ramips_spi_exit);
 555
 556 MODULE_DESCRIPTION("Ralink SPI driver");
 557 MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 558 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 559 MODULE_LICENSE("GPL");