ralink: add 3.18 support
[openwrt.git] / target / linux / ramips / dts / mt7628an.dtsi
1 / {
2         #address-cells = <1>;
3         #size-cells = <1>;
4         compatible = "ralink,mtk7628an-soc";
5
6         cpus {
7                 cpu@0 {
8                         compatible = "mips,mips24KEc";
9                 };
10         };
11
12         cpuintc: cpuintc@0 {
13                 #address-cells = <0>;
14                 #interrupt-cells = <1>;
15                 interrupt-controller;
16                 compatible = "mti,cpu-interrupt-controller";
17         };
18
19         palmbus@10000000 {
20                 compatible = "palmbus";
21                 reg = <0x10000000 0x200000>;
22                 ranges = <0x0 0x10000000 0x1FFFFF>;
23
24                 #address-cells = <1>;
25                 #size-cells = <1>;
26
27                 sysc@0 {
28                         compatible = "ralink,mt7620a-sysc";
29                         reg = <0x0 0x100>;
30                 };
31
32                 watchdog@120 {
33                         compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
34                         reg = <0x120 0x10>;
35
36                         resets = <&rstctrl 8>;
37                         reset-names = "wdt";
38
39                         interrupt-parent = <&intc>;
40                         interrupts = <24>;
41                 };
42
43                 intc: intc@200 {
44                         compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
45                         reg = <0x200 0x100>;
46
47                         resets = <&rstctrl 9>;
48                         reset-names = "intc";
49
50                         interrupt-controller;
51                         #interrupt-cells = <1>;
52
53                         interrupt-parent = <&cpuintc>;
54                         interrupts = <2>;
55
56                         ralink,intc-registers = <0x9c 0xa0
57                                                  0x6c 0xa4
58                                                  0x80 0x78>;
59                 };
60
61                 memc@300 {
62                         compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
63                         reg = <0x300 0x100>;
64
65                         resets = <&rstctrl 20>;
66                         reset-names = "mc";
67
68                         interrupt-parent = <&intc>;
69                         interrupts = <3>;
70                 };
71
72                 gpio@600 {
73                         #address-cells = <1>;
74                         #size-cells = <0>;
75
76                         compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
77                         reg = <0x600 0x100>;
78
79                         gpio0: bank@0 {
80                                 reg = <0>;
81                                 compatible = "mtk,mt7621-gpio-bank";
82                                 gpio-controller;
83                                 #gpio-cells = <2>;
84                         };
85
86                         gpio1: bank@1 {
87                                 reg = <1>;
88                                 compatible = "mtk,mt7621-gpio-bank";
89                                 gpio-controller;
90                                 #gpio-cells = <2>;
91                         };
92
93                         gpio2: bank@2 {
94                                 reg = <2>;
95                                 compatible = "mtk,mt7621-gpio-bank";
96                                 gpio-controller;
97                                 #gpio-cells = <2>;
98                         };
99                 };
100
101                 spi@b00 {
102                         compatible = "ralink,mt7621-spi";
103                         reg = <0xb00 0x100>;
104
105                         resets = <&rstctrl 18>;
106                         reset-names = "spi";
107
108                         #address-cells = <1>;
109                         #size-cells = <1>;
110
111                         pinctrl-names = "default";
112                         pinctrl-0 = <&spi_pins>;
113
114                         status = "disabled";
115                 };
116
117                 uartlite@c00 {
118                         compatible = "ns16550a";
119                         reg = <0xc00 0x100>;
120
121                         reg-shift = <2>;
122                         reg-io-width = <4>;
123                         no-loopback-test;
124
125                         resets = <&rstctrl 12>;
126                         reset-names = "uartl";
127
128                         interrupt-parent = <&intc>;
129                         interrupts = <20>;
130
131                         pinctrl-names = "default";
132                         pinctrl-0 = <&uart0_pins>;
133                 };
134         };
135
136         pinctrl {
137                 compatible = "ralink,rt2880-pinmux";
138                 pinctrl-names = "default";
139                 pinctrl-0 = <&state_default>;
140                 state_default: pinctrl0 {
141                 };
142                 spi_pins: spi {
143                         spi {
144                                 ralink,group = "spi";
145                                 ralink,function = "spi";
146                         };
147                 };
148                 uart0_pins: uartlite {
149                         uart {
150                                 ralink,group = "uart0";
151                                 ralink,function = "uart";
152                         };
153                 };
154         };
155
156         rstctrl: rstctrl {
157                 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
158                 #reset-cells = <1>;
159         };
160
161         usbphy: usbphy {
162                 compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
163                 #phy-cells = <1>;
164
165                 resets = <&rstctrl 22>;
166                 reset-names = "host";
167         };
168
169         sdhci@10130000 {
170                 compatible = "ralink,mt7620-sdhci";
171                 reg = <0x10130000 4000>;
172
173                 interrupt-parent = <&intc>;
174                 interrupts = <14>;
175
176                 status = "disabled";
177         };
178
179         ehci@101c0000 {
180                 compatible = "ralink,rt3xxx-ehci";
181                 reg = <0x101c0000 0x1000>;
182
183                 phys = <&usbphy 1>;
184                 phy-names = "usb";
185
186                 interrupt-parent = <&intc>;
187                 interrupts = <18>;
188         };
189
190         ohci@101c1000 {
191                 compatible = "ralink,rt3xxx-ohci";
192                 reg = <0x101c1000 0x1000>;
193
194                 phys = <&usbphy 1>;
195                 phy-names = "usb";
196
197                 interrupt-parent = <&intc>;
198                 interrupts = <18>;
199         };
200
201         ethernet@10100000 {
202                 compatible = "ralink,rt5350-eth";
203                 reg = <0x10100000 10000>;
204
205                 interrupt-parent = <&cpuintc>;
206                 interrupts = <5>;
207
208                 resets = <&rstctrl 21 &rstctrl 23>;
209                 reset-names = "fe", "esw";
210         };
211
212         esw@10110000 {
213                 compatible = "ralink,rt3050-esw";
214                 reg = <0x10110000 8000>;
215
216                 resets = <&rstctrl 23>;
217                 reset-names = "esw";
218
219                 interrupt-parent = <&intc>;
220                 interrupts = <17>;
221         };
222
223         pcie@10140000 {
224                 compatible = "mediatek,mt7620-pci";
225                 reg = <0x10140000 0x100
226                         0x10142000 0x100>;
227
228                 #address-cells = <3>;
229                 #size-cells = <2>;
230
231                 resets = <&rstctrl 26>;
232                 reset-names = "pcie0";
233
234                 interrupt-parent = <&cpuintc>;
235                 interrupts = <4>;
236
237                 status = "disabled";
238
239                 device_type = "pci";
240
241                 bus-range = <0 255>;
242                 ranges = <
243                         0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
244                         0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
245                 >;
246
247                 pcie-bridge {
248                         reg = <0x0000 0 0 0 0>;
249
250                         #address-cells = <3>;
251                         #size-cells = <2>;
252
253                         device_type = "pci";
254                 };
255         };
256
257 };