target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mtk7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         aliases {
  26                 serial0 = &uartlite;
  27         };
  28
  29         cpuclock: cpuclock@0 {
  30                 #clock-cells = <0>;
  31                 compatible = "fixed-clock";
  32
  33                 /* FIXME: there should be way to detect this */
  34                 clock-frequency = <880000000>;
  35         };
  36
  37         sysclock: sysclock@0 {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40
  41                 /* FIXME: there should be way to detect this */
  42                 clock-frequency = <50000000>;
  43         };
  44
  45         palmbus@1E000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1E000000 0x100000>;
  48                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc@0 {
  54                         compatible = "mtk,mt7621-sysc";
  55                         reg = <0x0 0x100>;
  56                 };
  57
  58                 wdt@100 {
  59                         compatible = "mtk,mt7621-wdt";
  60                         reg = <0x100 0x100>;
  61                 };
  62
  63                 gpio@600 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66
  67                         compatible = "mtk,mt7621-gpio";
  68                         reg = <0x600 0x100>;
  69
  70                         gpio0: bank@0 {
  71                                 reg = <0>;
  72                                 compatible = "mtk,mt7621-gpio-bank";
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                         };
  76
  77                         gpio1: bank@1 {
  78                                 reg = <1>;
  79                                 compatible = "mtk,mt7621-gpio-bank";
  80                                 gpio-controller;
  81                                 #gpio-cells = <2>;
  82                         };
  83
  84                         gpio2: bank@2 {
  85                                 reg = <2>;
  86                                 compatible = "mtk,mt7621-gpio-bank";
  87                                 gpio-controller;
  88                                 #gpio-cells = <2>;
  89                         };
  90                 };
  91
  92                 memc@5000 {
  93                         compatible = "mtk,mt7621-memc";
  94                         reg = <0x300 0x100>;
  95                 };
  96
  97                 cpc@1fbf0000 {
  98                              compatible = "mtk,mt7621-cpc";
  99                              reg = <0x1fbf0000 0x8000>;
 100                 };
 101
 102                 mc@1fbf8000 {
 103                             compatible = "mtk,mt7621-mc";
 104                             reg = <0x1fbf8000 0x8000>;
 105                 };
 106
 107                 uartlite: uartlite@c00 {
 108                         compatible = "ns16550a";
 109                         reg = <0xc00 0x100>;
 110
 111                         clocks = <&sysclock>;
 112
 113                         interrupt-parent = <&gic>;
 114                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 115
 116                         reg-shift = <2>;
 117                         reg-io-width = <4>;
 118                         no-loopback-test;
 119                 };
 120
 121                 spi@b00 {
 122                         status = "okay";
 123
 124                         compatible = "ralink,mt7621-spi";
 125                         reg = <0xb00 0x100>;
 126
 127                         clocks = <&sysclock>;
 128
 129                         resets = <&rstctrl 18>;
 130                         reset-names = "spi";
 131
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&spi_pins>;
 137
 138                         m25p80@0 {
 139                                 #address-cells = <1>;
 140                                 #size-cells = <1>;
 141                                 reg = <0 0>;
 142                                 spi-max-frequency = <10000000>;
 143                                 m25p,chunked-io = <32>;
 144                         };
 145                 };
 146         };
 147
 148         pinctrl {
 149                 compatible = "ralink,rt2880-pinmux";
 150                 pinctrl-names = "default";
 151                 pinctrl-0 = <&state_default>;
 152
 153                 state_default: pinctrl0 {
 154                 };
 155
 156                 spi_pins: spi {
 157                         spi {
 158                                 ralink,group = "spi";
 159                                 ralink,function = "spi";
 160                         };
 161                 };
 162
 163                 i2c_pins: i2c {
 164                         i2c {
 165                                 ralink,group = "i2c";
 166                                 ralink,function = "i2c";
 167                         };
 168                 };
 169
 170                 uart1_pins: uart1 {
 171                         uart1 {
 172                                 ralink,group = "uart1";
 173                                 ralink,function = "uart1";
 174                         };
 175                 };
 176
 177                 uart2_pins: uart2 {
 178                         uart2 {
 179                                 ralink,group = "uart2";
 180                                 ralink,function = "uart2";
 181                         };
 182                 };
 183
 184                 uart3_pins: uart3 {
 185                         uart3 {
 186                                 ralink,group = "uart3";
 187                                 ralink,function = "uart3";
 188                         };
 189                 };
 190
 191                 rgmii1_pins: rgmii1 {
 192                         rgmii1 {
 193                                 ralink,group = "rgmii1";
 194                                 ralink,function = "rgmii1";
 195                         };
 196                 };
 197
 198                 rgmii2_pins: rgmii2 {
 199                         rgmii2 {
 200                                 ralink,group = "rgmii2";
 201                                 ralink,function = "rgmii2";
 202                         };
 203                 };
 204
 205                 mdio_pins: mdio {
 206                         mdio {
 207                                 ralink,group = "mdio";
 208                                 ralink,function = "mdio";
 209                         };
 210                 };
 211
 212                 pcie_pins: pcie {
 213                         pcie {
 214                                 ralink,group = "pcie";
 215                                 ralink,function = "pcie rst";
 216                         };
 217                 };
 218
 219                 nand_pins: nand {
 220                         spi-nand {
 221                                 ralink,group = "spi";
 222                                 ralink,function = "nand1";
 223                         };
 224
 225                         sdhci-nand {
 226                                 ralink,group = "sdhci";
 227                                 ralink,function = "nand2";
 228                         };
 229                 };
 230
 231                 sdhci_pins: sdhci {
 232                         sdhci {
 233                                 ralink,group = "sdhci";
 234                                 ralink,function = "sdhci";
 235                         };
 236                 };
 237         };
 238
 239         rstctrl: rstctrl {
 240                 compatible = "ralink,rt2880-reset";
 241                 #reset-cells = <1>;
 242         };
 243
 244         sdhci@1E130000 {
 245                 compatible = "ralink,mt7620-sdhci";
 246                 reg = <0x1E130000 0x4000>;
 247
 248                 interrupt-parent = <&gic>;
 249                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 250         };
 251
 252         xhci@1E1C0000 {
 253                 status = "okay";
 254
 255                 compatible = "mediatek,mt8173-xhci";
 256                 reg = <0x1e1c0000 0x1000
 257                        0x1e1d0700 0x0100>;
 258
 259                 clocks = <&sysclock>;
 260                 clock-names = "sys_ck";
 261
 262                 interrupt-parent = <&gic>;
 263                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 264         };
 265
 266         gic: interrupt-controller@1fbc0000 {
 267                 compatible = "mti,gic";
 268                 reg = <0x1fbc0000 0x2000>;
 269
 270                 interrupt-controller;
 271                 #interrupt-cells = <3>;
 272
 273                 mti,reserved-cpu-vectors = <7>;
 274
 275                 timer {
 276                         compatible = "mti,gic-timer";
 277                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 278                         clocks = <&cpuclock>;
 279                 };
 280         };
 281
 282         nand@1e003000 {
 283                 status = "disabled";
 284
 285                 compatible = "mtk,mt7621-nand";
 286                 bank-width = <2>;
 287                 reg = <0x1e003000 0x800
 288                         0x1e003800 0x800>;
 289                 #address-cells = <1>;
 290                 #size-cells = <1>;
 291         };
 292
 293         ethernet@1e100000 {
 294                 compatible = "mediatek,mt7621-eth";
 295                 reg = <0x1e100000 0x10000>;
 296
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299
 300                 resets = <&rstctrl 6 &rstctrl 23>;
 301                 reset-names = "fe", "eth";
 302
 303                 interrupt-parent = <&gic>;
 304                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 305
 306                 mediatek,switch = <&gsw>;
 307
 308                 mdio-bus {
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311
 312                         phy1f: ethernet-phy@1f {
 313                                 reg = <0x1f>;
 314                                 phy-mode = "rgmii";
 315                         };
 316                 };
 317         };
 318
 319         gsw: gsw@1e110000 {
 320                 compatible = "mediatek,mt7621-gsw";
 321                 reg = <0x1e110000 0x8000>;
 322                 interrupt-parent = <&gic>;
 323                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 324         };
 325
 326         pcie@1e140000 {
 327                 compatible = "mediatek,mt7621-pci";
 328                 reg = <0x1e140000 0x100
 329                         0x1e142000 0x100>;
 330
 331                 #address-cells = <3>;
 332                 #size-cells = <2>;
 333
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&pcie_pins>;
 336
 337                 device_type = "pci";
 338
 339                 bus-range = <0 255>;
 340                 ranges = <
 341                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 342                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 343                 >;
 344
 345                 interrupt-parent = <&gic>;
 346                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 347                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 348                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 349
 350                 status = "okay";
 351
 352                 pcie0 {
 353                         reg = <0x0000 0 0 0 0>;
 354
 355                         #address-cells = <3>;
 356                         #size-cells = <2>;
 357
 358                         device_type = "pci";
 359                 };
 360
 361                 pcie1 {
 362                         reg = <0x0800 0 0 0 0>;
 363
 364                         #address-cells = <3>;
 365                         #size-cells = <2>;
 366
 367                         device_type = "pci";
 368                 };
 369
 370                 pcie2 {
 371                         reg = <0x1000 0 0 0 0>;
 372
 373                         #address-cells = <3>;
 374                         #size-cells = <2>;
 375
 376                         device_type = "pci";
 377                 };
 378         };
 379 };