target/linux/pxa-2.6/patches/000-cpufreq.patch

   1 diff -Nurbw linux-2.6.17/arch/arm/Kconfig linux-2.6.17-patched/arch/arm/Kconfig
   2 --- linux-2.6.17/arch/arm/Kconfig       2006-06-17 18:49:35.000000000 -0700
   3 +++ linux-2.6.17-patched/arch/arm/Kconfig       2006-09-21 14:57:02.000000000 -0700
   4 @@ -656,7 +656,7 @@
   5
   6  endmenu
   7
   8 -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1)
   9 +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1 || ARCH_PXA)
  10
  11  menu "CPU Frequency scaling"
  12
  13 @@ -685,6 +685,13 @@
  14
  15  endmenu
  16
  17 +config CPU_FREQ_PXA
  18 +       bool
  19 +       depends on CPU_FREQ && ARCH_PXA
  20 +       default y
  21 +       select CPU_FREQ_DEFAULT_GOV_USERSPACE
  22 +       select CPU_FREQ_TABLE
  23 +
  24  endif
  25
  26  menu "Floating point emulation"
  27 diff -Nurbw linux-2.6.17/arch/arm/mach-pxa/cpu-pxa.c linux-2.6.17-patched/arch/arm/mach-pxa/cpu-pxa.c
  28 --- linux-2.6.17/arch/arm/mach-pxa/cpu-pxa.c    1969-12-31 16:00:00.000000000 -0800
  29 +++ linux-2.6.17-patched/arch/arm/mach-pxa/cpu-pxa.c    2006-09-21 14:57:02.000000000 -0700
  30 @@ -0,0 +1,324 @@
  31 +/*
  32 + *  linux/arch/arm/mach-pxa/cpu-pxa.c
  33 + *
  34 + *  Copyright (C) 2002,2003 Intrinsyc Software
  35 + *
  36 + * This program is free software; you can redistribute it and/or modify
  37 + * it under the terms of the GNU General Public License as published by
  38 + * the Free Software Foundation; either version 2 of the License, or
  39 + * (at your option) any later version.
  40 + *
  41 + * This program is distributed in the hope that it will be useful,
  42 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  43 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  44 + * GNU General Public License for more details.
  45 + *
  46 + * You should have received a copy of the GNU General Public License
  47 + * along with this program; if not, write to the Free Software
  48 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  49 + *
  50 + * History:
  51 + *   31-Jul-2002 : Initial version [FB]
  52 + *   29-Jan-2003 : added PXA255 support [FB]
  53 + *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
  54 + *
  55 + * Note:
  56 + *   This driver may change the memory bus clock rate, but will not do any
  57 + *   platform specific access timing changes... for example if you have flash
  58 + *   memory connected to CS0, you will need to register a platform specific
  59 + *   notifier which will adjust the memory access strobes to maintain a
  60 + *   minimum strobe width.
  61 + *
  62 + */
  63 +
  64 +#include <linux/kernel.h>
  65 +#include <linux/module.h>
  66 +#include <linux/sched.h>
  67 +#include <linux/init.h>
  68 +#include <linux/cpufreq.h>
  69 +
  70 +#include <asm/hardware.h>
  71 +#include <asm/arch/pxa-regs.h>
  72 +
  73 +#undef DEBUG
  74 +
  75 +#ifdef DEBUG
  76 +  static unsigned int freq_debug = DEBUG;
  77 +  module_param(freq_debug, int, 0);
  78 +  MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
  79 +#else
  80 +  #define freq_debug  0
  81 +#endif
  82 +
  83 +typedef struct
  84 +{
  85 +    unsigned int khz;
  86 +    unsigned int membus;
  87 +    unsigned int cccr;
  88 +    unsigned int div2;
  89 +} pxa_freqs_t;
  90 +
  91 +/* Define the refresh period in mSec for the SDRAM and the number of rows */
  92 +#define SDRAM_TREF          64      /* standard 64ms SDRAM */
  93 +#define SDRAM_ROWS          2048    /* 64MB=8192 32MB=4096 */
  94 +#define MDREFR_DRI(x)       ((x*SDRAM_TREF)/(SDRAM_ROWS*32))
  95 +
  96 +#define CCLKCFG_TURBO       0x1
  97 +#define CCLKCFG_FCS         0x2
  98 +#define PXA25x_MIN_FREQ     99533
  99 +#define PXA25x_MAX_FREQ     530842
 100 +#define MDREFR_DB2_MASK     (MDREFR_K2DB2 | MDREFR_K1DB2)
 101 +#define MDREFR_DRI_MASK     0xFFF
 102 +
 103 +
 104 +/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
 105 +static pxa_freqs_t pxa255_run_freqs[] =
 106 +{
 107 +    /* CPU   MEMBUS  CCCR  DIV2*/
 108 +    { 99533,  99533, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50,  SDRAM=50 */
 109 +    {132710, 132710, 0x123, 1}, /* run=133, turbo=133, PXbus=66,  SDRAM=66 */
 110 +    {199066,  99533, 0x141, 0}, /* run=199, turbo=199, PXbus=99,  SDRAM=99 */
 111 +    {265421, 132710, 0x143, 0}, /* run=265, turbo=265, PXbus=133, SDRAM=133 */
 112 +    {331776, 165888, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
 113 +    {398131,  99533, 0x161, 0}, /* run=398, turbo=398, PXbus=99,  SDRAM=99 */
 114 +    {398131, 132710, 0x1c3, 0}, /* run=265, turbo=398, PXbus=133, SDRAM=133 */
 115 +    {530842, 132710, 0x163, 0}, /* run=531, turbo=531, PXbus=133, SDRAM=133 */
 116 +    {0,}
 117 +};
 118 +#define NUM_RUN_FREQS (sizeof(pxa255_run_freqs)/sizeof(pxa_freqs_t))
 119 +
 120 +static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
 121 +
 122 +/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
 123 +static pxa_freqs_t pxa255_turbo_freqs[] =
 124 +{
 125 +    /* CPU   MEMBUS  CCCR  DIV2*/
 126 +    { 99533, 99533,  0x121, 1}, /* run=99,  turbo= 99, PXbus=99, SDRAM=50 */
 127 +    {149299, 99533,  0x1a1, 0}, /* run=99,  turbo=149, PXbus=99, SDRAM=99 */
 128 +    {199066, 99533,  0x221, 0}, /* run=99,  turbo=199, PXbus=99, SDRAM=99 */
 129 +    {298598, 99533,  0x321, 0}, /* run=99,  turbo=299, PXbus=99, SDRAM=99 */
 130 +    {398131, 99533,  0x241, 1}, /* run=199, turbo=398, PXbus=99, SDRAM=50 */
 131 +    {0,}
 132 +};
 133 +#define NUM_TURBO_FREQS (sizeof(pxa255_turbo_freqs)/sizeof(pxa_freqs_t))
 134 +
 135 +static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
 136 +
 137 +extern unsigned get_clk_frequency_khz(int info);
 138 +
 139 +/* find a valid frequency point */
 140 +static int pxa_verify_policy(struct cpufreq_policy *policy)
 141 +{
 142 +    int ret;
 143 +    struct cpufreq_frequency_table *pxa_freqs_table;
 144 +
 145 +    if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
 146 +        pxa_freqs_table = pxa255_run_freq_table;
 147 +    } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
 148 +        pxa_freqs_table = pxa255_turbo_freq_table;
 149 +    } else {
 150 +        printk("CPU PXA: Unknown policy found. "
 151 +               "Using CPUFREQ_POLICY_PERFORMANCE\n");
 152 +        pxa_freqs_table = pxa255_run_freq_table;
 153 +    }
 154 +       ret=cpufreq_frequency_table_verify(policy, pxa_freqs_table);
 155 +
 156 +    if(freq_debug) {
 157 +        printk("Verified CPU policy: %dKhz min to %dKhz max\n",
 158 +            policy->min, policy->max);
 159 +    }
 160 +
 161 +    return ret;
 162 +}
 163 +
 164 +static int pxa_set_target(struct cpufreq_policy *policy,
 165 +                 unsigned int target_freq,
 166 +                 unsigned int relation)
 167 +{
 168 +    int idx;
 169 +    cpumask_t cpus_allowed;
 170 +    int cpu = policy->cpu;
 171 +    struct cpufreq_freqs freqs;
 172 +    pxa_freqs_t *pxa_freq_settings;
 173 +    struct cpufreq_frequency_table *pxa_freqs_table;
 174 +    unsigned long flags;
 175 +    unsigned int unused;
 176 +    unsigned int preset_mdrefr, postset_mdrefr;
 177 +    void *ramstart;
 178 +
 179 +    /*
 180 +     * Save this threads cpus_allowed mask.
 181 +     */
 182 +    cpus_allowed = current->cpus_allowed;
 183 +
 184 +    /*
 185 +     * Bind to the specified CPU.  When this call returns,
 186 +     * we should be running on the right CPU.
 187 +     */
 188 +    set_cpus_allowed(current, cpumask_of_cpu(cpu));
 189 +    BUG_ON(cpu != smp_processor_id());
 190 +
 191 +    /* Get the current policy */
 192 +    if(policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
 193 +        pxa_freq_settings = pxa255_run_freqs;
 194 +        pxa_freqs_table   = pxa255_run_freq_table;
 195 +    }else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
 196 +        pxa_freq_settings = pxa255_turbo_freqs;
 197 +        pxa_freqs_table   = pxa255_turbo_freq_table;
 198 +    }else {
 199 +        printk("CPU PXA: Unknown policy found. "
 200 +               "Using CPUFREQ_POLICY_PERFORMANCE\n");
 201 +        pxa_freq_settings = pxa255_run_freqs;
 202 +        pxa_freqs_table   = pxa255_run_freq_table;
 203 +    }
 204 +
 205 +    /* Lookup the next frequency */
 206 +       if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
 207 +                                          target_freq, relation, &idx)) {
 208 +               return -EINVAL;
 209 +    }
 210 +
 211 +    freqs.old = policy->cur;
 212 +    freqs.new = pxa_freq_settings[idx].khz;
 213 +    freqs.cpu = policy->cpu;
 214 +    if(freq_debug) {
 215 +        printk(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
 216 +            freqs.new/1000, (pxa_freq_settings[idx].div2) ?
 217 +            (pxa_freq_settings[idx].membus/2000) :
 218 +            (pxa_freq_settings[idx].membus/1000));
 219 +    }
 220 +
 221 +    ramstart = phys_to_virt(0xa0000000);
 222 +
 223 +    /*
 224 +     * Tell everyone what we're about to do...
 225 +     * you should add a notify client with any platform specific
 226 +     * Vcc changing capability
 227 +     */
 228 +    cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 229 +
 230 +    /* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
 231 +     * we need to preset the smaller DRI before the change.  If we're speeding
 232 +     * up we need to set the larger DRI value after the change.
 233 +     */
 234 +    preset_mdrefr = postset_mdrefr = MDREFR;
 235 +    if((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
 236 +        preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
 237 +                        MDREFR_DRI(pxa_freq_settings[idx].membus);
 238 +    }
 239 +    postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
 240 +                    MDREFR_DRI(pxa_freq_settings[idx].membus);
 241 +
 242 +    /* If we're dividing the memory clock by two for the SDRAM clock, this
 243 +     * must be set prior to the change.  Clearing the divide must be done
 244 +     * after the change.
 245 +     */
 246 +    if(pxa_freq_settings[idx].div2) {
 247 +        preset_mdrefr  |= MDREFR_DB2_MASK;
 248 +        postset_mdrefr |= MDREFR_DB2_MASK;
 249 +    } else {
 250 +        postset_mdrefr &= ~MDREFR_DB2_MASK;
 251 +    }
 252 +
 253 +    local_irq_save(flags);
 254 +
 255 +    /* Set new the CCCR */
 256 +    CCCR = pxa_freq_settings[idx].cccr;
 257 +
 258 +    __asm__ __volatile__("                                  \
 259 +        ldr r4, [%1] ;  /* load MDREFR */                   \
 260 +        b   2f ;                                            \
 261 +        .align  5 ;                                         \
 262 +1:                                                          \
 263 +        str %4, [%1] ;          /* preset the MDREFR */     \
 264 +        mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */  \
 265 +        str %5, [%1] ;          /* postset the MDREFR */    \
 266 +                                                            \
 267 +        b   3f       ;                                      \
 268 +2:      b   1b       ;                                      \
 269 +3:      nop          ;                                      \
 270 +        "
 271 +        : "=&r" (unused)
 272 +        : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), \
 273 +          "r" (preset_mdrefr), "r" (postset_mdrefr)
 274 +        : "r4", "r5");
 275 +    local_irq_restore(flags);
 276 +
 277 +    /*
 278 +     * Restore the CPUs allowed mask.
 279 +     */
 280 +    set_cpus_allowed(current, cpus_allowed);
 281 +
 282 +    /*
 283 +     * Tell everyone what we've just done...
 284 +     * you should add a notify client with any platform specific
 285 +     * SDRAM refresh timer adjustments
 286 +     */
 287 +    cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 288 +
 289 +    return 0;
 290 +}
 291 +
 292 +static int pxa_cpufreq_init(struct cpufreq_policy *policy)
 293 +{
 294 +    cpumask_t cpus_allowed;
 295 +    unsigned int cpu = policy->cpu;
 296 +    int i;
 297 +
 298 +       cpus_allowed = current->cpus_allowed;
 299 +
 300 +       set_cpus_allowed(current, cpumask_of_cpu(cpu));
 301 +       BUG_ON(cpu != smp_processor_id());
 302 +
 303 +    /* set default policy and cpuinfo */
 304 +    policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 305 +    policy->policy = CPUFREQ_POLICY_PERFORMANCE;
 306 +    policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
 307 +    policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
 308 +    policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
 309 +    policy->cur = get_clk_frequency_khz(0); /* current freq */
 310 +    policy->min = policy->max = policy->cur;
 311 +
 312 +    /* Generate the run cpufreq_frequency_table struct */
 313 +    for(i=0;i<NUM_RUN_FREQS;i++) {
 314 +        pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
 315 +        pxa255_run_freq_table[i].index = i;
 316 +    }
 317 +    pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
 318 +    /* Generate the turbo cpufreq_frequency_table struct */
 319 +    for(i=0;i<NUM_TURBO_FREQS;i++) {
 320 +        pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
 321 +        pxa255_turbo_freq_table[i].index = i;
 322 +    }
 323 +    pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
 324 +
 325 +    set_cpus_allowed(current, cpus_allowed);
 326 +    printk(KERN_INFO "PXA CPU frequency change support initialized\n");
 327 +
 328 +    return 0;
 329 +}
 330 +
 331 +static struct cpufreq_driver pxa_cpufreq_driver = {
 332 +    .verify     = pxa_verify_policy,
 333 +    .target     = pxa_set_target,
 334 +    .init       = pxa_cpufreq_init,
 335 +    .name       = "PXA25x",
 336 +};
 337 +
 338 +static int __init pxa_cpu_init(void)
 339 +{
 340 +    return cpufreq_register_driver(&pxa_cpufreq_driver);
 341 +}
 342 +
 343 +static void __exit pxa_cpu_exit(void)
 344 +{
 345 +    cpufreq_unregister_driver(&pxa_cpufreq_driver);
 346 +}
 347 +
 348 +
 349 +MODULE_AUTHOR ("Intrinsyc Software Inc.");
 350 +MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
 351 +MODULE_LICENSE("GPL");
 352 +module_init(pxa_cpu_init);
 353 +module_exit(pxa_cpu_exit);
 354 +
 355 diff -Nurbw linux-2.6.17/arch/arm/mach-pxa/Makefile linux-2.6.17-patched/arch/arm/mach-pxa/Makefile
 356 --- linux-2.6.17/arch/arm/mach-pxa/Makefile     2006-09-21 15:11:33.000000000 -0700
 357 +++ linux-2.6.17-patched/arch/arm/mach-pxa/Makefile     2006-09-21 14:57:02.000000000 -0700
 358 @@ -30,5 +30,6 @@
 359  obj-$(CONFIG_PM) += pm.o sleep.o
 360  obj-$(CONFIG_PXA_SSP) += ssp.o
 361 +obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
 362
 363  ifeq ($(CONFIG_PXA27x),y)
 364  obj-$(CONFIG_PM) += standby.o
 365 diff -Nurbw linux-2.6.17/Documentation/cpu-freq/user-guide.txt linux-2.6.17-patched/Documentation/cpu-freq/user-guide.txt
 366 --- linux-2.6.17/Documentation/cpu-freq/user-guide.txt  2006-06-17 18:49:35.000000000 -0700
 367 +++ linux-2.6.17-patched/Documentation/cpu-freq/user-guide.txt  2006-09-21 14:57:02.000000000 -0700
 368 @@ -18,7 +18,7 @@
 369  Contents:
 370  ---------
 371  1. Supported Architectures and Processors
 372 -1.1 ARM
 373 +1.1 ARM, PXA
 374  1.2 x86
 375  1.3 sparc64
 376  1.4 ppc
 377 @@ -37,14 +37,15 @@
 378  1. Supported Architectures and Processors
 379  =========================================
 380
 381 -1.1 ARM
 382 --------
 383 +1.1 ARM, PXA
 384 +------------
 385
 386  The following ARM processors are supported by cpufreq:
 387
 388  ARM Integrator
 389  ARM-SA1100
 390  ARM-SA1110
 391 +Intel PXA
 392
 393
 394  1.2 x86
 395 diff -Nurbw linux-2.6.17/drivers/cpufreq/Kconfig linux-2.6.17-patched/drivers/cpufreq/Kconfig
 396 --- linux-2.6.17/drivers/cpufreq/Kconfig        2006-06-17 18:49:35.000000000 -0700
 397 +++ linux-2.6.17-patched/drivers/cpufreq/Kconfig        2006-09-21 15:06:12.000000000 -0700
 398 @@ -46,13 +46,9 @@
 399           This will show detail CPU frequency translation table in sysfs file
 400           system
 401
 402 -# Note that it is not currently possible to set the other governors (such as ondemand)
 403 -# as the default, since if they fail to initialise, cpufreq will be
 404 -# left in an undefined state.
 405 -
 406  choice
 407         prompt "Default CPUFreq governor"
 408 -       default CPU_FREQ_DEFAULT_GOV_USERSPACE if CPU_FREQ_SA1100 || CPU_FREQ_SA1110
 409 +       default CPU_FREQ_DEFAULT_GOV_USERSPACE if CPU_FREQ_SA1100 || CPU_FREQ_SA1110 || CPU_FREQ_PXA
 410         default CPU_FREQ_DEFAULT_GOV_PERFORMANCE
 411         help
 412           This option sets which CPUFreq governor shall be loaded at
 413 @@ -66,6 +62,14 @@
 414           the frequency statically to the highest frequency supported by
 415           the CPU.
 416
 417 +config CPU_FREQ_DEFAULT_GOV_POWERSAVE
 418 +       bool "powersave"
 419 +       select CPU_FREQ_GOV_POWERSAVE
 420 +       help
 421 +         Use the CPUFreq governor 'powersave' as default. This sets
 422 +         the frequency statically to the lowest frequency supported by
 423 +         the CPU.
 424 +
 425  config CPU_FREQ_DEFAULT_GOV_USERSPACE
 426         bool "userspace"
 427         select CPU_FREQ_GOV_USERSPACE
 428 @@ -75,6 +79,23 @@
 429           program shall be able to set the CPU dynamically without having
 430           to enable the userspace governor manually.
 431
 432 +config CPU_FREQ_DEFAULT_GOV_ONDEMAND
 433 +       bool "ondemand"
 434 +       select CPU_FREQ_GOV_ONDEMAND
 435 +       help
 436 +         Use the CPUFreq governor 'ondemand' as default.  This sets
 437 +         the frequency dynamically based on CPU load, throttling up
 438 +         and down as necessary.
 439 +
 440 +config CPU_FREQ_DEFAULT_GOV_CONSERVATIVE
 441 +       bool "conservative"
 442 +       select CPU_FREQ_GOV_CONSERVATIVE
 443 +       help
 444 +         Use the CPUFreq governor 'conservative' as default. This sets
 445 +         the frequency dynamically based on CPU load, throttling up
 446 +         and down as necessary. The frequency is gracefully increased
 447 +         and decreased rather than jumping to 100% when speed is required.
 448 +
 449  endchoice
 450
 451  config CPU_FREQ_GOV_PERFORMANCE
 452 diff -Nurbw linux-2.6.17/include/linux/cpufreq.h linux-2.6.17-patched/include/linux/cpufreq.h
 453 --- linux-2.6.17/include/linux/cpufreq.h        2006-06-17 18:49:35.000000000 -0700
 454 +++ linux-2.6.17-patched/include/linux/cpufreq.h        2006-09-21 15:08:35.000000000 -0700
 455 @@ -276,9 +276,18 @@
 456  #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
 457  extern struct cpufreq_governor cpufreq_gov_performance;
 458  #define CPUFREQ_DEFAULT_GOVERNOR       &cpufreq_gov_performance
 459 +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE)
 460 +extern struct cpufreq_governor cpufreq_gov_powersave;
 461 +#define CPUFREQ_DEFAULT_GOVERNOR       &cpufreq_gov_powersave
 462  #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE)
 463  extern struct cpufreq_governor cpufreq_gov_userspace;
 464  #define CPUFREQ_DEFAULT_GOVERNOR       &cpufreq_gov_userspace
 465 +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND)
 466 +extern struct cpufreq_governor cpufreq_gov_ondemand;
 467 +#define CPUFREQ_DEFAULT_GOVERNOR       &cpufreq_gov_ondemand;
 468 +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE)
 469 +extern struct cpufreq_governor cpufreq_gov_conservative;
 470 +#define CPUFREQ_DEFAULT_GOVERNOR        &cpufreq_gov_conservative;
 471  #endif
 472
 473
 474 diff -Nubrw --exclude='.*.o.cmd' linux-2.6.17/drivers/cpufreq/cpufreq_conservative.c linux-2.6.17-patched/drivers/cpufreq/cpufreq_conservative.c
 475 --- linux-2.6.17/drivers/cpufreq/cpufreq_conservative.c 2006-09-21 15:26:46.000000000 -0700
 476 +++ linux-2.6.17-patched/drivers/cpufreq/cpufreq_conservative.c 2006-06-17 18:49:35.000000000 -0700
 477 @@ -529,7 +529,7 @@
 478         return 0;
 479  }
 480
 481 -static struct cpufreq_governor cpufreq_gov_dbs = {
 482 +struct cpufreq_governor cpufreq_gov_conservative = {
 483         .name           = "conservative",
 484         .governor       = cpufreq_governor_dbs,
 485         .owner          = THIS_MODULE,
 486 @@ -537,7 +537,7 @@
 487
 488  static int __init cpufreq_gov_dbs_init(void)
 489  {
 490 -       return cpufreq_register_governor(&cpufreq_gov_dbs);
 491 +       return cpufreq_register_governor(&cpufreq_gov_conservative);
 492  }
 493
 494  static void __exit cpufreq_gov_dbs_exit(void)
 495 @@ -545,7 +545,7 @@
 496         /* Make sure that the scheduled work is indeed not running */
 497         flush_scheduled_work();
 498
 499 -       cpufreq_unregister_governor(&cpufreq_gov_dbs);
 500 +       cpufreq_unregister_governor(&cpufreq_gov_conservative);
 501  }
 502
 503
 504 diff -Nubrw --exclude='.*.o.cmd' linux-2.6.17/drivers/cpufreq/cpufreq_ondemand.c linux-2.6.17-patched/drivers/cpufreq/cpufreq_ondemand.c
 505 --- linux-2.6.17/drivers/cpufreq/cpufreq_ondemand.c     2006-06-17 18:49:35.000000000 -0700
 506 +++ linux-2.6.17-patched/drivers/cpufreq/cpufreq_ondemand.c     2006-09-27 14:00:15.000000000 -0700
 507 @@ -484,7 +484,7 @@
 508         return 0;
 509  }
 510
 511 -static struct cpufreq_governor cpufreq_gov_dbs = {
 512 +struct cpufreq_governor cpufreq_gov_ondemand = {
 513         .name           = "ondemand",
 514         .governor       = cpufreq_governor_dbs,
 515         .owner          = THIS_MODULE,
 516 @@ -492,7 +492,7 @@
 517
 518  static int __init cpufreq_gov_dbs_init(void)
 519  {
 520 -       return cpufreq_register_governor(&cpufreq_gov_dbs);
 521 +       return cpufreq_register_governor(&cpufreq_gov_ondemand);
 522  }
 523
 524  static void __exit cpufreq_gov_dbs_exit(void)
 525 @@ -504,7 +504,7 @@
 526                 destroy_workqueue(dbs_workq);
 527         }
 528
 529 -       cpufreq_unregister_governor(&cpufreq_gov_dbs);
 530 +       cpufreq_unregister_governor(&cpufreq_gov_ondemand);
 531  }
 532
 533