2 * PCIe driver for PLX NAS782X SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/mbus.h>
14 #include <linux/slab.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/reset.h>
25 #include <mach/iomap.h>
26 #include <mach/hardware.h>
27 #include <mach/utils.h>
29 #define VERSION_ID_MAGIC 0x082510b5
30 #define LINK_UP_TIMEOUT_SECONDS 1
31 #define NUM_CONTROLLERS 1
34 PCIE_DEVICE_TYPE_MASK = 0x0F,
35 PCIE_DEVICE_TYPE_ENDPOINT = 0,
36 PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
37 PCIE_DEVICE_TYPE_ROOT = 4,
40 PCIE_READY_ENTR_L23 = BIT(9),
41 PCIE_LINK_UP = BIT(11),
42 PCIE_OBTRANS = BIT(12),
46 HCSL_BIAS_ON = BIT(0),
47 HCSL_PCIE_EN = BIT(1),
48 HCSL_PCIEA_EN = BIT(2),
49 HCSL_PCIEB_EN = BIT(3),
53 /* pcie phy reg offset */
56 /* phy data reg bits */
62 /* core config registers */
64 PCI_CONFIG_VERSION_DEVICEID = 0,
65 PCI_CONFIG_COMMAND_STATUS = 4,
68 /* inbound config registers */
70 IB_ADDR_XLATE_ENABLE = 0xFC,
73 ENABLE_IN_ADDR_TRANS = BIT(0),
76 /* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
78 PCIE_POM0_MEM_ADDR = 0,
79 PCIE_POM1_MEM_ADDR = 4,
80 PCIE_IN0_MEM_ADDR = 8,
81 PCIE_IN1_MEM_ADDR = 12,
83 PCIE_IN_CFG0_ADDR = 20,
84 PCIE_IN_CFG1_ADDR = 24,
85 PCIE_IN_MSG_ADDR = 28,
86 PCIE_IN0_MEM_LIMIT = 32,
87 PCIE_IN1_MEM_LIMIT = 36,
88 PCIE_IN_IO_LIMIT = 40,
89 PCIE_IN_CFG0_LIMIT = 44,
90 PCIE_IN_CFG1_LIMIT = 48,
91 PCIE_IN_MSG_LIMIT = 52,
92 PCIE_AHB_SLAVE_CTRL = 56,
94 PCIE_SLAVE_BE_SHIFT = 22,
97 #define ADDR_VAL(val) ((val) & 0xFFFF)
98 #define DATA_VAL(val) ((val) & 0xFFFF)
100 #define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
101 #define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
103 struct oxnas_pcie_shared {
104 /* seems all access are serialized, no lock required */
108 /* Structure representing one PCIe interfaces */
110 void __iomem *cfgbase;
112 void __iomem *inbound;
113 void __iomem *outbound;
114 void __iomem *pcie_ctrl;
117 struct platform_device *pdev;
120 struct resource pre_mem; /* prefetchable */
121 struct resource non_mem; /* non-prefetchable */
122 struct resource busn; /* max available bus numbers */
123 int card_reset; /* gpio pin, optional */
124 unsigned hcsl_en; /* hcsl pci enable bit */
126 struct clk *busclk; /* for pcie bus, actually the PLLB */
127 void *private_data[1];
131 static struct oxnas_pcie_shared pcie_shared = {
135 static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
137 return sys->private_data;
141 static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
143 oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL,
144 PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
148 static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
152 /* Poll for PCIE link up */
153 end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
154 while (!time_after(jiffies, end)) {
155 if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP)
161 static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
163 /* We won't have any inbound address translation. This allows PCI
164 * devices to access anywhere in the AHB address map. Might be regarded
165 * as a bit dangerous, but let's get things working before we worry
168 oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
169 ENABLE_IN_ADDR_TRANS);
173 * Program outbound translation windows
175 * Outbound window is what is referred to as "PCI client" region in HRM
177 * Could use the larger alternative address space to get >>64M regions
178 * for graphics cards etc., but will not bother at this point.
180 * IP bug means that AMBA window size must be a power of 2
182 * Set mem0 window for first 16MB of outbound window non-prefetchable
183 * Set mem1 window for second 16MB of outbound window prefetchable
184 * Set io window for next 16MB of outbound window
185 * Set cfg0 for final 1MB of outbound window
187 * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
188 * 820 that would need them
190 * Probably ideally want no offset between mem0 window start as seen by
191 * ARM and as seen on PCI bus and get Linux to assign memory regions to
192 * PCI devices using the same "PCI client" region start address as seen
196 /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
197 writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR);
198 writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT);
199 writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR);
201 /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
202 writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR);
203 writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT);
204 writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR);
206 /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
207 writel_relaxed(pcie->io.start, pcie->outbound + PCIE_IN_IO_ADDR);
208 writel_relaxed(pcie->io.end, pcie->outbound + PCIE_IN_IO_LIMIT);
210 /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
211 writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR);
212 writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT);
215 /* Enable outbound address translation */
216 oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS);
220 * Program PCIe command register for core to:
221 * enable memory space
225 writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
230 static unsigned oxnas_pcie_cfg_to_offset(
231 struct pci_sys_data *sys,
232 unsigned char bus_number,
236 unsigned int function = PCI_FUNC(devfn);
237 unsigned int slot = PCI_SLOT(devfn);
238 unsigned char bus_number_offset;
240 bus_number_offset = bus_number - sys->busnr;
243 * We'll assume for now that the offset, function, slot, bus encoding
244 * should map onto linear, contiguous addresses in PCIe config space,
245 * albeit that the majority will be unused as only slot 0 is valid for
246 * any PCIe bus and most devices have only function 0
248 * Could be that PCIe in fact works by not encoding the slot number into
249 * the config space address as it's known that only slot 0 is valid.
250 * We'll have to experiment if/when we get a PCIe switch connected to
253 return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
257 /* PCI configuration space write function */
258 static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
259 int where, int size, u32 val)
262 struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
267 /* Only a single device per bus for PCIe point-to-point links */
268 if (PCI_SLOT(devfn) > 0)
269 return PCIBIOS_DEVICE_NOT_FOUND;
272 return PCIBIOS_DEVICE_NOT_FOUND;
274 offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
277 value = val << (8 * (where & 3));
278 lanes = (0xf >> (4-size)) << (where & 3);
279 /* it race with mem and io write, but the possibility is low, normally
280 * all config writes happens at driver initialize stage, wont interleave
282 * and many pcie cards use dword (4bytes) access mem/io access only,
283 * so not bother to copy that ugly work-around now. */
284 spin_lock_irqsave(&pcie->lock, flags);
285 set_out_lanes(pcie, lanes);
286 writel_relaxed(value, pcie->cfgbase + offset);
287 set_out_lanes(pcie, 0xf);
288 spin_unlock_irqrestore(&pcie->lock, flags);
290 return PCIBIOS_SUCCESSFUL;
293 /* PCI configuration space read function */
294 static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
297 struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
300 u32 left_bytes, right_bytes;
302 /* Only a single device per bus for PCIe point-to-point links */
303 if (PCI_SLOT(devfn) > 0) {
305 return PCIBIOS_DEVICE_NOT_FOUND;
308 if (!pcie->haslink) {
310 return PCIBIOS_DEVICE_NOT_FOUND;
313 offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
315 value = readl_relaxed(pcie->cfgbase + offset);
316 left_bytes = where & 3;
317 right_bytes = 4 - left_bytes - size;
318 value <<= right_bytes * 8;
319 value >>= (left_bytes + right_bytes) * 8;
322 return PCIBIOS_SUCCESSFUL;
325 static struct pci_ops oxnas_pcie_ops = {
326 .read = oxnas_pcie_rd_conf,
327 .write = oxnas_pcie_wr_conf,
330 static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
332 struct oxnas_pcie *pcie = sys_to_pcie(sys);
334 pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
335 pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
336 pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
337 pci_add_resource(&sys->resources, &pcie->busn);
338 if (sys->busnr == 0) { /* default one */
339 sys->busnr = pcie->busn.start;
341 /* do not use devm_ioremap_resource, it does not like cfg resource */
342 pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
343 resource_size(&pcie->cfg));
347 oxnas_pcie_setup_hw(pcie);
352 static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
357 memset(&hw, 0, sizeof(hw));
358 for (i = 0; i < NUM_CONTROLLERS; i++)
359 pcie->private_data[i] = pcie;
361 hw.nr_controllers = NUM_CONTROLLERS;
362 /* I think use stack pointer is a bad idea though it is valid in this case */
363 hw.private_data = pcie->private_data;
364 hw.setup = oxnas_pcie_setup;
365 hw.map_irq = of_irq_parse_and_map_pci;
366 hw.ops = &oxnas_pcie_ops;
368 /* pass dev to maintain of tree, interrupt mapping rely on this */
369 pci_common_init_dev(dev, &hw);
372 void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
373 void __iomem *phybase)
375 struct reset_control *rstc;
378 /* generate clocks from HCSL buffers, shared parts */
379 writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL);
381 /* Ensure PCIe PHY is properly reset */
382 rstc = reset_control_get(&pdev->dev, "phy");
386 ret = reset_control_reset(rstc);
387 reset_control_put(rstc);
391 dev_err(&pdev->dev, "phy reset failed %d\n", ret);
395 /* Enable PCIe Pre-Emphasis: What these value means? */
397 writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
398 writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
399 writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
401 writel(ADDR_VAL(0x2004), phybase + PHY_ADDR);
402 writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA);
403 writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
406 static int oxnas_pcie_shared_init(struct platform_device *pdev)
408 if (++pcie_shared.refcount == 1) {
409 /* we are the first */
410 struct device_node *np = pdev->dev.of_node;
411 void __iomem *phy = of_iomap(np, 2);
413 --pcie_shared.refcount;
416 oxnas_pcie_init_shared_hw(pdev, phy);
425 /* maybe we will call it when enter low power state */
426 static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
428 if (--pcie_shared.refcount == 0) {
429 /* no cleanup needed */;
435 oxnas_pcie_map_registers(struct platform_device *pdev,
436 struct device_node *np,
437 struct oxnas_pcie *pcie)
439 struct resource regs;
441 u32 outbound_ctrl_offset;
442 u32 pcie_ctrl_offset;
444 /* 2 is reserved for shared phy */
445 ret = of_address_to_resource(np, 0, ®s);
448 pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
452 ret = of_address_to_resource(np, 1, ®s);
455 pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
460 if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
461 &outbound_ctrl_offset))
463 /* SYSCRTL is shared by too many drivers, so is mapped by board file */
464 pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset);
466 if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
469 pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset);
474 static int __init oxnas_pcie_init_res(struct platform_device *pdev,
475 struct oxnas_pcie *pcie,
476 struct device_node *np)
478 struct of_pci_range range;
479 struct of_pci_range_parser parser;
482 if (of_pci_range_parser_init(&parser, np))
485 /* Get the I/O and memory ranges from DT */
486 for_each_of_pci_range(&parser, &range) {
488 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
489 if (restype == IORESOURCE_IO) {
490 of_pci_range_to_resource(&range, np, &pcie->io);
491 pcie->io.name = "I/O";
493 if (restype == IORESOURCE_MEM) {
494 if (range.flags & IORESOURCE_PREFETCH) {
495 of_pci_range_to_resource(&range, np, &pcie->pre_mem);
496 pcie->pre_mem.name = "PRE MEM";
498 of_pci_range_to_resource(&range, np, &pcie->non_mem);
499 pcie->non_mem.name = "NON MEM";
504 of_pci_range_to_resource(&range, np, &pcie->cfg);
507 /* Get the bus range */
508 ret = of_pci_parse_bus_range(np, &pcie->busn);
511 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
516 pcie->card_reset = of_get_gpio(np, 0);
517 if (pcie->card_reset < 0)
518 dev_info(&pdev->dev, "card reset gpio pin not exists\n");
520 if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
523 pcie->clk = of_clk_get_by_name(np, "pcie");
524 if (IS_ERR(pcie->clk)) {
525 return PTR_ERR(pcie->clk);
528 pcie->busclk = of_clk_get_by_name(np, "busclk");
529 if (IS_ERR(pcie->busclk)) {
531 return PTR_ERR(pcie->busclk);
537 static void oxnas_pcie_init_hw(struct platform_device *pdev,
538 struct oxnas_pcie *pcie)
543 clk_prepare_enable(pcie->busclk);
545 /* reset PCIe cards use hard-wired gpio pin */
546 if (pcie->card_reset >= 0 &&
547 !gpio_direction_output(pcie->card_reset, 0)) {
550 /* must tri-state the pin to pull it up */
551 gpio_direction_input(pcie->card_reset);
556 oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en));
559 ret = device_reset(&pdev->dev);
561 dev_err(&pdev->dev, "core reset failed %d\n", ret);
565 /* Start PCIe core clocks */
566 clk_prepare_enable(pcie->clk);
568 version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
569 dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
571 if (version_id != VERSION_ID_MAGIC) {
572 dev_info(&pdev->dev, "PCIe controller not found\n");
577 /* allow entry to L23 state */
578 oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23);
580 /* Set PCIe core into RootCore mode */
581 oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK,
582 PCIE_DEVICE_TYPE_ROOT);
585 /* Bring up the PCI core */
586 oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM);
590 static int __init oxnas_pcie_probe(struct platform_device *pdev)
592 struct oxnas_pcie *pcie;
593 struct device_node *np = pdev->dev.of_node;
596 pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
603 spin_lock_init(&pcie->lock);
605 ret = oxnas_pcie_init_res(pdev, pcie, np);
608 if (pcie->card_reset >= 0) {
609 ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
610 dev_name(&pdev->dev));
612 dev_err(&pdev->dev, "cannot request gpio pin %d\n",
618 ret = oxnas_pcie_map_registers(pdev, np, pcie);
620 dev_err(&pdev->dev, "cannot map registers\n");
624 ret = oxnas_pcie_shared_init(pdev);
628 /* if hw not found, haslink cleared */
629 oxnas_pcie_init_hw(pdev, pcie);
631 if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
633 dev_info(&pdev->dev, "link up\n");
636 dev_info(&pdev->dev, "link down\n");
638 /* should we register our controller even when pcie->haslink is 0 ? */
639 /* register the controller with framework */
640 oxnas_pcie_enable(&pdev->dev, pcie);
645 if (pcie->card_reset)
646 gpio_free(pcie->card_reset);
651 static const struct of_device_id oxnas_pcie_of_match_table[] = {
652 { .compatible = "plxtech,nas782x-pcie", },
655 MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table);
657 static struct platform_driver oxnas_pcie_driver = {
659 .owner = THIS_MODULE,
660 .name = "oxnas-pcie",
662 of_match_ptr(oxnas_pcie_of_match_table),
666 static int __init oxnas_pcie_init(void)
668 return platform_driver_probe(&oxnas_pcie_driver,
672 subsys_initcall(oxnas_pcie_init);
674 MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>");
675 MODULE_DESCRIPTION("NAS782x PCIe driver");
676 MODULE_LICENSE("GPLv2");