1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/of_platform.h>
5 #include <linux/clocksource.h>
6 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
10 #include <linux/reset.h>
11 #include <linux/version.h>
12 #include <asm/mach-types.h>
13 #include <asm/mach/map.h>
14 #include <asm/mach/arch.h>
16 #include <mach/iomap.h>
17 #include <mach/hardware.h>
18 #include <mach/utils.h>
21 static struct map_desc ox820_io_desc[] __initdata = {
23 .virtual = (unsigned long)OXNAS_PERCPU_BASE_VA,
24 .pfn = __phys_to_pfn(OXNAS_PERCPU_BASE),
25 .length = OXNAS_PERCPU_SIZE,
29 .virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA,
30 .pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE),
31 .length = OXNAS_SYSCRTL_SIZE,
35 .virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA,
36 .pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE),
37 .length = OXNAS_SECCRTL_SIZE,
41 .virtual = (unsigned long)OXNAS_RPSA_BASE_VA,
42 .pfn = __phys_to_pfn(OXNAS_RPSA_BASE),
43 .length = OXNAS_RPSA_SIZE,
47 .virtual = (unsigned long)OXNAS_RPSC_BASE_VA,
48 .pfn = __phys_to_pfn(OXNAS_RPSC_BASE),
49 .length = OXNAS_RPSC_SIZE,
54 void __init ox820_map_common_io(void)
57 iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc));
60 static void __init ox820_dt_init(void)
64 ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
68 pr_err("of_platform_populate failed: %d\n", ret);
74 static void __init ox820_timer_init(void)
77 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,3,0)
78 clocksource_of_init();
84 void ox820_init_early(void)
89 void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd)
93 /* Assert reset to cores as per power on defaults
94 * Don't touch the DDR interface as things will come to an impromptu stop
95 * NB Possibly should be asserting reset for PLLB, but there are timing
96 * concerns here according to the docs */
97 value = BIT(SYS_CTRL_RST_COPRO) |
98 BIT(SYS_CTRL_RST_USBHS) |
99 BIT(SYS_CTRL_RST_USBHSPHYA) |
100 BIT(SYS_CTRL_RST_MACA) |
101 BIT(SYS_CTRL_RST_PCIEA) |
102 BIT(SYS_CTRL_RST_SGDMA) |
103 BIT(SYS_CTRL_RST_CIPHER) |
104 BIT(SYS_CTRL_RST_SATA) |
105 BIT(SYS_CTRL_RST_SATA_LINK) |
106 BIT(SYS_CTRL_RST_SATA_PHY) |
107 BIT(SYS_CTRL_RST_PCIEPHY) |
108 BIT(SYS_CTRL_RST_STATIC) |
109 BIT(SYS_CTRL_RST_UART1) |
110 BIT(SYS_CTRL_RST_UART2) |
111 BIT(SYS_CTRL_RST_MISC) |
112 BIT(SYS_CTRL_RST_I2S) |
113 BIT(SYS_CTRL_RST_SD) |
114 BIT(SYS_CTRL_RST_MACB) |
115 BIT(SYS_CTRL_RST_PCIEB) |
116 BIT(SYS_CTRL_RST_VIDEO) |
117 BIT(SYS_CTRL_RST_USBHSPHYB) |
118 BIT(SYS_CTRL_RST_USBDEV);
120 writel(value, SYS_CTRL_RST_SET_CTRL);
122 /* Release reset to cores as per power on defaults */
123 writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
125 /* Disable clocks to cores as per power-on defaults - must leave DDR
126 * related clocks enabled otherwise we'll stop rather abruptly. */
128 BIT(SYS_CTRL_CLK_COPRO) |
129 BIT(SYS_CTRL_CLK_DMA) |
130 BIT(SYS_CTRL_CLK_CIPHER) |
131 BIT(SYS_CTRL_CLK_SD) |
132 BIT(SYS_CTRL_CLK_SATA) |
133 BIT(SYS_CTRL_CLK_I2S) |
134 BIT(SYS_CTRL_CLK_USBHS) |
135 BIT(SYS_CTRL_CLK_MAC) |
136 BIT(SYS_CTRL_CLK_PCIEA) |
137 BIT(SYS_CTRL_CLK_STATIC) |
138 BIT(SYS_CTRL_CLK_MACB) |
139 BIT(SYS_CTRL_CLK_PCIEB) |
140 BIT(SYS_CTRL_CLK_REF600) |
141 BIT(SYS_CTRL_CLK_USBDEV);
143 writel(value, SYS_CTRL_CLK_CLR_CTRL);
145 /* Enable clocks to cores as per power-on defaults */
147 /* Set sys-control pin mux'ing as per power-on defaults */
148 writel(0, SYS_CTRL_SECONDARY_SEL);
149 writel(0, SYS_CTRL_TERTIARY_SEL);
150 writel(0, SYS_CTRL_QUATERNARY_SEL);
151 writel(0, SYS_CTRL_DEBUG_SEL);
152 writel(0, SYS_CTRL_ALTERNATIVE_SEL);
153 writel(0, SYS_CTRL_PULLUP_SEL);
155 writel(0, SYS_CTRL_SECONDARY_SEL);
156 writel(0, SYS_CTRL_TERTIARY_SEL);
157 writel(0, SYS_CTRL_QUATERNARY_SEL);
158 writel(0, SYS_CTRL_DEBUG_SEL);
159 writel(0, SYS_CTRL_ALTERNATIVE_SEL);
160 writel(0, SYS_CTRL_PULLUP_SEL);
162 /* No need to save any state, as the ROM loader can determine whether
163 * reset is due to power cycling or programatic action, just hit the
164 * (self-clearing) CPU reset bit of the block reset register */
166 BIT(SYS_CTRL_RST_SCU) |
167 BIT(SYS_CTRL_RST_ARM0) |
168 BIT(SYS_CTRL_RST_ARM1);
170 writel(value, SYS_CTRL_RST_SET_CTRL);
173 static const char * const ox820_dt_board_compat[] = {
180 DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)")
181 .map_io = ox820_map_common_io,
182 .smp = smp_ops(ox820_smp_ops),
183 .init_early = ox820_init_early,
184 .init_time = ox820_timer_init,
185 .init_machine = ox820_dt_init,
186 .restart = ox820_assert_system_reset,
187 .dt_compat = ox820_dt_board_compat,