target/linux/mvebu/patches-3.10/0122-mtd-nand-pxa3xx-Move-cached-registers-to-info-struct.patch

   1 From 5c5367d7f9ad835b3b8a2dddfbe90e4c6e669084 Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Mon, 12 Aug 2013 14:14:55 -0300
   4 Subject: [PATCH 122/203] mtd: nand: pxa3xx: Move cached registers to info
   5  structure
   6
   7 This registers are not per-chip (aka host) but controller-wide,
   8 so it's better to store them in the global 'info' structure.
   9
  10 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  11 Tested-by: Daniel Mack <zonque@gmail.com>
  12 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
  13 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
  14 ---
  15  drivers/mtd/nand/pxa3xx_nand.c | 36 +++++++++++++++++-------------------
  16  1 file changed, 17 insertions(+), 19 deletions(-)
  17
  18 --- a/drivers/mtd/nand/pxa3xx_nand.c
  19 +++ b/drivers/mtd/nand/pxa3xx_nand.c
  20 @@ -144,10 +144,6 @@ struct pxa3xx_nand_host {
  21         unsigned int            row_addr_cycles;
  22         size_t                  read_id_bytes;
  23
  24 -       /* cached register value */
  25 -       uint32_t                reg_ndcr;
  26 -       uint32_t                ndtr0cs0;
  27 -       uint32_t                ndtr1cs0;
  28  };
  29
  30  struct pxa3xx_nand_info {
  31 @@ -193,6 +189,11 @@ struct pxa3xx_nand_info {
  32         unsigned int            oob_size;
  33         int                     retcode;
  34
  35 +       /* cached register value */
  36 +       uint32_t                reg_ndcr;
  37 +       uint32_t                ndtr0cs0;
  38 +       uint32_t                ndtr1cs0;
  39 +
  40         /* generated NDCBx register values */
  41         uint32_t                ndcb0;
  42         uint32_t                ndcb1;
  43 @@ -258,8 +259,8 @@ static void pxa3xx_nand_set_timing(struc
  44                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
  45                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
  46
  47 -       host->ndtr0cs0 = ndtr0;
  48 -       host->ndtr1cs0 = ndtr1;
  49 +       info->ndtr0cs0 = ndtr0;
  50 +       info->ndtr1cs0 = ndtr1;
  51         nand_writel(info, NDTR0CS0, ndtr0);
  52         nand_writel(info, NDTR1CS0, ndtr1);
  53  }
  54 @@ -267,7 +268,7 @@ static void pxa3xx_nand_set_timing(struc
  55  static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
  56  {
  57         struct pxa3xx_nand_host *host = info->host[info->cs];
  58 -       int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
  59 +       int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
  60
  61         info->data_size = host->page_size;
  62         if (!oob_enable) {
  63 @@ -293,10 +294,9 @@ static void pxa3xx_set_datasize(struct p
  64   */
  65  static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
  66  {
  67 -       struct pxa3xx_nand_host *host = info->host[info->cs];
  68         uint32_t ndcr;
  69
  70 -       ndcr = host->reg_ndcr;
  71 +       ndcr = info->reg_ndcr;
  72
  73         if (info->use_ecc)
  74                 ndcr |= NDCR_ECC_EN;
  75 @@ -683,7 +683,7 @@ static void pxa3xx_nand_cmdfunc(struct m
  76          * "byte" address into a "word" address appropriate
  77          * for indexing a word-oriented device
  78          */
  79 -       if (host->reg_ndcr & NDCR_DWIDTH_M)
  80 +       if (info->reg_ndcr & NDCR_DWIDTH_M)
  81                 column /= 2;
  82
  83         /*
  84 @@ -693,8 +693,8 @@ static void pxa3xx_nand_cmdfunc(struct m
  85          */
  86         if (info->cs != host->cs) {
  87                 info->cs = host->cs;
  88 -               nand_writel(info, NDTR0CS0, host->ndtr0cs0);
  89 -               nand_writel(info, NDTR1CS0, host->ndtr1cs0);
  90 +               nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  91 +               nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  92         }
  93
  94         info->state = STATE_PREPARED;
  95 @@ -870,7 +870,7 @@ static int pxa3xx_nand_config_flash(stru
  96         ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
  97         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
  98
  99 -       host->reg_ndcr = ndcr;
 100 +       info->reg_ndcr = ndcr;
 101
 102         pxa3xx_nand_set_timing(host, f->timing);
 103         return 0;
 104 @@ -893,11 +893,9 @@ static int pxa3xx_nand_detect_config(str
 105                 host->read_id_bytes = 2;
 106         }
 107
 108 -       host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 109 -
 110 -       host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 111 -       host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 112 -
 113 +       info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 114 +       info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 115 +       info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 116         return 0;
 117  }
 118
 119 @@ -1044,7 +1042,7 @@ KEEP_CONFIG:
 120         chip->ecc.size = host->page_size;
 121         chip->ecc.strength = 1;
 122
 123 -       if (host->reg_ndcr & NDCR_DWIDTH_M)
 124 +       if (info->reg_ndcr & NDCR_DWIDTH_M)
 125                 chip->options |= NAND_BUSWIDTH_16;
 126
 127         if (nand_scan_ident(mtd, 1, def))