target/linux/mvebu/patches-3.10/0059-ARM-mvebu-Relocate-Armada-370-XP-PCIe-device-tree-no.patch

   1 From db5029d82c4f0685438ea38eb3fbaadac46a22ba Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Wed, 12 Jun 2013 18:02:19 -0300
   4 Subject: [PATCH 059/203] ARM: mvebu: Relocate Armada 370/XP PCIe device tree
   5  nodes
   6
   7 Now that mbus has been added to the device tree, it's possible to
   8 move the PCIe nodes out of internal registers, placing it directly
   9 below the mbus. This is a more accurate representation of the
  10 hardware.
  11
  12 Moving the PCIe nodes, we now need to introduce an extra cell to
  13 encode the window target ID and attribute. Since this depends on
  14 the PCIe port, we split the ranges translation entries, to correspond
  15 to each MBus window.
  16
  17 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  18 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  19 Tested-by: Andrew Lunn <andrew@lunn.ch>
  20 Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  21 ---
  22  arch/arm/boot/dts/armada-370-mirabox.dts         |  32 +-
  23  arch/arm/boot/dts/armada-370-xp.dtsi             |   2 +
  24  arch/arm/boot/dts/armada-370.dtsi                | 101 +++---
  25  arch/arm/boot/dts/armada-xp-db.dts               |  67 ++--
  26  arch/arm/boot/dts/armada-xp-gp.dts               |  42 +--
  27  arch/arm/boot/dts/armada-xp-mv78230.dtsi         | 222 ++++++------
  28  arch/arm/boot/dts/armada-xp-mv78260.dtsi         | 261 ++++++++-------
  29  arch/arm/boot/dts/armada-xp-mv78460.dtsi         | 409 ++++++++++++-----------
  30  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts |  18 +-
  31  9 files changed, 612 insertions(+), 542 deletions(-)
  32
  33 --- a/arch/arm/boot/dts/armada-370-mirabox.dts
  34 +++ b/arch/arm/boot/dts/armada-370-mirabox.dts
  35 @@ -28,6 +28,22 @@
  36                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
  37                           MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
  38
  39 +               pcie-controller {
  40 +                       status = "okay";
  41 +
  42 +                       /* Internal mini-PCIe connector */
  43 +                       pcie@1,0 {
  44 +                               /* Port 0, Lane 0 */
  45 +                               status = "okay";
  46 +                       };
  47 +
  48 +                       /* Connected on the PCB to a USB 3.0 XHCI controller */
  49 +                       pcie@2,0 {
  50 +                               /* Port 1, Lane 0 */
  51 +                               status = "okay";
  52 +                       };
  53 +               };
  54 +
  55                 internal-regs {
  56                         serial@12000 {
  57                                 clock-frequency = <200000000>;
  58 @@ -123,22 +139,6 @@
  59                                         reg = <0x25>;
  60                                 };
  61                         };
  62 -
  63 -                       pcie-controller {
  64 -                               status = "okay";
  65 -
  66 -                               /* Internal mini-PCIe connector */
  67 -                               pcie@1,0 {
  68 -                                       /* Port 0, Lane 0 */
  69 -                                       status = "okay";
  70 -                               };
  71 -
  72 -                               /* Connected on the PCB to a USB 3.0 XHCI controller */
  73 -                               pcie@2,0 {
  74 -                                       /* Port 1, Lane 0 */
  75 -                                       status = "okay";
  76 -                               };
  77 -                       };
  78                 };
  79         };
  80  };
  81 --- a/arch/arm/boot/dts/armada-370-xp.dtsi
  82 +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
  83 @@ -35,6 +35,8 @@
  84                 #size-cells = <1>;
  85                 controller = <&mbusc>;
  86                 interrupt-parent = <&mpic>;
  87 +               pcie-mem-aperture = <0xe0000000 0x8000000>;
  88 +               pcie-io-aperture  = <0xe8000000 0x100000>;
  89
  90                 devbus-bootcs {
  91                         compatible = "marvell,mvebu-devbus";
  92 --- a/arch/arm/boot/dts/armada-370.dtsi
  93 +++ b/arch/arm/boot/dts/armada-370.dtsi
  94 @@ -36,6 +36,59 @@
  95                         reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
  96                 };
  97
  98 +               pcie-controller {
  99 +                       compatible = "marvell,armada-370-pcie";
 100 +                       status = "disabled";
 101 +                       device_type = "pci";
 102 +
 103 +                       #address-cells = <3>;
 104 +                       #size-cells = <2>;
 105 +
 106 +                       bus-range = <0x00 0xff>;
 107 +
 108 +                       ranges =
 109 +                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 110 +                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
 111 +                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
 112 +                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
 113 +                               0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
 114 +                               0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
 115 +
 116 +                       pcie@1,0 {
 117 +                               device_type = "pci";
 118 +                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 119 +                               reg = <0x0800 0 0 0 0>;
 120 +                               #address-cells = <3>;
 121 +                               #size-cells = <2>;
 122 +                               #interrupt-cells = <1>;
 123 +                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 124 +                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
 125 +                               interrupt-map-mask = <0 0 0 0>;
 126 +                               interrupt-map = <0 0 0 0 &mpic 58>;
 127 +                               marvell,pcie-port = <0>;
 128 +                               marvell,pcie-lane = <0>;
 129 +                               clocks = <&gateclk 5>;
 130 +                               status = "disabled";
 131 +                       };
 132 +
 133 +                       pcie@2,0 {
 134 +                               device_type = "pci";
 135 +                               assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 136 +                               reg = <0x1000 0 0 0 0>;
 137 +                               #address-cells = <3>;
 138 +                               #size-cells = <2>;
 139 +                               #interrupt-cells = <1>;
 140 +                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 141 +                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
 142 +                               interrupt-map-mask = <0 0 0 0>;
 143 +                               interrupt-map = <0 0 0 0 &mpic 62>;
 144 +                               marvell,pcie-port = <1>;
 145 +                               marvell,pcie-lane = <0>;
 146 +                               clocks = <&gateclk 9>;
 147 +                               status = "disabled";
 148 +                       };
 149 +               };
 150 +
 151                 internal-regs {
 152                         system-controller@18200 {
 153                                 compatible = "marvell,armada-370-xp-system-controller";
 154 @@ -174,54 +227,6 @@
 155                                         0x18304 0x4>;
 156                                 status = "okay";
 157                         };
 158 -
 159 -                       pcie-controller {
 160 -                               compatible = "marvell,armada-370-pcie";
 161 -                               status = "disabled";
 162 -                               device_type = "pci";
 163 -
 164 -                               #address-cells = <3>;
 165 -                               #size-cells = <2>;
 166 -
 167 -                               bus-range = <0x00 0xff>;
 168 -
 169 -                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
 170 -                                       0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
 171 -                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 172 -                                       0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
 173 -
 174 -                               pcie@1,0 {
 175 -                                       device_type = "pci";
 176 -                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 177 -                                       reg = <0x0800 0 0 0 0>;
 178 -                                       #address-cells = <3>;
 179 -                                       #size-cells = <2>;
 180 -                                       #interrupt-cells = <1>;
 181 -                                       ranges;
 182 -                                       interrupt-map-mask = <0 0 0 0>;
 183 -                                       interrupt-map = <0 0 0 0 &mpic 58>;
 184 -                                       marvell,pcie-port = <0>;
 185 -                                       marvell,pcie-lane = <0>;
 186 -                                       clocks = <&gateclk 5>;
 187 -                                       status = "disabled";
 188 -                               };
 189 -
 190 -                               pcie@2,0 {
 191 -                                       device_type = "pci";
 192 -                                       assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 193 -                                       reg = <0x1000 0 0 0 0>;
 194 -                                       #address-cells = <3>;
 195 -                                       #size-cells = <2>;
 196 -                                       #interrupt-cells = <1>;
 197 -                                       ranges;
 198 -                                       interrupt-map-mask = <0 0 0 0>;
 199 -                                       interrupt-map = <0 0 0 0 &mpic 62>;
 200 -                                       marvell,pcie-port = <1>;
 201 -                                       marvell,pcie-lane = <0>;
 202 -                                       clocks = <&gateclk 9>;
 203 -                                       status = "disabled";
 204 -                               };
 205 -                       };
 206                 };
 207         };
 208  };
 209 --- a/arch/arm/boot/dts/armada-xp-db.dts
 210 +++ b/arch/arm/boot/dts/armada-xp-db.dts
 211 @@ -62,6 +62,39 @@
 212                         };
 213                 };
 214
 215 +               pcie-controller {
 216 +                       status = "okay";
 217 +
 218 +                       /*
 219 +                        * All 6 slots are physically present as
 220 +                        * standard PCIe slots on the board.
 221 +                        */
 222 +                       pcie@1,0 {
 223 +                               /* Port 0, Lane 0 */
 224 +                               status = "okay";
 225 +                       };
 226 +                       pcie@2,0 {
 227 +                               /* Port 0, Lane 1 */
 228 +                               status = "okay";
 229 +                       };
 230 +                       pcie@3,0 {
 231 +                               /* Port 0, Lane 2 */
 232 +                               status = "okay";
 233 +                       };
 234 +                       pcie@4,0 {
 235 +                               /* Port 0, Lane 3 */
 236 +                               status = "okay";
 237 +                       };
 238 +                       pcie@9,0 {
 239 +                               /* Port 2, Lane 0 */
 240 +                               status = "okay";
 241 +                       };
 242 +                       pcie@10,0 {
 243 +                               /* Port 3, Lane 0 */
 244 +                               status = "okay";
 245 +                       };
 246 +               };
 247 +
 248                 internal-regs {
 249                         serial@12000 {
 250                                 clock-frequency = <250000000>;
 251 @@ -155,40 +188,6 @@
 252                                         spi-max-frequency = <20000000>;
 253                                 };
 254                         };
 255 -
 256 -                       pcie-controller {
 257 -                               status = "okay";
 258 -
 259 -                               /*
 260 -                                * All 6 slots are physically present as
 261 -                                * standard PCIe slots on the board.
 262 -                                */
 263 -                               pcie@1,0 {
 264 -                                       /* Port 0, Lane 0 */
 265 -                                       status = "okay";
 266 -                               };
 267 -                               pcie@2,0 {
 268 -                                       /* Port 0, Lane 1 */
 269 -                                       status = "okay";
 270 -                               };
 271 -                               pcie@3,0 {
 272 -                                       /* Port 0, Lane 2 */
 273 -                                       status = "okay";
 274 -                               };
 275 -                               pcie@4,0 {
 276 -                                       /* Port 0, Lane 3 */
 277 -                                       status = "okay";
 278 -                               };
 279 -                               pcie@9,0 {
 280 -                                       /* Port 2, Lane 0 */
 281 -                                       status = "okay";
 282 -                               };
 283 -                               pcie@10,0 {
 284 -                                       /* Port 3, Lane 0 */
 285 -                                       status = "okay";
 286 -                               };
 287 -                       };
 288 -
 289                 };
 290         };
 291  };
 292 --- a/arch/arm/boot/dts/armada-xp-gp.dts
 293 +++ b/arch/arm/boot/dts/armada-xp-gp.dts
 294 @@ -71,6 +71,27 @@
 295                         };
 296                 };
 297
 298 +               pcie-controller {
 299 +                       status = "okay";
 300 +
 301 +                       /*
 302 +                        * The 3 slots are physically present as
 303 +                        * standard PCIe slots on the board.
 304 +                        */
 305 +                       pcie@1,0 {
 306 +                               /* Port 0, Lane 0 */
 307 +                               status = "okay";
 308 +                       };
 309 +                       pcie@9,0 {
 310 +                               /* Port 2, Lane 0 */
 311 +                               status = "okay";
 312 +                       };
 313 +                       pcie@10,0 {
 314 +                               /* Port 3, Lane 0 */
 315 +                               status = "okay";
 316 +                       };
 317 +               };
 318 +
 319                 internal-regs {
 320                         serial@12000 {
 321                                 clock-frequency = <250000000>;
 322 @@ -154,27 +175,6 @@
 323                                         spi-max-frequency = <108000000>;
 324                                 };
 325                         };
 326 -
 327 -                       pcie-controller {
 328 -                               status = "okay";
 329 -
 330 -                               /*
 331 -                                * The 3 slots are physically present as
 332 -                                * standard PCIe slots on the board.
 333 -                                */
 334 -                               pcie@1,0 {
 335 -                                       /* Port 0, Lane 0 */
 336 -                                       status = "okay";
 337 -                               };
 338 -                               pcie@9,0 {
 339 -                                       /* Port 2, Lane 0 */
 340 -                                       status = "okay";
 341 -                               };
 342 -                               pcie@10,0 {
 343 -                                       /* Port 3, Lane 0 */
 344 -                                       status = "okay";
 345 -                               };
 346 -                       };
 347                 };
 348         };
 349  };
 350 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
 351 +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
 352 @@ -44,6 +44,124 @@
 353         };
 354
 355         soc {
 356 +               /*
 357 +                * MV78230 has 2 PCIe units Gen2.0: One unit can be
 358 +                * configured as x4 or quad x1 lanes. One unit is
 359 +                * x4/x1.
 360 +                */
 361 +               pcie-controller {
 362 +                       compatible = "marvell,armada-xp-pcie";
 363 +                       status = "disabled";
 364 +                       device_type = "pci";
 365 +
 366 +                       #address-cells = <3>;
 367 +                       #size-cells = <2>;
 368 +
 369 +                       bus-range = <0x00 0xff>;
 370 +
 371 +                       ranges =
 372 +                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
 373 +                               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
 374 +                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
 375 +                               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
 376 +                               0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
 377 +                               0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 378 +                               0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
 379 +                               0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
 380 +                               0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
 381 +                               0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
 382 +                               0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
 383 +                               0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
 384 +                               0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 385 +                               0x82000000 0x9 0       MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 386 +                               0x81000000 0x9 0       MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;
 387 +
 388 +                       pcie@1,0 {
 389 +                               device_type = "pci";
 390 +                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 391 +                               reg = <0x0800 0 0 0 0>;
 392 +                               #address-cells = <3>;
 393 +                               #size-cells = <2>;
 394 +                               #interrupt-cells = <1>;
 395 +                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 396 +                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
 397 +                               interrupt-map-mask = <0 0 0 0>;
 398 +                               interrupt-map = <0 0 0 0 &mpic 58>;
 399 +                               marvell,pcie-port = <0>;
 400 +                               marvell,pcie-lane = <0>;
 401 +                               clocks = <&gateclk 5>;
 402 +                               status = "disabled";
 403 +                       };
 404 +
 405 +                       pcie@2,0 {
 406 +                               device_type = "pci";
 407 +                               assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 408 +                               reg = <0x1000 0 0 0 0>;
 409 +                               #address-cells = <3>;
 410 +                               #size-cells = <2>;
 411 +                               #interrupt-cells = <1>;
 412 +                               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 413 +                                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
 414 +                               interrupt-map-mask = <0 0 0 0>;
 415 +                               interrupt-map = <0 0 0 0 &mpic 59>;
 416 +                               marvell,pcie-port = <0>;
 417 +                               marvell,pcie-lane = <1>;
 418 +                               clocks = <&gateclk 6>;
 419 +                               status = "disabled";
 420 +                       };
 421 +
 422 +                       pcie@3,0 {
 423 +                               device_type = "pci";
 424 +                               assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 425 +                               reg = <0x1800 0 0 0 0>;
 426 +                               #address-cells = <3>;
 427 +                               #size-cells = <2>;
 428 +                               #interrupt-cells = <1>;
 429 +                               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 430 +                                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
 431 +                               interrupt-map-mask = <0 0 0 0>;
 432 +                               interrupt-map = <0 0 0 0 &mpic 60>;
 433 +                               marvell,pcie-port = <0>;
 434 +                               marvell,pcie-lane = <2>;
 435 +                               clocks = <&gateclk 7>;
 436 +                               status = "disabled";
 437 +                       };
 438 +
 439 +                       pcie@4,0 {
 440 +                               device_type = "pci";
 441 +                               assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
 442 +                               reg = <0x2000 0 0 0 0>;
 443 +                               #address-cells = <3>;
 444 +                               #size-cells = <2>;
 445 +                               #interrupt-cells = <1>;
 446 +                               ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 447 +                                         0x81000000 0 0 0x81000000 0x4 0 1 0>;
 448 +                               interrupt-map-mask = <0 0 0 0>;
 449 +                               interrupt-map = <0 0 0 0 &mpic 61>;
 450 +                               marvell,pcie-port = <0>;
 451 +                               marvell,pcie-lane = <3>;
 452 +                               clocks = <&gateclk 8>;
 453 +                               status = "disabled";
 454 +                       };
 455 +
 456 +                       pcie@9,0 {
 457 +                               device_type = "pci";
 458 +                               assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
 459 +                               reg = <0x4800 0 0 0 0>;
 460 +                               #address-cells = <3>;
 461 +                               #size-cells = <2>;
 462 +                               #interrupt-cells = <1>;
 463 +                               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 464 +                                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
 465 +                               interrupt-map-mask = <0 0 0 0>;
 466 +                               interrupt-map = <0 0 0 0 &mpic 99>;
 467 +                               marvell,pcie-port = <2>;
 468 +                               marvell,pcie-lane = <0>;
 469 +                               clocks = <&gateclk 26>;
 470 +                               status = "disabled";
 471 +                       };
 472 +               };
 473 +
 474                 internal-regs {
 475                         pinctrl {
 476                                 compatible = "marvell,mv78230-pinctrl";
 477 @@ -79,108 +197,6 @@
 478                         };
 479
 480                         /*
 481 -                        * MV78230 has 2 PCIe units Gen2.0: One unit can be
 482 -                        * configured as x4 or quad x1 lanes. One unit is
 483 -                        * x1 only.
 484 -                        */
 485 -                       pcie-controller {
 486 -                               compatible = "marvell,armada-xp-pcie";
 487 -                               status = "disabled";
 488 -                               device_type = "pci";
 489 -
 490 -#address-cells = <3>;
 491 -#size-cells = <2>;
 492 -
 493 -                               bus-range = <0x00 0xff>;
 494 -
 495 -                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
 496 -                                       0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
 497 -                                       0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
 498 -                                       0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
 499 -                                       0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
 500 -                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 501 -                                       0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
 502 -
 503 -                               pcie@1,0 {
 504 -                                       device_type = "pci";
 505 -                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 506 -                                       reg = <0x0800 0 0 0 0>;
 507 -                                       #address-cells = <3>;
 508 -                                       #size-cells = <2>;
 509 -                                       #interrupt-cells = <1>;
 510 -                                       ranges;
 511 -                                       interrupt-map-mask = <0 0 0 0>;
 512 -                                       interrupt-map = <0 0 0 0 &mpic 58>;
 513 -                                       marvell,pcie-port = <0>;
 514 -                                       marvell,pcie-lane = <0>;
 515 -                                       clocks = <&gateclk 5>;
 516 -                                       status = "disabled";
 517 -                               };
 518 -
 519 -                               pcie@2,0 {
 520 -                                       device_type = "pci";
 521 -                                       assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 522 -                                       reg = <0x1000 0 0 0 0>;
 523 -                                       #address-cells = <3>;
 524 -                                       #size-cells = <2>;
 525 -                                       #interrupt-cells = <1>;
 526 -                                       ranges;
 527 -                                       interrupt-map-mask = <0 0 0 0>;
 528 -                                       interrupt-map = <0 0 0 0 &mpic 59>;
 529 -                                       marvell,pcie-port = <0>;
 530 -                                       marvell,pcie-lane = <1>;
 531 -                                       clocks = <&gateclk 6>;
 532 -                                       status = "disabled";
 533 -                               };
 534 -
 535 -                               pcie@3,0 {
 536 -                                       device_type = "pci";
 537 -                                       assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 538 -                                       reg = <0x1800 0 0 0 0>;
 539 -                                       #address-cells = <3>;
 540 -                                       #size-cells = <2>;
 541 -                                       #interrupt-cells = <1>;
 542 -                                       ranges;
 543 -                                       interrupt-map-mask = <0 0 0 0>;
 544 -                                       interrupt-map = <0 0 0 0 &mpic 60>;
 545 -                                       marvell,pcie-port = <0>;
 546 -                                       marvell,pcie-lane = <2>;
 547 -                                       clocks = <&gateclk 7>;
 548 -                                       status = "disabled";
 549 -                               };
 550 -
 551 -                               pcie@4,0 {
 552 -                                       device_type = "pci";
 553 -                                       assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
 554 -                                       reg = <0x2000 0 0 0 0>;
 555 -                                       #address-cells = <3>;
 556 -                                       #size-cells = <2>;
 557 -                                       #interrupt-cells = <1>;
 558 -                                       ranges;
 559 -                                       interrupt-map-mask = <0 0 0 0>;
 560 -                                       interrupt-map = <0 0 0 0 &mpic 61>;
 561 -                                       marvell,pcie-port = <0>;
 562 -                                       marvell,pcie-lane = <3>;
 563 -                                       clocks = <&gateclk 8>;
 564 -                                       status = "disabled";
 565 -                               };
 566 -
 567 -                               pcie@5,0 {
 568 -                                       device_type = "pci";
 569 -                                       assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
 570 -                                       reg = <0x2800 0 0 0 0>;
 571 -                                       #address-cells = <3>;
 572 -                                       #size-cells = <2>;
 573 -                                       #interrupt-cells = <1>;
 574 -                                       ranges;
 575 -                                       interrupt-map-mask = <0 0 0 0>;
 576 -                                       interrupt-map = <0 0 0 0 &mpic 62>;
 577 -                                       marvell,pcie-port = <1>;
 578 -                                       marvell,pcie-lane = <0>;
 579 -                                       clocks = <&gateclk 9>;
 580 -                                       status = "disabled";
 581 -                               };
 582 -                       };
 583                 };
 584         };
 585  };
 586 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
 587 +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
 588 @@ -45,6 +45,145 @@
 589         };
 590
 591         soc {
 592 +               /*
 593 +                * MV78260 has 3 PCIe units Gen2.0: Two units can be
 594 +                * configured as x4 or quad x1 lanes. One unit is
 595 +                * x4/x1.
 596 +                */
 597 +               pcie-controller {
 598 +                       compatible = "marvell,armada-xp-pcie";
 599 +                       status = "disabled";
 600 +                       device_type = "pci";
 601 +
 602 +                       #address-cells = <3>;
 603 +                       #size-cells = <2>;
 604 +
 605 +                       bus-range = <0x00 0xff>;
 606 +
 607 +                       ranges =
 608 +                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
 609 +                               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
 610 +                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
 611 +                               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
 612 +                               0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
 613 +                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
 614 +                               0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
 615 +                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 616 +                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
 617 +                               0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
 618 +                               0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
 619 +                               0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
 620 +                               0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
 621 +                               0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
 622 +                               0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 623 +                               0x82000000 0x9 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 624 +                               0x81000000 0x9 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 625 +                               0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
 626 +                               0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 627 +
 628 +                       pcie@1,0 {
 629 +                               device_type = "pci";
 630 +                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 631 +                               reg = <0x0800 0 0 0 0>;
 632 +                               #address-cells = <3>;
 633 +                               #size-cells = <2>;
 634 +                               #interrupt-cells = <1>;
 635 +                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 636 +                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
 637 +                               interrupt-map-mask = <0 0 0 0>;
 638 +                               interrupt-map = <0 0 0 0 &mpic 58>;
 639 +                               marvell,pcie-port = <0>;
 640 +                               marvell,pcie-lane = <0>;
 641 +                               clocks = <&gateclk 5>;
 642 +                               status = "disabled";
 643 +                       };
 644 +
 645 +                       pcie@2,0 {
 646 +                               device_type = "pci";
 647 +                               assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 648 +                               reg = <0x1000 0 0 0 0>;
 649 +                               #address-cells = <3>;
 650 +                               #size-cells = <2>;
 651 +                               #interrupt-cells = <1>;
 652 +                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 653 +                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
 654 +                               interrupt-map-mask = <0 0 0 0>;
 655 +                               interrupt-map = <0 0 0 0 &mpic 59>;
 656 +                               marvell,pcie-port = <0>;
 657 +                               marvell,pcie-lane = <1>;
 658 +                               clocks = <&gateclk 6>;
 659 +                               status = "disabled";
 660 +                       };
 661 +
 662 +                       pcie@3,0 {
 663 +                               device_type = "pci";
 664 +                               assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 665 +                               reg = <0x1800 0 0 0 0>;
 666 +                               #address-cells = <3>;
 667 +                               #size-cells = <2>;
 668 +                               #interrupt-cells = <1>;
 669 +                               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 670 +                                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
 671 +                               interrupt-map-mask = <0 0 0 0>;
 672 +                               interrupt-map = <0 0 0 0 &mpic 60>;
 673 +                               marvell,pcie-port = <0>;
 674 +                               marvell,pcie-lane = <2>;
 675 +                               clocks = <&gateclk 7>;
 676 +                               status = "disabled";
 677 +                       };
 678 +
 679 +                       pcie@4,0 {
 680 +                               device_type = "pci";
 681 +                               assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
 682 +                               reg = <0x2000 0 0 0 0>;
 683 +                               #address-cells = <3>;
 684 +                               #size-cells = <2>;
 685 +                               #interrupt-cells = <1>;
 686 +                               ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 687 +                                         0x81000000 0 0 0x81000000 0x4 0 1 0>;
 688 +                               interrupt-map-mask = <0 0 0 0>;
 689 +                               interrupt-map = <0 0 0 0 &mpic 61>;
 690 +                               marvell,pcie-port = <0>;
 691 +                               marvell,pcie-lane = <3>;
 692 +                               clocks = <&gateclk 8>;
 693 +                               status = "disabled";
 694 +                       };
 695 +
 696 +                       pcie@9,0 {
 697 +                               device_type = "pci";
 698 +                               assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
 699 +                               reg = <0x4800 0 0 0 0>;
 700 +                               #address-cells = <3>;
 701 +                               #size-cells = <2>;
 702 +                               #interrupt-cells = <1>;
 703 +                               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 704 +                                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
 705 +                               interrupt-map-mask = <0 0 0 0>;
 706 +                               interrupt-map = <0 0 0 0 &mpic 99>;
 707 +                               marvell,pcie-port = <2>;
 708 +                               marvell,pcie-lane = <0>;
 709 +                               clocks = <&gateclk 26>;
 710 +                               status = "disabled";
 711 +                       };
 712 +
 713 +                       pcie@10,0 {
 714 +                               device_type = "pci";
 715 +                               assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
 716 +                               reg = <0x5000 0 0 0 0>;
 717 +                               #address-cells = <3>;
 718 +                               #size-cells = <2>;
 719 +                               #interrupt-cells = <1>;
 720 +                               ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
 721 +                                         0x81000000 0 0 0x81000000 0xa 0 1 0>;
 722 +                               interrupt-map-mask = <0 0 0 0>;
 723 +                               interrupt-map = <0 0 0 0 &mpic 103>;
 724 +                               marvell,pcie-port = <3>;
 725 +                               marvell,pcie-lane = <0>;
 726 +                               clocks = <&gateclk 27>;
 727 +                               status = "disabled";
 728 +                       };
 729 +               };
 730 +
 731                 internal-regs {
 732                         pinctrl {
 733                                 compatible = "marvell,mv78260-pinctrl";
 734 @@ -98,177 +237,6 @@
 735                                 status = "disabled";
 736                         };
 737
 738 -                       /*
 739 -                        * MV78260 has 3 PCIe units Gen2.0: Two units can be
 740 -                        * configured as x4 or quad x1 lanes. One unit is
 741 -                        * x4 only.
 742 -                        */
 743 -                       pcie-controller {
 744 -                               compatible = "marvell,armada-xp-pcie";
 745 -                               status = "disabled";
 746 -                               device_type = "pci";
 747 -
 748 -                               #address-cells = <3>;
 749 -                               #size-cells = <2>;
 750 -
 751 -                               bus-range = <0x00 0xff>;
 752 -
 753 -                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
 754 -                                       0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
 755 -                                       0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
 756 -                                       0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
 757 -                                       0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
 758 -                                       0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
 759 -                                       0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
 760 -                                       0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
 761 -                                       0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
 762 -                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 763 -                                       0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
 764 -
 765 -                               pcie@1,0 {
 766 -                                       device_type = "pci";
 767 -                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 768 -                                       reg = <0x0800 0 0 0 0>;
 769 -                                       #address-cells = <3>;
 770 -                                       #size-cells = <2>;
 771 -                                       #interrupt-cells = <1>;
 772 -                                       ranges;
 773 -                                       interrupt-map-mask = <0 0 0 0>;
 774 -                                       interrupt-map = <0 0 0 0 &mpic 58>;
 775 -                                       marvell,pcie-port = <0>;
 776 -                                       marvell,pcie-lane = <0>;
 777 -                                       clocks = <&gateclk 5>;
 778 -                                       status = "disabled";
 779 -                               };
 780 -
 781 -                               pcie@2,0 {
 782 -                                       device_type = "pci";
 783 -                                       assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 784 -                                       reg = <0x1000 0 0 0 0>;
 785 -                                       #address-cells = <3>;
 786 -                                       #size-cells = <2>;
 787 -                                       #interrupt-cells = <1>;
 788 -                                       ranges;
 789 -                                       interrupt-map-mask = <0 0 0 0>;
 790 -                                       interrupt-map = <0 0 0 0 &mpic 59>;
 791 -                                       marvell,pcie-port = <0>;
 792 -                                       marvell,pcie-lane = <1>;
 793 -                                       clocks = <&gateclk 6>;
 794 -                                       status = "disabled";
 795 -                               };
 796 -
 797 -                               pcie@3,0 {
 798 -                                       device_type = "pci";
 799 -                                       assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 800 -                                       reg = <0x1800 0 0 0 0>;
 801 -                                       #address-cells = <3>;
 802 -                                       #size-cells = <2>;
 803 -                                       #interrupt-cells = <1>;
 804 -                                       ranges;
 805 -                                       interrupt-map-mask = <0 0 0 0>;
 806 -                                       interrupt-map = <0 0 0 0 &mpic 60>;
 807 -                                       marvell,pcie-port = <0>;
 808 -                                       marvell,pcie-lane = <2>;
 809 -                                       clocks = <&gateclk 7>;
 810 -                                       status = "disabled";
 811 -                               };
 812 -
 813 -                               pcie@4,0 {
 814 -                                       device_type = "pci";
 815 -                                       assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
 816 -                                       reg = <0x2000 0 0 0 0>;
 817 -                                       #address-cells = <3>;
 818 -                                       #size-cells = <2>;
 819 -                                       #interrupt-cells = <1>;
 820 -                                       ranges;
 821 -                                       interrupt-map-mask = <0 0 0 0>;
 822 -                                       interrupt-map = <0 0 0 0 &mpic 61>;
 823 -                                       marvell,pcie-port = <0>;
 824 -                                       marvell,pcie-lane = <3>;
 825 -                                       clocks = <&gateclk 8>;
 826 -                                       status = "disabled";
 827 -                               };
 828 -
 829 -                               pcie@5,0 {
 830 -                                       device_type = "pci";
 831 -                                       assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
 832 -                                       reg = <0x2800 0 0 0 0>;
 833 -                                       #address-cells = <3>;
 834 -                                       #size-cells = <2>;
 835 -                                       #interrupt-cells = <1>;
 836 -                                       ranges;
 837 -                                       interrupt-map-mask = <0 0 0 0>;
 838 -                                       interrupt-map = <0 0 0 0 &mpic 62>;
 839 -                                       marvell,pcie-port = <1>;
 840 -                                       marvell,pcie-lane = <0>;
 841 -                                       clocks = <&gateclk 9>;
 842 -                                       status = "disabled";
 843 -                               };
 844 -
 845 -                               pcie@6,0 {
 846 -                                       device_type = "pci";
 847 -                                       assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
 848 -                                       reg = <0x3000 0 0 0 0>;
 849 -                                       #address-cells = <3>;
 850 -                                       #size-cells = <2>;
 851 -                                       #interrupt-cells = <1>;
 852 -                                       ranges;
 853 -                                       interrupt-map-mask = <0 0 0 0>;
 854 -                                       interrupt-map = <0 0 0 0 &mpic 63>;
 855 -                                       marvell,pcie-port = <1>;
 856 -                                       marvell,pcie-lane = <1>;
 857 -                                       clocks = <&gateclk 10>;
 858 -                                       status = "disabled";
 859 -                               };
 860 -
 861 -                               pcie@7,0 {
 862 -                                       device_type = "pci";
 863 -                                       assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
 864 -                                       reg = <0x3800 0 0 0 0>;
 865 -                                       #address-cells = <3>;
 866 -                                       #size-cells = <2>;
 867 -                                       #interrupt-cells = <1>;
 868 -                                       ranges;
 869 -                                       interrupt-map-mask = <0 0 0 0>;
 870 -                                       interrupt-map = <0 0 0 0 &mpic 64>;
 871 -                                       marvell,pcie-port = <1>;
 872 -                                       marvell,pcie-lane = <2>;
 873 -                                       clocks = <&gateclk 11>;
 874 -                                       status = "disabled";
 875 -                               };
 876 -
 877 -                               pcie@8,0 {
 878 -                                       device_type = "pci";
 879 -                                       assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
 880 -                                       reg = <0x4000 0 0 0 0>;
 881 -                                       #address-cells = <3>;
 882 -                                       #size-cells = <2>;
 883 -                                       #interrupt-cells = <1>;
 884 -                                       ranges;
 885 -                                       interrupt-map-mask = <0 0 0 0>;
 886 -                                       interrupt-map = <0 0 0 0 &mpic 65>;
 887 -                                       marvell,pcie-port = <1>;
 888 -                                       marvell,pcie-lane = <3>;
 889 -                                       clocks = <&gateclk 12>;
 890 -                                       status = "disabled";
 891 -                               };
 892 -
 893 -                               pcie@9,0 {
 894 -                                       device_type = "pci";
 895 -                                       assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
 896 -                                       reg = <0x4800 0 0 0 0>;
 897 -                                       #address-cells = <3>;
 898 -                                       #size-cells = <2>;
 899 -                                       #interrupt-cells = <1>;
 900 -                                       ranges;
 901 -                                       interrupt-map-mask = <0 0 0 0>;
 902 -                                       interrupt-map = <0 0 0 0 &mpic 99>;
 903 -                                       marvell,pcie-port = <2>;
 904 -                                       marvell,pcie-lane = <0>;
 905 -                                       clocks = <&gateclk 26>;
 906 -                                       status = "disabled";
 907 -                               };
 908 -                       };
 909                 };
 910         };
 911  };
 912 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
 913 +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
 914 @@ -60,6 +60,227 @@
 915         };
 916
 917         soc {
 918 +               /*
 919 +                * MV78460 has 4 PCIe units Gen2.0: Two units can be
 920 +                * configured as x4 or quad x1 lanes. Two units are
 921 +                * x4/x1.
 922 +                */
 923 +               pcie-controller {
 924 +                       compatible = "marvell,armada-xp-pcie";
 925 +                       status = "disabled";
 926 +                       device_type = "pci";
 927 +
 928 +                       #address-cells = <3>;
 929 +                       #size-cells = <2>;
 930 +
 931 +                       bus-range = <0x00 0xff>;
 932 +
 933 +                       ranges =
 934 +                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
 935 +                               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
 936 +                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
 937 +                               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
 938 +                               0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
 939 +                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
 940 +                               0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
 941 +                               0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
 942 +                               0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
 943 +                               0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
 944 +                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 945 +                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
 946 +                               0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
 947 +                               0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
 948 +                               0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
 949 +                               0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
 950 +                               0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
 951 +                               0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 952 +
 953 +                               0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 954 +                               0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 955 +                               0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
 956 +                               0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
 957 +                               0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
 958 +                               0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
 959 +                               0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
 960 +                               0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
 961 +
 962 +                               0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 963 +                               0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
 964 +
 965 +                               0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
 966 +                               0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 967 +
 968 +                       pcie@1,0 {
 969 +                               device_type = "pci";
 970 +                               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 971 +                               reg = <0x0800 0 0 0 0>;
 972 +                               #address-cells = <3>;
 973 +                               #size-cells = <2>;
 974 +                               #interrupt-cells = <1>;
 975 +                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 976 +                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
 977 +                               interrupt-map-mask = <0 0 0 0>;
 978 +                               interrupt-map = <0 0 0 0 &mpic 58>;
 979 +                               marvell,pcie-port = <0>;
 980 +                               marvell,pcie-lane = <0>;
 981 +                               clocks = <&gateclk 5>;
 982 +                               status = "disabled";
 983 +                       };
 984 +
 985 +                       pcie@2,0 {
 986 +                               device_type = "pci";
 987 +                               assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 988 +                               reg = <0x1000 0 0 0 0>;
 989 +                               #address-cells = <3>;
 990 +                               #size-cells = <2>;
 991 +                               #interrupt-cells = <1>;
 992 +                               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 993 +                                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
 994 +                               interrupt-map-mask = <0 0 0 0>;
 995 +                               interrupt-map = <0 0 0 0 &mpic 59>;
 996 +                               marvell,pcie-port = <0>;
 997 +                               marvell,pcie-lane = <1>;
 998 +                               clocks = <&gateclk 6>;
 999 +                               status = "disabled";
1000 +                       };
1001 +
1002 +                       pcie@3,0 {
1003 +                               device_type = "pci";
1004 +                               assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
1005 +                               reg = <0x1800 0 0 0 0>;
1006 +                               #address-cells = <3>;
1007 +                               #size-cells = <2>;
1008 +                               #interrupt-cells = <1>;
1009 +                               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
1010 +                                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
1011 +                               interrupt-map-mask = <0 0 0 0>;
1012 +                               interrupt-map = <0 0 0 0 &mpic 60>;
1013 +                               marvell,pcie-port = <0>;
1014 +                               marvell,pcie-lane = <2>;
1015 +                               clocks = <&gateclk 7>;
1016 +                               status = "disabled";
1017 +                       };
1018 +
1019 +                       pcie@4,0 {
1020 +                               device_type = "pci";
1021 +                               assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
1022 +                               reg = <0x2000 0 0 0 0>;
1023 +                               #address-cells = <3>;
1024 +                               #size-cells = <2>;
1025 +                               #interrupt-cells = <1>;
1026 +                               ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
1027 +                                         0x81000000 0 0 0x81000000 0x4 0 1 0>;
1028 +                               interrupt-map-mask = <0 0 0 0>;
1029 +                               interrupt-map = <0 0 0 0 &mpic 61>;
1030 +                               marvell,pcie-port = <0>;
1031 +                               marvell,pcie-lane = <3>;
1032 +                               clocks = <&gateclk 8>;
1033 +                               status = "disabled";
1034 +                       };
1035 +
1036 +                       pcie@5,0 {
1037 +                               device_type = "pci";
1038 +                               assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
1039 +                               reg = <0x2800 0 0 0 0>;
1040 +                               #address-cells = <3>;
1041 +                               #size-cells = <2>;
1042 +                               #interrupt-cells = <1>;
1043 +                               ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
1044 +                                         0x81000000 0 0 0x81000000 0x5 0 1 0>;
1045 +                               interrupt-map-mask = <0 0 0 0>;
1046 +                               interrupt-map = <0 0 0 0 &mpic 62>;
1047 +                               marvell,pcie-port = <1>;
1048 +                               marvell,pcie-lane = <0>;
1049 +                               clocks = <&gateclk 9>;
1050 +                               status = "disabled";
1051 +                       };
1052 +
1053 +                       pcie@6,0 {
1054 +                               device_type = "pci";
1055 +                               assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
1056 +                               reg = <0x3000 0 0 0 0>;
1057 +                               #address-cells = <3>;
1058 +                               #size-cells = <2>;
1059 +                               #interrupt-cells = <1>;
1060 +                               ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
1061 +                                         0x81000000 0 0 0x81000000 0x6 0 1 0>;
1062 +                               interrupt-map-mask = <0 0 0 0>;
1063 +                               interrupt-map = <0 0 0 0 &mpic 63>;
1064 +                               marvell,pcie-port = <1>;
1065 +                               marvell,pcie-lane = <1>;
1066 +                               clocks = <&gateclk 10>;
1067 +                               status = "disabled";
1068 +                       };
1069 +
1070 +                       pcie@7,0 {
1071 +                               device_type = "pci";
1072 +                               assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
1073 +                               reg = <0x3800 0 0 0 0>;
1074 +                               #address-cells = <3>;
1075 +                               #size-cells = <2>;
1076 +                               #interrupt-cells = <1>;
1077 +                               ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
1078 +                                         0x81000000 0 0 0x81000000 0x7 0 1 0>;
1079 +                               interrupt-map-mask = <0 0 0 0>;
1080 +                               interrupt-map = <0 0 0 0 &mpic 64>;
1081 +                               marvell,pcie-port = <1>;
1082 +                               marvell,pcie-lane = <2>;
1083 +                               clocks = <&gateclk 11>;
1084 +                               status = "disabled";
1085 +                       };
1086 +
1087 +                       pcie@8,0 {
1088 +                               device_type = "pci";
1089 +                               assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
1090 +                               reg = <0x4000 0 0 0 0>;
1091 +                               #address-cells = <3>;
1092 +                               #size-cells = <2>;
1093 +                               #interrupt-cells = <1>;
1094 +                               ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
1095 +                                         0x81000000 0 0 0x81000000 0x8 0 1 0>;
1096 +                               interrupt-map-mask = <0 0 0 0>;
1097 +                               interrupt-map = <0 0 0 0 &mpic 65>;
1098 +                               marvell,pcie-port = <1>;
1099 +                               marvell,pcie-lane = <3>;
1100 +                               clocks = <&gateclk 12>;
1101 +                               status = "disabled";
1102 +                       };
1103 +
1104 +                       pcie@9,0 {
1105 +                               device_type = "pci";
1106 +                               assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
1107 +                               reg = <0x4800 0 0 0 0>;
1108 +                               #address-cells = <3>;
1109 +                               #size-cells = <2>;
1110 +                               #interrupt-cells = <1>;
1111 +                               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
1112 +                                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
1113 +                               interrupt-map-mask = <0 0 0 0>;
1114 +                               interrupt-map = <0 0 0 0 &mpic 99>;
1115 +                               marvell,pcie-port = <2>;
1116 +                               marvell,pcie-lane = <0>;
1117 +                               clocks = <&gateclk 26>;
1118 +                               status = "disabled";
1119 +                       };
1120 +
1121 +                       pcie@10,0 {
1122 +                               device_type = "pci";
1123 +                               assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
1124 +                               reg = <0x5000 0 0 0 0>;
1125 +                               #address-cells = <3>;
1126 +                               #size-cells = <2>;
1127 +                               #interrupt-cells = <1>;
1128 +                               ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
1129 +                                         0x81000000 0 0 0x81000000 0xa 0 1 0>;
1130 +                               interrupt-map-mask = <0 0 0 0>;
1131 +                               interrupt-map = <0 0 0 0 &mpic 103>;
1132 +                               marvell,pcie-port = <3>;
1133 +                               marvell,pcie-lane = <0>;
1134 +                               clocks = <&gateclk 27>;
1135 +                               status = "disabled";
1136 +                       };
1137 +               };
1138 +
1139                 internal-regs {
1140                         pinctrl {
1141                                 compatible = "marvell,mv78460-pinctrl";
1142 @@ -112,194 +333,6 @@
1143                                 clocks = <&gateclk 1>;
1144                                 status = "disabled";
1145                         };
1146 -
1147 -                       /*
1148 -                        * MV78460 has 4 PCIe units Gen2.0: Two units can be
1149 -                        * configured as x4 or quad x1 lanes. Two units are
1150 -                        * x4/x1.
1151 -                        */
1152 -                       pcie-controller {
1153 -                               compatible = "marvell,armada-xp-pcie";
1154 -                               status = "disabled";
1155 -                               device_type = "pci";
1156 -
1157 -                               #address-cells = <3>;
1158 -                               #size-cells = <2>;
1159 -
1160 -                               bus-range = <0x00 0xff>;
1161 -
1162 -                               ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
1163 -                                       0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
1164 -                                       0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
1165 -                                       0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
1166 -                                       0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
1167 -                                       0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
1168 -                                       0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
1169 -                                       0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
1170 -                                       0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
1171 -                                       0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
1172 -                                       0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
1173 -                                       0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
1174 -
1175 -                               pcie@1,0 {
1176 -                                       device_type = "pci";
1177 -                                       assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
1178 -                                       reg = <0x0800 0 0 0 0>;
1179 -                                       #address-cells = <3>;
1180 -                                       #size-cells = <2>;
1181 -                                       #interrupt-cells = <1>;
1182 -                                       ranges;
1183 -                                       interrupt-map-mask = <0 0 0 0>;
1184 -                                       interrupt-map = <0 0 0 0 &mpic 58>;
1185 -                                       marvell,pcie-port = <0>;
1186 -                                       marvell,pcie-lane = <0>;
1187 -                                       clocks = <&gateclk 5>;
1188 -                                       status = "disabled";
1189 -                               };
1190 -
1191 -                               pcie@2,0 {
1192 -                                       device_type = "pci";
1193 -                                       assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
1194 -                                       reg = <0x1000 0 0 0 0>;
1195 -                                       #address-cells = <3>;
1196 -                                       #size-cells = <2>;
1197 -                                       #interrupt-cells = <1>;
1198 -                                       ranges;
1199 -                                       interrupt-map-mask = <0 0 0 0>;
1200 -                                       interrupt-map = <0 0 0 0 &mpic 59>;
1201 -                                       marvell,pcie-port = <0>;
1202 -                                       marvell,pcie-lane = <1>;
1203 -                                       clocks = <&gateclk 6>;
1204 -                                       status = "disabled";
1205 -                               };
1206 -
1207 -                               pcie@3,0 {
1208 -                                       device_type = "pci";
1209 -                                       assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
1210 -                                       reg = <0x1800 0 0 0 0>;
1211 -                                       #address-cells = <3>;
1212 -                                       #size-cells = <2>;
1213 -                                       #interrupt-cells = <1>;
1214 -                                       ranges;
1215 -                                       interrupt-map-mask = <0 0 0 0>;
1216 -                                       interrupt-map = <0 0 0 0 &mpic 60>;
1217 -                                       marvell,pcie-port = <0>;
1218 -                                       marvell,pcie-lane = <2>;
1219 -                                       clocks = <&gateclk 7>;
1220 -                                       status = "disabled";
1221 -                               };
1222 -
1223 -                               pcie@4,0 {
1224 -                                       device_type = "pci";
1225 -                                       assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
1226 -                                       reg = <0x2000 0 0 0 0>;
1227 -                                       #address-cells = <3>;
1228 -                                       #size-cells = <2>;
1229 -                                       #interrupt-cells = <1>;
1230 -                                       ranges;
1231 -                                       interrupt-map-mask = <0 0 0 0>;
1232 -                                       interrupt-map = <0 0 0 0 &mpic 61>;
1233 -                                       marvell,pcie-port = <0>;
1234 -                                       marvell,pcie-lane = <3>;
1235 -                                       clocks = <&gateclk 8>;
1236 -                                       status = "disabled";
1237 -                               };
1238 -
1239 -                               pcie@5,0 {
1240 -                                       device_type = "pci";
1241 -                                       assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
1242 -                                       reg = <0x2800 0 0 0 0>;
1243 -                                       #address-cells = <3>;
1244 -                                       #size-cells = <2>;
1245 -                                       #interrupt-cells = <1>;
1246 -                                       ranges;
1247 -                                       interrupt-map-mask = <0 0 0 0>;
1248 -                                       interrupt-map = <0 0 0 0 &mpic 62>;
1249 -                                       marvell,pcie-port = <1>;
1250 -                                       marvell,pcie-lane = <0>;
1251 -                                       clocks = <&gateclk 9>;
1252 -                                       status = "disabled";
1253 -                               };
1254 -
1255 -                               pcie@6,0 {
1256 -                                       device_type = "pci";
1257 -                                       assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
1258 -                                       reg = <0x3000 0 0 0 0>;
1259 -                                       #address-cells = <3>;
1260 -                                       #size-cells = <2>;
1261 -                                       #interrupt-cells = <1>;
1262 -                                       ranges;
1263 -                                       interrupt-map-mask = <0 0 0 0>;
1264 -                                       interrupt-map = <0 0 0 0 &mpic 63>;
1265 -                                       marvell,pcie-port = <1>;
1266 -                                       marvell,pcie-lane = <1>;
1267 -                                       clocks = <&gateclk 10>;
1268 -                                       status = "disabled";
1269 -                               };
1270 -
1271 -                               pcie@7,0 {
1272 -                                       device_type = "pci";
1273 -                                       assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
1274 -                                       reg = <0x3800 0 0 0 0>;
1275 -                                       #address-cells = <3>;
1276 -                                       #size-cells = <2>;
1277 -                                       #interrupt-cells = <1>;
1278 -                                       ranges;
1279 -                                       interrupt-map-mask = <0 0 0 0>;
1280 -                                       interrupt-map = <0 0 0 0 &mpic 64>;
1281 -                                       marvell,pcie-port = <1>;
1282 -                                       marvell,pcie-lane = <2>;
1283 -                                       clocks = <&gateclk 11>;
1284 -                                       status = "disabled";
1285 -                               };
1286 -
1287 -                               pcie@8,0 {
1288 -                                       device_type = "pci";
1289 -                                       assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
1290 -                                       reg = <0x4000 0 0 0 0>;
1291 -                                       #address-cells = <3>;
1292 -                                       #size-cells = <2>;
1293 -                                       #interrupt-cells = <1>;
1294 -                                       ranges;
1295 -                                       interrupt-map-mask = <0 0 0 0>;
1296 -                                       interrupt-map = <0 0 0 0 &mpic 65>;
1297 -                                       marvell,pcie-port = <1>;
1298 -                                       marvell,pcie-lane = <3>;
1299 -                                       clocks = <&gateclk 12>;
1300 -                                       status = "disabled";
1301 -                               };
1302 -                               pcie@9,0 {
1303 -                                       device_type = "pci";
1304 -                                       assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
1305 -                                       reg = <0x4800 0 0 0 0>;
1306 -                                       #address-cells = <3>;
1307 -                                       #size-cells = <2>;
1308 -                                       #interrupt-cells = <1>;
1309 -                                       ranges;
1310 -                                       interrupt-map-mask = <0 0 0 0>;
1311 -                                       interrupt-map = <0 0 0 0 &mpic 99>;
1312 -                                       marvell,pcie-port = <2>;
1313 -                                       marvell,pcie-lane = <0>;
1314 -                                       clocks = <&gateclk 26>;
1315 -                                       status = "disabled";
1316 -                               };
1317 -
1318 -                               pcie@10,0 {
1319 -                                       device_type = "pci";
1320 -                                       assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
1321 -                                       reg = <0x5000 0 0 0 0>;
1322 -                                       #address-cells = <3>;
1323 -                                       #size-cells = <2>;
1324 -                                       #interrupt-cells = <1>;
1325 -                                       ranges;
1326 -                                       interrupt-map-mask = <0 0 0 0>;
1327 -                                       interrupt-map = <0 0 0 0 &mpic 103>;
1328 -                                       marvell,pcie-port = <3>;
1329 -                                       marvell,pcie-lane = <0>;
1330 -                                       clocks = <&gateclk 27>;
1331 -                                       status = "disabled";
1332 -                               };
1333 -                       };
1334                 };
1335         };
1336  };
1337 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
1338 +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
1339 @@ -59,6 +59,15 @@
1340                         };
1341                 };
1342
1343 +               pcie-controller {
1344 +                       status = "okay";
1345 +                       /* Internal mini-PCIe connector */
1346 +                       pcie@1,0 {
1347 +                               /* Port 0, Lane 0 */
1348 +                               status = "okay";
1349 +                       };
1350 +               };
1351 +
1352                 internal-regs {
1353                         serial@12000 {
1354                                 clock-frequency = <250000000>;
1355 @@ -172,15 +181,6 @@
1356                         usb@51000 {
1357                                 status = "okay";
1358                         };
1359 -
1360 -                       pcie-controller {
1361 -                               status = "okay";
1362 -                               /* Internal mini-PCIe connector */
1363 -                               pcie@1,0 {
1364 -                                       /* Port 0, Lane 0 */
1365 -                                       status = "okay";
1366 -                               };
1367 -                       };
1368                 };
1369         };
1370  };