target/linux/mvebu/patches-3.10/0028-arm-mvebu-don-t-hardcode-a-physical-address-in-heads.patch

   1 From 88260610ea7a2c5a164721af28f59856880221b4 Mon Sep 17 00:00:00 2001
   2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   3 Date: Thu, 6 Jun 2013 12:24:28 +0200
   4 Subject: [PATCH 028/203] arm: mvebu: don't hardcode a physical address in
   5  headsmp.S
   6
   7 Now that the coherency_init() function is called a bit earlier, we can
   8 actually read the physical address of the coherency unit registers
   9 from the Device Tree, and communicate that to the headsmp.S code,
  10 which avoids hardcoding a physical address.
  11
  12 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  13 Acked-by: Arnd Bergmann <arnd@arndb.de>
  14 Reviewed-by: Will Deacon <will.deacon@arm.com>
  15 Acked-by: Nicolas Pitre <nico@linaro.org>
  16 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
  17 ---
  18  arch/arm/mach-mvebu/coherency.c | 12 ++++++++++++
  19  arch/arm/mach-mvebu/headsmp.S   | 16 ++++++++--------
  20  2 files changed, 20 insertions(+), 8 deletions(-)
  21
  22 --- a/arch/arm/mach-mvebu/coherency.c
  23 +++ b/arch/arm/mach-mvebu/coherency.c
  24 @@ -25,8 +25,10 @@
  25  #include <linux/dma-mapping.h>
  26  #include <linux/platform_device.h>
  27  #include <asm/smp_plat.h>
  28 +#include <asm/cacheflush.h>
  29  #include "armada-370-xp.h"
  30
  31 +unsigned long __cpuinitdata coherency_phys_base;
  32  static void __iomem *coherency_base;
  33  static void __iomem *coherency_cpu_base;
  34
  35 @@ -124,7 +126,17 @@ int __init coherency_init(void)
  36
  37         np = of_find_matching_node(NULL, of_coherency_table);
  38         if (np) {
  39 +               struct resource res;
  40                 pr_info("Initializing Coherency fabric\n");
  41 +               of_address_to_resource(np, 0, &res);
  42 +               coherency_phys_base = res.start;
  43 +               /*
  44 +                * Ensure secondary CPUs will see the updated value,
  45 +                * which they read before they join the coherency
  46 +                * fabric, and therefore before they are coherent with
  47 +                * the boot CPU cache.
  48 +                */
  49 +               sync_cache_w(&coherency_phys_base);
  50                 coherency_base = of_iomap(np, 0);
  51                 coherency_cpu_base = of_iomap(np, 1);
  52                 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
  53 --- a/arch/arm/mach-mvebu/headsmp.S
  54 +++ b/arch/arm/mach-mvebu/headsmp.S
  55 @@ -21,12 +21,6 @@
  56  #include <linux/linkage.h>
  57  #include <linux/init.h>
  58
  59 -/*
  60 - * At this stage the secondary CPUs don't have acces yet to the MMU, so
  61 - * we have to provide physical addresses
  62 - */
  63 -#define ARMADA_XP_CFB_BASE          0xD0020200
  64 -
  65         __CPUINIT
  66
  67  /*
  68 @@ -35,15 +29,21 @@
  69   * startup
  70   */
  71  ENTRY(armada_xp_secondary_startup)
  72 +       /* Get coherency fabric base physical address */
  73 +       adr     r0, 1f
  74 +       ldr     r1, [r0]
  75 +       ldr     r0, [r0, r1]
  76
  77         /* Read CPU id */
  78         mrc     p15, 0, r1, c0, c0, 5
  79         and     r1, r1, #0xF
  80
  81         /* Add CPU to coherency fabric */
  82 -       ldr     r0, =ARMADA_XP_CFB_BASE
  83 -
  84         bl      ll_set_cpu_coherent
  85         b       secondary_startup
  86
  87  ENDPROC(armada_xp_secondary_startup)
  88 +
  89 +       .align 2
  90 +1:
  91 +       .long   coherency_phys_base - .