mvebu: add SolidRun ClearFog A1 support
[openwrt.git] / target / linux / mvebu / files / arch / arm / boot / dts / armada-388-clearfog.dts
1 /*
2  * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
3  *
4  *  Copyright (C) 2015 Russell King
5  *
6  * This board is in development; the contents of this file work with
7  * the A1 rev 2.0 of the board, which does not represent final
8  * production board.  Things will change, don't expect this file to
9  * remain compatible info the future.
10  *
11  * This file is dual-licensed: you can use it either under the terms
12  * of the GPL or the X11 license, at your option. Note that this dual
13  * licensing only applies to this file, and not this project as a
14  * whole.
15  *
16  *  a) This file is free software; you can redistribute it and/or
17  *     modify it under the terms of the GNU General Public License
18  *     version 2 as published by the Free Software Foundation.
19  *
20  *     This file is distributed in the hope that it will be useful
21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *     GNU General Public License for more details.
24  *
25  * Or, alternatively
26  *
27  *  b) Permission is hereby granted, free of charge, to any person
28  *     obtaining a copy of this software and associated documentation
29  *     files (the "Software"), to deal in the Software without
30  *     restriction, including without limitation the rights to use
31  *     copy, modify, merge, publish, distribute, sublicense, and/or
32  *     sell copies of the Software, and to permit persons to whom the
33  *     Software is furnished to do so, subject to the following
34  *     conditions:
35  *
36  *     The above copyright notice and this permission notice shall be
37  *     included in all copies or substantial portions of the Software.
38  *
39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46  *     OTHER DEALINGS IN THE SOFTWARE.
47  */
48
49 /dts-v1/;
50 #include "armada-388.dtsi"
51 #include "armada-38x-solidrun-microsom.dtsi"
52
53 / {
54         model = "SolidRun Clearfog A1";
55         compatible = "solidrun,clearfog-a1", "marvell,armada388",
56                 "marvell,armada385", "marvell,armada380";
57
58         aliases {
59                 /* So that mvebu u-boot can update the MAC addresses */
60                 ethernet1 = &eth0;
61                 ethernet2 = &eth1;
62                 ethernet3 = &eth2;
63         };
64
65         chosen {
66                 stdout-path = "serial0:115200n8";
67         };
68
69         reg_3p3v: regulator-3p3v {
70                 compatible = "regulator-fixed";
71                 regulator-name = "3P3V";
72                 regulator-min-microvolt = <3300000>;
73                 regulator-max-microvolt = <3300000>;
74                 regulator-always-on;
75         };
76
77         soc {
78                 internal-regs {
79                         ethernet@30000 {
80                                 phy-mode = "sgmii";
81                                 status = "okay";
82
83                                 fixed-link {
84                                         speed = <1000>;
85                                         full-duplex;
86                                 };
87                         };
88
89                         ethernet@34000 {
90                                 phy-mode = "sgmii";
91                                 status = "okay";
92
93                                 fixed-link {
94                                         speed = <1000>;
95                                         full-duplex;
96                                 };
97                         };
98
99                         i2c@11000 {
100                                 /* Is there anything on this? */
101                                 clock-frequency = <100000>;
102                                 pinctrl-0 = <&i2c0_pins>;
103                                 pinctrl-names = "default";
104                                 status = "okay";
105
106                                 /*
107                                  * PCA9655 GPIO expander, up to 1MHz clock.
108                                  *  0-CON3 CLKREQ#
109                                  *  1-CON3 PERST#
110                                  *  2-CON2 PERST#
111                                  *  3-CON3 W_DISABLE
112                                  *  4-CON2 CLKREQ#
113                                  *  5-USB3 overcurrent
114                                  *  6-USB3 power
115                                  *  7-CON2 W_DISABLE
116                                  *  8-JP4 P1
117                                  *  9-JP4 P4
118                                  * 10-JP4 P5
119                                  * 11-m.2 DEVSLP
120                                  * 12-SFP_LOS
121                                  * 13-SFP_TX_FAULT
122                                  * 14-SFP_TX_DISABLE
123                                  * 15-SFP_MOD_DEF0
124                                  */
125                                 expander0: gpio-expander@20 {
126                                         /*
127                                          * This is how it should be:
128                                          * compatible = "onnn,pca9655",
129                                          *       "nxp,pca9555";
130                                          * but you can't do this because of
131                                          * the way I2C works.
132                                          */
133                                         compatible = "nxp,pca9555";
134                                         gpio-controller;
135                                         #gpio-cells = <2>;
136                                         reg = <0x20>;
137
138                                         pcie1_0_clkreq {
139                                                 gpio-hog;
140                                                 gpios = <0 GPIO_ACTIVE_LOW>;
141                                                 input;
142                                                 line-name = "pcie1.0-clkreq";
143                                         };
144                                         pcie1_0_w_disable {
145                                                 gpio-hog;
146                                                 gpios = <3 GPIO_ACTIVE_LOW>;
147                                                 output-low;
148                                                 line-name = "pcie1.0-w-disable";
149                                         };
150                                         pcie2_0_clkreq {
151                                                 gpio-hog;
152                                                 gpios = <4 GPIO_ACTIVE_LOW>;
153                                                 input;
154                                                 line-name = "pcie2.0-clkreq";
155                                         };
156                                         pcie2_0_w_disable {
157                                                 gpio-hog;
158                                                 gpios = <7 GPIO_ACTIVE_LOW>;
159                                                 output-low;
160                                                 line-name = "pcie2.0-w-disable";
161                                         };
162                                         usb3_ilimit {
163                                                 gpio-hog;
164                                                 gpios = <5 GPIO_ACTIVE_LOW>;
165                                                 input;
166                                                 line-name = "usb3-current-limit";
167                                         };
168                                         usb3_power {
169                                                 gpio-hog;
170                                                 gpios = <6 GPIO_ACTIVE_HIGH>;
171                                                 output-high;
172                                                 line-name = "usb3-power";
173                                         };
174                                         m2_devslp {
175                                                 gpio-hog;
176                                                 gpios = <11 GPIO_ACTIVE_HIGH>;
177                                                 output-low;
178                                                 line-name = "m.2 devslp";
179                                         };
180                                         sfp_los {
181                                                 /* SFP loss of signal */
182                                                 gpio-hog;
183                                                 gpios = <12 GPIO_ACTIVE_HIGH>;
184                                                 input;
185                                                 line-name = "sfp-los";
186                                         };
187                                         sfp_tx_fault {
188                                                 /* SFP laser fault */
189                                                 gpio-hog;
190                                                 gpios = <13 GPIO_ACTIVE_HIGH>;
191                                                 input;
192                                                 line-name = "sfp-tx-fault";
193                                         };
194                                         sfp_tx_disable {
195                                                 /* SFP transmit disable */
196                                                 gpio-hog;
197                                                 gpios = <14 GPIO_ACTIVE_HIGH>;
198                                                 output-low;
199                                                 line-name = "sfp-tx-disable";
200                                         };
201                                         sfp_mod_def0 {
202                                                 /* SFP module present */
203                                                 gpio-hog;
204                                                 gpios = <15 GPIO_ACTIVE_LOW>;
205                                                 input;
206                                                 line-name = "sfp-mod-def0";
207                                         };
208                                 };
209
210                                 /* The MCP3021 is 100kHz clock only */
211                                 mikrobus_adc: mcp3021@4c {
212                                         compatible = "microchip,mcp3021";
213                                         reg = <0x4c>;
214                                 };
215
216                                 /* Also something at 0x64 */
217                         };
218
219                         i2c@11100 {
220                                 /*
221                                  * Routed to SFP, mikrobus, and PCIe.
222                                  * SFP limits this to 100kHz, and requires
223                                  *  an AT24C01A/02/04 with address pins tied
224                                  *  low, which takes addresses 0x50 and 0x51.
225                                  * Mikrobus doesn't specify beyond an I2C
226                                  *  bus being present.
227                                  * PCIe uses ARP to assign addresses, or
228                                  *  0x63-0x64.
229                                  */
230                                 clock-frequency = <100000>;
231                                 pinctrl-0 = <&clearfog_i2c1_pins>;
232                                 pinctrl-names = "default";
233                                 status = "okay";
234                         };
235
236                         mdio@72004 {
237                                 pinctrl-0 = <&mdio_pins>;
238                                 pinctrl-names = "default";
239
240                                 phy_dedicated: ethernet-phy@0 {
241                                         /*
242                                          * Annoyingly, the marvell phy driver
243                                          * configures the LED register, rather
244                                          * than preserving reset-loaded setting.
245                                          * We undo that rubbish here.
246                                          */
247                                         marvell,reg-init = <3 16 0 0x101e>;
248                                         reg = <0>;
249                                 };
250                         };
251
252                         pinctrl@18000 {
253                                 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
254                                         marvell,pins = "mpp46";
255                                         marvell,function = "ref";
256                                 };
257                                 clearfog_dsa0_pins: clearfog-dsa0-pins {
258                                         marvell,pins = "mpp23", "mpp41";
259                                         marvell,function = "gpio";
260                                 };
261                                 clearfog_i2c1_pins: i2c1-pins {
262                                         /* SFP, PCIe, mSATA, mikrobus */
263                                         marvell,pins = "mpp26", "mpp27";
264                                         marvell,function = "i2c1";
265                                 };
266                                 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
267                                         marvell,pins = "mpp20";
268                                         marvell,function = "gpio";
269                                 };
270                                 clearfog_sdhci_pins: clearfog-sdhci-pins {
271                                         marvell,pins = "mpp21", "mpp28",
272                                                        "mpp37", "mpp38",
273                                                        "mpp39", "mpp40";
274                                         marvell,function = "sd0";
275                                 };
276                                 clearfog_spi1_cs_pins: spi1-cs-pins {
277                                         marvell,pins = "mpp55";
278                                         marvell,function = "spi1";
279                                 };
280                                 mikro_pins: mikro-pins {
281                                         /* int: mpp22 rst: mpp29 */
282                                         marvell,pins = "mpp22", "mpp29";
283                                         marvell,function = "gpio";
284                                 };
285                                 mikro_spi_pins: mikro-spi-pins {
286                                         marvell,pins = "mpp43";
287                                         marvell,function = "spi1";
288                                 };
289                                 mikro_uart_pins: mikro-uart-pins {
290                                         marvell,pins = "mpp24", "mpp25";
291                                         marvell,function = "ua1";
292                                 };
293                                 rear_button_pins: rear-button-pins {
294                                         marvell,pins = "mpp34";
295                                         marvell,function = "gpio";
296                                 };
297                         };
298
299                         sata@a8000 {
300                                 /* pinctrl? */
301                                 status = "okay";
302                         };
303
304                         sata@e0000 {
305                                 /* pinctrl? */
306                                 status = "okay";
307                         };
308
309                         sdhci@d8000 {
310                                 bus-width = <4>;
311                                 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
312                                 no-1-8-v;
313                                 pinctrl-0 = <&clearfog_sdhci_pins
314                                              &clearfog_sdhci_cd_pins>;
315                                 pinctrl-names = "default";
316                                 status = "okay";
317                                 vmmc = <&reg_3p3v>;
318                                 wp-inverted;
319                         };
320
321                         serial@12100 {
322                                 /* mikrobus uart */
323                                 pinctrl-0 = <&mikro_uart_pins>;
324                                 pinctrl-names = "default";
325                                 status = "okay";
326                         };
327
328                         spi@10680 {
329                                 /*
330                                  * We don't seem to have the W25Q32 on the
331                                  * A1 Rev 2.0 boards, so disable SPI.
332                                  * CS0: W25Q32 (doesn't appear to be present)
333                                  * CS1:
334                                  * CS2: mikrobus
335                                  */
336                                 pinctrl-0 = <&spi1_pins
337                                              &clearfog_spi1_cs_pins
338                                              &mikro_spi_pins>;
339                                 pinctrl-names = "default";
340                                 status = "okay";
341
342                                 spi-flash@0 {
343                                         #address-cells = <1>;
344                                         #size-cells = <0>;
345                                         compatible = "w25q32", "jedec,spi-nor";
346                                         reg = <0>; /* Chip select 0 */
347                                         spi-max-frequency = <3000000>;
348                                         status = "disabled";
349                                 };
350                         };
351
352                         usb@58000 {
353                                 /* CON3, nearest  power. */
354                                 status = "okay";
355                         };
356
357                         usb3@f0000 {
358                                 /* CON2, nearest CPU, USB2 only. */
359                                 status = "okay";
360                         };
361
362                         usb3@f8000 {
363                                 /* CON7 */
364                                 status = "okay";
365                         };
366                 };
367
368                 pcie-controller {
369                         status = "okay";
370                         /*
371                          * The two PCIe units are accessible through
372                          * the mini-PCIe connectors on the board.
373                          */
374                         pcie@2,0 {
375                                 /* Port 1, Lane 0. CON3, nearest power. */
376                                 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
377                                 status = "okay";
378                         };
379                         pcie@3,0 {
380                                 /* Port 2, Lane 0. CON2, nearest CPU. */
381                                 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
382                                 status = "okay";
383                         };
384                 };
385         };
386
387         dsa@0 {
388                 compatible = "marvell,dsa";
389                 dsa,ethernet = <&eth1>;
390                 dsa,mii-bus = <&mdio>;
391                 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
392                 pinctrl-names = "default";
393                 #address-cells = <2>;
394                 #size-cells = <0>;
395
396                 switch@0 {
397                         #address-cells = <1>;
398                         #size-cells = <0>;
399                         reg = <4 0>;
400
401                         port@0 {
402                                 reg = <0>;
403                                 label = "lan1";
404                         };
405
406                         port@1 {
407                                 reg = <1>;
408                                 label = "lan2";
409                         };
410
411                         port@2 {
412                                 reg = <2>;
413                                 label = "lan3";
414                         };
415
416                         port@3 {
417                                 reg = <3>;
418                                 label = "lan4";
419                         };
420
421                         port@4 {
422                                 reg = <4>;
423                                 label = "lan5";
424                         };
425
426                         port@5 {
427                                 reg = <5>;
428                                 label = "cpu";
429                         };
430
431                         port@6 {
432                                 /* 88E1512 external phy */
433                                 reg = <6>;
434                                 label = "lan6";
435                                 fixed-link {
436                                         speed = <1000>;
437                                         full-duplex;
438                                 };
439                         };
440                 };
441         };
442
443         gpio-keys {
444                 compatible = "gpio-keys";
445                 pinctrl-0 = <&rear_button_pins>;
446                 pinctrl-names = "default";
447
448                 button_0 {
449                         /* The rear SW3 button */
450                         label = "Rear Button";
451                         gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
452                         linux,can-disable;
453                         linux,code = <BTN_0>;
454                 };
455         };
456 };