target/linux/mpc85xx/patches-3.18/140-powerpc-85xx-tl-wdr4900-v1-support.patch

   1 From 406d86e5990ac171f18ef6e2973672d8fbfe1556 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Wed, 20 Feb 2013 08:40:33 +0100
   4 Subject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1
   5  board
   6
   7 This patch adds support for the TP-Link TL-WDR4900 v1
   8 concurrent dual-band wireless router. The devices uses
   9 the Freescale P1014 SoC.
  10
  11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  12 ---
  13  arch/powerpc/boot/Makefile                  |   3 +
  14  arch/powerpc/boot/cuboot-tl-wdr4900-v1.c    | 164 +++++++++++++++++++++
  15  arch/powerpc/boot/dts/tl-wdr4900-v1.dts     | 212 ++++++++++++++++++++++++++++
  16  arch/powerpc/boot/wrapper                   |   4 +
  17  arch/powerpc/platforms/85xx/Kconfig         |  11 ++
  18  arch/powerpc/platforms/85xx/Makefile        |   1 +
  19  arch/powerpc/platforms/85xx/tl_wdr4900_v1.c | 145 +++++++++++++++++++
  20  7 files changed, 540 insertions(+)
  21  create mode 100644 arch/powerpc/boot/cuboot-tl-wdr4900-v1.c
  22  create mode 100644 arch/powerpc/boot/dts/tl-wdr4900-v1.dts
  23  create mode 100644 arch/powerpc/platforms/85xx/tl_wdr4900_v1.c
  24
  25 --- a/arch/powerpc/boot/Makefile
  26 +++ b/arch/powerpc/boot/Makefile
  27 @@ -112,6 +112,7 @@ src-plat-$(CONFIG_PPC_POWERNV) += pserie
  28  src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
  29  src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
  30  src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
  31 +src-plat-$(CONFIG_TL_WDR4900_V1) += cuboot-tl-wdr4900-v1.c
  32
  33  src-wlib := $(sort $(src-wlib-y))
  34  src-plat := $(sort $(src-plat-y))
  35 @@ -296,6 +297,7 @@ image-$(CONFIG_TQM8555)                     += cuImage.tqm
  36  image-$(CONFIG_TQM8560)                        += cuImage.tqm8560
  37  image-$(CONFIG_SBC8548)                        += cuImage.sbc8548
  38  image-$(CONFIG_KSI8560)                        += cuImage.ksi8560
  39 +image-$(CONFIG_TL_WDR4900_V1)          += cuImage.tl-wdr4900-v1
  40
  41  # Board ports in arch/powerpc/platform/embedded6xx/Kconfig
  42  image-$(CONFIG_STORCENTER)             += cuImage.storcenter
  43 --- /dev/null
  44 +++ b/arch/powerpc/boot/cuboot-tl-wdr4900-v1.c
  45 @@ -0,0 +1,164 @@
  46 +/*
  47 + * U-Boot compatibility wrapper for the TP-Link TL-WDR4900 v1 board
  48 + *
  49 + * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
  50 + *
  51 + * Based on:
  52 + *  cuboot-85xx.c
  53 + *     Author: Scott Wood <scottwood@freescale.com>
  54 + *     Copyright (c) 2007 Freescale Semiconductor, Inc.
  55 + *
  56 + *  simpleboot.c
  57 + *     Authors: Scott Wood <scottwood@freescale.com>
  58 + *              Grant Likely <grant.likely@secretlab.ca>
  59 + *     Copyright (c) 2007 Freescale Semiconductor, Inc.
  60 + *     Copyright (c) 2008 Secret Lab Technologies Ltd.
  61 + *
  62 + * This program is free software; you can redistribute it and/or modify it
  63 + * under the terms of the GNU General Public License version 2 as published
  64 + * by the Free Software Foundation.
  65 + */
  66 +
  67 +#include "ops.h"
  68 +#include "types.h"
  69 +#include "io.h"
  70 +#include "stdio.h"
  71 +#include <libfdt.h>
  72 +
  73 +BSS_STACK(4*1024);
  74 +
  75 +static unsigned long bus_freq;
  76 +static unsigned long int_freq;
  77 +static u64 mem_size;
  78 +static unsigned char enetaddr[6];
  79 +
  80 +static void process_boot_dtb(void *boot_dtb)
  81 +{
  82 +       const u32 *na, *ns, *reg, *val32;
  83 +       const char *path;
  84 +       u64 memsize64;
  85 +       int node, size, i;
  86 +
  87 +       /* Make sure FDT blob is sane */
  88 +       if (fdt_check_header(boot_dtb) != 0)
  89 +               fatal("Invalid device tree blob\n");
  90 +
  91 +       /* Find the #address-cells and #size-cells properties */
  92 +       node = fdt_path_offset(boot_dtb, "/");
  93 +       if (node < 0)
  94 +               fatal("Cannot find root node\n");
  95 +       na = fdt_getprop(boot_dtb, node, "#address-cells", &size);
  96 +       if (!na || (size != 4))
  97 +               fatal("Cannot find #address-cells property");
  98 +
  99 +       ns = fdt_getprop(boot_dtb, node, "#size-cells", &size);
 100 +       if (!ns || (size != 4))
 101 +               fatal("Cannot find #size-cells property");
 102 +
 103 +       /* Find the memory range */
 104 +       node = fdt_node_offset_by_prop_value(boot_dtb, -1, "device_type",
 105 +                                            "memory", sizeof("memory"));
 106 +       if (node < 0)
 107 +               fatal("Cannot find memory node\n");
 108 +       reg = fdt_getprop(boot_dtb, node, "reg", &size);
 109 +       if (size < (*na+*ns) * sizeof(u32))
 110 +               fatal("cannot get memory range\n");
 111 +
 112 +       /* Only interested in memory based at 0 */
 113 +       for (i = 0; i < *na; i++)
 114 +               if (*reg++ != 0)
 115 +                       fatal("Memory range is not based at address 0\n");
 116 +
 117 +       /* get the memsize and trucate it to under 4G on 32 bit machines */
 118 +       memsize64 = 0;
 119 +       for (i = 0; i < *ns; i++)
 120 +               memsize64 = (memsize64 << 32) | *reg++;
 121 +       if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
 122 +               memsize64 = 0xffffffff;
 123 +
 124 +       mem_size = memsize64;
 125 +
 126 +       /* get clock frequencies */
 127 +       node = fdt_node_offset_by_prop_value(boot_dtb, -1, "device_type",
 128 +                                            "cpu", sizeof("cpu"));
 129 +       if (!node)
 130 +               fatal("Cannot find cpu node\n");
 131 +
 132 +       val32 = fdt_getprop(boot_dtb, node, "clock-frequency", &size);
 133 +       if (!val32 || (size != 4))
 134 +               fatal("Cannot get clock frequency");
 135 +
 136 +       int_freq = *val32;
 137 +
 138 +       val32 = fdt_getprop(boot_dtb, node, "bus-frequency", &size);
 139 +       if (!val32 || (size != 4))
 140 +               fatal("Cannot get bus frequency");
 141 +
 142 +       bus_freq = *val32;
 143 +
 144 +       path = fdt_get_alias(boot_dtb, "ethernet0");
 145 +       if (path) {
 146 +               const void *p;
 147 +
 148 +               node = fdt_path_offset(boot_dtb, path);
 149 +               if (node < 0)
 150 +                       fatal("Cannot find ethernet0 node");
 151 +
 152 +               p = fdt_getprop(boot_dtb, node, "mac-address", &size);
 153 +               if (!p || (size < 6)) {
 154 +                       printf("no mac-address property, finding local\n\r");
 155 +                       p = fdt_getprop(boot_dtb, node, "local-mac-address", &size);
 156 +               }
 157 +
 158 +               if (!p || (size < 6))
 159 +                       fatal("cannot get MAC addres");
 160 +
 161 +               memcpy(enetaddr, p, sizeof(enetaddr));
 162 +       }
 163 +}
 164 +
 165 +static void platform_fixups(void)
 166 +{
 167 +       void *soc;
 168 +
 169 +       dt_fixup_memory(0, mem_size);
 170 +
 171 +       dt_fixup_mac_address_by_alias("ethernet0", enetaddr);
 172 +       dt_fixup_cpu_clocks(int_freq, bus_freq / 8, bus_freq);
 173 +
 174 +       /* Unfortunately, the specific model number is encoded in the
 175 +        * soc node name in existing dts files -- once that is fixed,
 176 +        * this can do a simple path lookup.
 177 +        */
 178 +       soc = find_node_by_devtype(NULL, "soc");
 179 +       if (soc) {
 180 +               void *serial = NULL;
 181 +
 182 +               setprop(soc, "bus-frequency", &bus_freq, sizeof(bus_freq));
 183 +
 184 +               while ((serial = find_node_by_devtype(serial, "serial"))) {
 185 +                       if (get_parent(serial) != soc)
 186 +                               continue;
 187 +
 188 +                       setprop(serial, "clock-frequency", &bus_freq,
 189 +                               sizeof(bus_freq));
 190 +               }
 191 +       }
 192 +}
 193 +
 194 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 195 +                   unsigned long r6, unsigned long r7)
 196 +{
 197 +       mem_size = 64 * 1024 * 1024;
 198 +
 199 +       simple_alloc_init(_end, mem_size - (u32)_end - 1024*1024, 32, 64);
 200 +
 201 +       fdt_init(_dtb_start);
 202 +       serial_console_init();
 203 +
 204 +       printf("\n\r-- TL-WDR4900 v1 boot wrapper --\n\r");
 205 +
 206 +       process_boot_dtb((void *) r3);
 207 +
 208 +       platform_ops.fixups = platform_fixups;
 209 +}
 210 --- /dev/null
 211 +++ b/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
 212 @@ -0,0 +1,212 @@
 213 +/*
 214 + * TP-Link TL-WDR4900 v1 Device Tree Source
 215 + *
 216 + * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
 217 + *
 218 + * This program is free software; you can redistribute  it and/or modify it
 219 + * under  the terms of  the GNU General  Public License as published by the
 220 + * Free Software Foundation;  either version 2 of the  License, or (at your
 221 + * option) any later version.
 222 + */
 223 +
 224 +/include/ "fsl/p1010si-pre.dtsi"
 225 +
 226 +/ {
 227 +       model = "TP-Link TL-WDR4900 v1";
 228 +       compatible = "tp-link,TL-WDR4900v1";
 229 +
 230 +       chosen {
 231 +               bootargs = "console=ttyS0,115200";
 232 +/*
 233 +               linux,stdout-path = "/soc@ffe00000/serial@4500";
 234 +*/
 235 +       };
 236 +
 237 +       aliases {
 238 +               spi0 = &spi0;
 239 +       };
 240 +
 241 +       memory {
 242 +               device_type = "memory";
 243 +       };
 244 +
 245 +       soc: soc@ffe00000 {
 246 +               ranges = <0x0 0x0 0xffe00000 0x100000>;
 247 +
 248 +               spi0: spi@7000 {
 249 +                       flash@0 {
 250 +                               #address-cells = <1>;
 251 +                               #size-cells = <1>;
 252 +                               compatible = "spansion,s25fl129p1";
 253 +                               reg = <0>;
 254 +                               spi-max-frequency = <25000000>;
 255 +
 256 +                               u-boot@0 {
 257 +                                       reg = <0x0 0x0050000>;
 258 +                                       label = "u-boot";
 259 +                                       read-only;
 260 +                               };
 261 +
 262 +                               dtb@50000 {
 263 +                                       reg = <0x00050000 0x00010000>;
 264 +                                       label = "dtb";
 265 +                                       read-only;
 266 +                               };
 267 +
 268 +                               kernel@60000 {
 269 +                                       reg = <0x00060000 0x002a0000>;
 270 +                                       label = "kernel";
 271 +                               };
 272 +
 273 +                               rootfs@300000 {
 274 +                                       reg = <0x00300000 0x00ce0000>;
 275 +                                       label = "rootfs";
 276 +                               };
 277 +
 278 +                               config@fe0000 {
 279 +                                       reg = <0x00fe0000 0x00010000>;
 280 +                                       label = "config";
 281 +                                       read-only;
 282 +                               };
 283 +
 284 +                               caldata@ff0000 {
 285 +                                       reg = <0x00ff0000 0x00010000>;
 286 +                                       label = "caldata";
 287 +                                       read-only;
 288 +                               };
 289 +
 290 +                               firmware@60000 {
 291 +                                       reg = <0x00060000 0x00f80000>;
 292 +                                       label = "firmware";
 293 +                               };
 294 +                       };
 295 +               };
 296 +
 297 +               gpio0: gpio-controller@f000 {
 298 +               };
 299 +
 300 +               usb@22000 {
 301 +                       phy_type = "utmi";
 302 +                       dr_mode = "host";
 303 +               };
 304 +
 305 +               mdio@24000 {
 306 +                       phy0: ethernet-phy@0 {
 307 +                               reg = <0x0>;
 308 +                               qca,ar8327-initvals = <
 309 +                                       0x00004 0x07600000 /* PAD0_MODE */
 310 +                                       0x00008 0x00000000 /* PAD5_MODE */
 311 +                                       0x0000c 0x01000000 /* PAD6_MODE */
 312 +                                       0x00010 0x40000000 /* POWER_ON_STRIP */
 313 +                                       0x00050 0xcf35cf35 /* LED_CTRL0 */
 314 +                                       0x00054 0xcf35cf35 /* LED_CTRL1 */
 315 +                                       0x00058 0xcf35cf35 /* LED_CTRL2 */
 316 +                                       0x0005c 0x03ffff00 /* LED_CTRL3 */
 317 +                                       0x0007c 0x0000007e /* PORT0_STATUS */
 318 +                               >;
 319 +                       };
 320 +               };
 321 +
 322 +               mdio@25000 {
 323 +                       status = "disabled";
 324 +               };
 325 +
 326 +               mdio@26000 {
 327 +                       status = "disabled";
 328 +               };
 329 +
 330 +               enet0: ethernet@b0000 {
 331 +                       phy-handle = <&phy0>;
 332 +                       phy-connection-type = "rgmii-id";
 333 +               };
 334 +
 335 +               enet1: ethernet@b1000 {
 336 +                       status = "disabled";
 337 +               };
 338 +
 339 +               enet2: ethernet@b2000 {
 340 +                       status = "disabled";
 341 +               };
 342 +
 343 +               sdhc@2e000 {
 344 +                       status = "disabled";
 345 +               };
 346 +
 347 +               serial1: serial@4600 {
 348 +                       status = "disabled";
 349 +               };
 350 +
 351 +               can0: can@1c000 {
 352 +                       status = "disabled";
 353 +               };
 354 +
 355 +               can1: can@1d000 {
 356 +                       status = "disabled";
 357 +               };
 358 +       };
 359 +
 360 +       pci0: pcie@ffe09000 {
 361 +               reg = <0 0xffe09000 0 0x1000>;
 362 +               ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 363 +                         0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
 364 +               pcie@0 {
 365 +                       ranges = <0x2000000 0x0 0xa0000000
 366 +                                 0x2000000 0x0 0xa0000000
 367 +                                 0x0 0x20000000
 368 +
 369 +                                 0x1000000 0x0 0x0
 370 +                                 0x1000000 0x0 0x0
 371 +                                 0x0 0x100000>;
 372 +               };
 373 +       };
 374 +
 375 +       pci1: pcie@ffe0a000 {
 376 +               reg = <0 0xffe0a000 0 0x1000>;
 377 +               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 378 +                         0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
 379 +               pcie@0 {
 380 +                       ranges = <0x2000000 0x0 0x80000000
 381 +                                 0x2000000 0x0 0x80000000
 382 +                                 0x0 0x20000000
 383 +
 384 +                                 0x1000000 0x0 0x0
 385 +                                 0x1000000 0x0 0x0
 386 +                                 0x0 0x100000>;
 387 +               };
 388 +       };
 389 +
 390 +       ifc: ifc@ffe1e000 {
 391 +               status = "disabled";
 392 +       };
 393 +
 394 +       leds {
 395 +               compatible = "gpio-leds";
 396 +
 397 +               system {
 398 +                       gpios = <&gpio0 2 1>; /* active low */
 399 +                       label = "tp-link:blue:system";
 400 +               };
 401 +
 402 +               usb1 {
 403 +                       gpios = <&gpio0 3 1>; /* active low */
 404 +                       label = "tp-link:green:usb1";
 405 +               };
 406 +
 407 +               usb2 {
 408 +                       gpios = <&gpio0 4 1>; /* active low */
 409 +                       label = "tp-link:green:usb2";
 410 +               };
 411 +       };
 412 +
 413 +       buttons {
 414 +               compatible = "gpio-keys";
 415 +
 416 +               reset {
 417 +                       label = "Reset button";
 418 +                       gpios = <&gpio0 5 1>; /* active low */
 419 +                       linux,code = <0x198>; /* KEY_RESTART */
 420 +               };
 421 +       };
 422 +};
 423 +
 424 +/include/ "fsl/p1010si-post.dtsi"
 425 --- a/arch/powerpc/boot/wrapper
 426 +++ b/arch/powerpc/boot/wrapper
 427 @@ -218,6 +218,10 @@ cuboot*)
 428      *-mpc85*|*-tqm85*|*-sbc85*)
 429          platformo=$object/cuboot-85xx.o
 430          ;;
 431 +    *-tl-wdr4900-v1)
 432 +        platformo=$object/cuboot-tl-wdr4900-v1.o
 433 +       link_address='0x1000000'
 434 +        ;;
 435      *-amigaone)
 436          link_address='0x800000'
 437          ;;
 438 --- a/arch/powerpc/platforms/85xx/Kconfig
 439 +++ b/arch/powerpc/platforms/85xx/Kconfig
 440 @@ -168,6 +168,17 @@ config STX_GP3
 441         select CPM2
 442         select DEFAULT_UIMAGE
 443
 444 +config TL_WDR4900_V1
 445 +       bool "TP-Link TL-WDR4900 v1"
 446 +       select DEFAULT_UIMAGE
 447 +       select ARCH_REQUIRE_GPIOLIB
 448 +       select GPIO_MPC8XXX
 449 +       help
 450 +         This option enables support for the TP-Link TL-WDR4900 v1 board.
 451 +
 452 +         This board is a Concurrent Dual-Band wireless router with a
 453 +         Freescale P1014 SoC.
 454 +
 455  config TQM8540
 456         bool "TQ Components TQM8540"
 457         help
 458 --- a/arch/powerpc/platforms/85xx/Makefile
 459 +++ b/arch/powerpc/platforms/85xx/Makefile
 460 @@ -23,6 +23,7 @@ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
 461  obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
 462  obj-$(CONFIG_STX_GP3)    += stx_gp3.o
 463  obj-$(CONFIG_TQM85xx)    += tqm85xx.o
 464 +obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o
 465  obj-$(CONFIG_SBC8548)     += sbc8548.o
 466  obj-$(CONFIG_PPA8548)     += ppa8548.o
 467  obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o
 468 --- /dev/null
 469 +++ b/arch/powerpc/platforms/85xx/tl_wdr4900_v1.c
 470 @@ -0,0 +1,145 @@
 471 +/*
 472 + * TL-WDR4900 v1 board setup
 473 + *
 474 + * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
 475 + *
 476 + * Based on:
 477 + *   p1010rdb.c:
 478 + *      P1010RDB Board Setup
 479 + *      Copyright 2011 Freescale Semiconductor Inc.
 480 + *
 481 + * This program is free software; you can redistribute  it and/or modify it
 482 + * under  the terms of  the GNU General  Public License as published by the
 483 + * Free Software Foundation;  either version 2 of the  License, or (at your
 484 + * option) any later version.
 485 + */
 486 +
 487 +#include <linux/stddef.h>
 488 +#include <linux/kernel.h>
 489 +#include <linux/pci.h>
 490 +#include <linux/delay.h>
 491 +#include <linux/interrupt.h>
 492 +#include <linux/of_platform.h>
 493 +#include <linux/ath9k_platform.h>
 494 +#include <linux/leds.h>
 495 +
 496 +#include <asm/time.h>
 497 +#include <asm/machdep.h>
 498 +#include <asm/pci-bridge.h>
 499 +#include <mm/mmu_decl.h>
 500 +#include <asm/prom.h>
 501 +#include <asm/udbg.h>
 502 +#include <asm/mpic.h>
 503 +
 504 +#include <sysdev/fsl_soc.h>
 505 +#include <sysdev/fsl_pci.h>
 506 +
 507 +#include "mpc85xx.h"
 508 +
 509 +void __init tl_wdr4900_v1_pic_init(void)
 510 +{
 511 +       struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
 512 +         MPIC_SINGLE_DEST_CPU,
 513 +         0, 256, " OpenPIC  ");
 514 +
 515 +       BUG_ON(mpic == NULL);
 516 +
 517 +       mpic_init(mpic);
 518 +}
 519 +
 520 +#ifdef CONFIG_PCI
 521 +static struct gpio_led tl_wdr4900_v1_wmac_leds_gpio[] = {
 522 +       {
 523 +               .name           = "tp-link:blue:wps",
 524 +               .gpio           = 1,
 525 +               .active_low     = 1,
 526 +       },
 527 +};
 528 +
 529 +static struct ath9k_platform_data tl_wdr4900_v1_wmac0_data = {
 530 +       .led_pin = 0,
 531 +       .eeprom_name = "pci_wmac0.eeprom",
 532 +       .leds = tl_wdr4900_v1_wmac_leds_gpio,
 533 +       .num_leds = ARRAY_SIZE(tl_wdr4900_v1_wmac_leds_gpio),
 534 +};
 535 +
 536 +static struct ath9k_platform_data tl_wdr4900_v1_wmac1_data = {
 537 +       .led_pin = 0,
 538 +       .eeprom_name = "pci_wmac1.eeprom",
 539 +};
 540 +
 541 +static void tl_wdr4900_v1_pci_wmac_fixup(struct pci_dev *dev)
 542 +{
 543 +       if (!machine_is(tl_wdr4900_v1))
 544 +               return;
 545 +
 546 +       if (dev->bus->number == 1 &&
 547 +           PCI_SLOT(dev->devfn) == 0) {
 548 +               dev->dev.platform_data = &tl_wdr4900_v1_wmac0_data;
 549 +               return;
 550 +       }
 551 +
 552 +       if (dev->bus->number == 3 &&
 553 +           PCI_SLOT(dev->devfn) == 0 &&
 554 +           dev->device == 0xabcd) {
 555 +               dev->dev.platform_data = &tl_wdr4900_v1_wmac1_data;
 556 +
 557 +               /*
 558 +                * The PCI header of the AR9381 chip is not programmed
 559 +                * correctly by the bootloader and the device uses wrong
 560 +                * data due to that. Replace the broken values with the
 561 +                * correct ones.
 562 +                */
 563 +               dev->device = 0x30;
 564 +               dev->class = 0x028000;
 565 +
 566 +               pr_info("pci %s: AR9381 fixup applied\n", pci_name(dev));
 567 +       }
 568 +}
 569 +
 570 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
 571 +                       tl_wdr4900_v1_pci_wmac_fixup);
 572 +#endif /* CONFIG_PCI */
 573 +
 574 +/*
 575 + * Setup the architecture
 576 + */
 577 +static void __init tl_wdr4900_v1_setup_arch(void)
 578 +{
 579 +       if (ppc_md.progress)
 580 +               ppc_md.progress("tl_wdr4900_v1_setup_arch()", 0);
 581 +
 582 +       fsl_pci_assign_primary();
 583 +
 584 +       printk(KERN_INFO "TL-WDR4900 v1 board from TP-Link\n");
 585 +}
 586 +
 587 +machine_arch_initcall(tl_wdr4900_v1, mpc85xx_common_publish_devices);
 588 +machine_arch_initcall(tl_wdr4900_v1, swiotlb_setup_bus_notifier);
 589 +
 590 +/*
 591 + * Called very early, device-tree isn't unflattened
 592 + */
 593 +static int __init tl_wdr4900_v1_probe(void)
 594 +{
 595 +       unsigned long root = of_get_flat_dt_root();
 596 +
 597 +       if (of_flat_dt_is_compatible(root, "tp-link,TL-WDR4900v1"))
 598 +               return 1;
 599 +
 600 +       return 0;
 601 +}
 602 +
 603 +define_machine(tl_wdr4900_v1) {
 604 +       .name                   = "Freescale P1014",
 605 +       .probe                  = tl_wdr4900_v1_probe,
 606 +       .setup_arch             = tl_wdr4900_v1_setup_arch,
 607 +       .init_IRQ               = tl_wdr4900_v1_pic_init,
 608 +#ifdef CONFIG_PCI
 609 +       .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 610 +#endif
 611 +       .get_irq                = mpic_get_irq,
 612 +       .restart                = fsl_rstcr_restart,
 613 +       .calibrate_decr         = generic_calibrate_decr,
 614 +       .progress               = udbg_progress,
 615 +};