1 From a4df453fbfa6199ad33435cee6ce2dfcc65321b0 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Jul 2015 05:45:58 +0200
4 Subject: [PATCH 73/76] clk
7 include/dt-bindings/clock/mt7623-clk.h | 158 +++++++++++++++-----------------
8 1 file changed, 73 insertions(+), 85 deletions(-)
10 --- a/include/dt-bindings/clock/mt7623-clk.h
11 +++ b/include/dt-bindings/clock/mt7623-clk.h
16 -#define CLK_TOP_AUDPLL_24 1
17 -#define CLK_TOP_AUDPLL_D16 2
18 -#define CLK_TOP_AUDPLL_D4 3
19 -#define CLK_TOP_AUDPLL_D8 4
20 -#define CLK_TOP_CLKPH_MCK 5
21 -#define CLK_TOP_CPUM_TCK_IN 6
22 -#define CLK_TOP_DSI0_LNTC_DSICLK 7
23 -#define CLK_TOP_HDMITX_CLKDIG_CTS 8
24 -#define CLK_TOP_LVDS_ETH 9
25 -#define CLK_TOP_LVDSPLL_D2 10
26 -#define CLK_TOP_LVDSPLL_D4 11
27 -#define CLK_TOP_LVDSPLL_D8 12
28 -#define CLK_TOP_MAINPLL_230P3M 13
29 -#define CLK_TOP_MAINPLL_322P4M 14
30 -#define CLK_TOP_MAINPLL_537P3M 15
31 -#define CLK_TOP_MAINPLL_806M 16
32 -#define CLK_TOP_MEMPLL_MCK_D4 17
33 -#define CLK_TOP_MMPLL_D2 18
34 -#define CLK_TOP_MSDCPLL_D2 19
35 -#define CLK_TOP_SYSPLL1_D16 20
36 -#define CLK_TOP_SYSPLL1_D2 21
37 -#define CLK_TOP_SYSPLL1_D4 22
38 -#define CLK_TOP_SYSPLL1_D8 23
39 -#define CLK_TOP_SYSPLL2_D2 24
40 -#define CLK_TOP_SYSPLL2_D4 25
41 -#define CLK_TOP_SYSPLL2_D8 26
42 -#define CLK_TOP_SYSPLL3_D2 27
43 -#define CLK_TOP_SYSPLL3_D4 28
44 -#define CLK_TOP_SYSPLL4_D2 29
45 -#define CLK_TOP_SYSPLL4_D4 30
46 -#define CLK_TOP_SYSPLL_D3 31
47 -#define CLK_TOP_SYSPLL_D5 32
48 -#define CLK_TOP_SYSPLL_D7 33
49 -#define CLK_TOP_TVDPLL_d2 34
50 -#define CLK_TOP_TVDPLL_D4 35
51 -#define CLK_TOP_UNIVPLL_178P3M 36
52 -#define CLK_TOP_UNIVPLL1_D10 37
53 -#define CLK_TOP_UNIVPLL1_D2 38
54 -#define CLK_TOP_UNIVPLL1_D4 39
55 -#define CLK_TOP_UNIVPLL1_D6 40
56 -#define CLK_TOP_UNIVPLL1_D8 41
57 -#define CLK_TOP_UNIVPLL_249P6M 42
58 -#define CLK_TOP_UNIVPLL2_D2 43
59 -#define CLK_TOP_UNIVPLL2_D4 44
60 -#define CLK_TOP_UNIVPLL2_D6 45
61 -#define CLK_TOP_UNIVPLL2_D8 46
62 -#define CLK_TOP_UNIVPLL_416M 47
63 -#define CLK_TOP_UNIVPLL_48M 48
64 -#define CLK_TOP_UNIVPLL_624M 49
65 -#define CLK_TOP_UNIVPLL_D26 50
66 -#define CLK_TOP_UNIVPLL_D5 51
67 -#define CLK_TOP_APLL_SEL 52
68 +#define CLK_TOP_MAINPLL_650M 1
69 +#define CLK_TOP_MAINPLL_433P3M 2
70 +#define CLK_TOP_MAINPLL_260M 3
71 +#define CLK_TOP_MAINPLL_185P6M 4
72 +#define CLK_TOP_UNIVPLL_624M 5
73 +#define CLK_TOP_UNIVPLL_416M 6
74 +#define CLK_TOP_UNIVPLL_249P6M 7
75 +#define CLK_TOP_UNIVPLL_178P3M 8
76 +#define CLK_TOP_UNIVPLL_48M 9
77 +#define CLK_TOP_AUDPLL_D4 10
78 +#define CLK_TOP_AUDPLL_D8 11
79 +#define CLK_TOP_AUDPLL_D16 12
80 +#define CLK_TOP_AUDPLL_24 13
81 +#define CLK_TOP_MSDCPLL_D2 14
82 +#define CLK_TOP_SYSPLL1_D2 15
83 +#define CLK_TOP_SYSPLL1_D4 16
84 +#define CLK_TOP_SYSPLL1_D8 17
85 +#define CLK_TOP_SYSPLL1_D16 18
86 +#define CLK_TOP_SYSPLL2_D2 19
87 +#define CLK_TOP_SYSPLL2_D4 20
88 +#define CLK_TOP_SYSPLL2_D8 21
89 +#define CLK_TOP_SYSPLL3_D2 22
90 +#define CLK_TOP_SYSPLL3_D4 23
91 +#define CLK_TOP_SYSPLL4_D2 24
92 +#define CLK_TOP_SYSPLL4_D4 25
93 +#define CLK_TOP_SYSPLL_D3 26
94 +#define CLK_TOP_SYSPLL_D5 27
95 +#define CLK_TOP_SYSPLL_D7 28
96 +#define CLK_TOP_UNIVPLL1_D2 29
97 +#define CLK_TOP_UNIVPLL1_D4 30
98 +#define CLK_TOP_UNIVPLL1_D6 31
99 +#define CLK_TOP_UNIVPLL1_D8 32
100 +#define CLK_TOP_UNIVPLL1_D10 33
101 +#define CLK_TOP_UNIVPLL2_D2 34
102 +#define CLK_TOP_UNIVPLL2_D4 35
103 +#define CLK_TOP_UNIVPLL2_D6 36
104 +#define CLK_TOP_UNIVPLL2_D8 37
105 +#define CLK_TOP_UNIVPLL_D5 38
106 +#define CLK_TOP_UNIVPLL_D26 39
107 +#define CLK_TOP_AXI_SEL 40
108 +#define CLK_TOP_MEM_SEL 41
109 +#define CLK_TOP_DDR_SEL 42
110 +#define CLK_TOP_MM_SEL 43
111 +#define CLK_TOP_PWM_SEL 44
112 +#define CLK_TOP_MFG_SEL 45
113 +#define CLK_TOP_UART_SEL 46
114 +#define CLK_TOP_SPI_SEL 47
115 +#define CLK_TOP_USB20_SEL 48
116 +#define CLK_TOP_MSDC30_0_SEL 49
117 +#define CLK_TOP_MSDC30_1_SEL 50
118 +#define CLK_TOP_MSDC30_2_SEL 51
119 +#define CLK_TOP_AUDIO_SEL 52
120 #define CLK_TOP_AUDIO_INTBUS_SEL 53
121 -#define CLK_TOP_AUDIO_SEL 54
122 -#define CLK_TOP_AXI_SEL 55
123 -#define CLK_TOP_CAM_SEL 56
124 -#define CLK_TOP_DDR_SEL 57
125 -#define CLK_TOP_DPI0_SEL 58
126 -#define CLK_TOP_DPI1_SEL 59
127 -#define CLK_TOP_DPILVDS_SEL 60
128 -#define CLK_TOP_ETH_SEL 61
129 -#define CLK_TOP_MEM_SEL 62
130 -#define CLK_TOP_MFG_SEL 63
131 -#define CLK_TOP_MM_SEL 64
132 -#define CLK_TOP_MSDC30_0_SEL 65
133 -#define CLK_TOP_MSDC30_1_SEL 66
134 -#define CLK_TOP_MSDC30_2_SEL 67
135 -#define CLK_TOP_NFI2X_SEL 68
136 -#define CLK_TOP_PMICSPI_SEL 69
137 -#define CLK_TOP_PWM_SEL 70
138 -#define CLK_TOP_RTC_SEL 71
139 -#define CLK_TOP_SCP_SEL 72
140 -#define CLK_TOP_SPI_SEL 73
141 -#define CLK_TOP_TVE_SEL 74
142 -#define CLK_TOP_UART_SEL 75
143 -#define CLK_TOP_USB20_SEL 76
144 -#define CLK_TOP_VDEC_SEL 77
145 -#define CLK_TOP_NR_CLK 78
146 +#define CLK_TOP_PMICSPI_SEL 54
147 +#define CLK_TOP_SCP_SEL 55
148 +#define CLK_TOP_APLL_SEL 56
149 +#define CLK_TOP_RTC_SEL 57
150 +#define CLK_TOP_NFI2X_SEL 58
151 +#define CLK_TOP_ETH_SEL 59
152 +#define CLK_TOP_NR_CLK 60
156 #define CLK_APMIXED_ARMPLL 1
157 #define CLK_APMIXED_MAINPLL 2
158 -#define CLK_APMIXED_MSDCPLL 3
159 -#define CLK_APMIXED_UNIVPLL 4
160 -#define CLK_APMIXED_MMPLL 5
161 -#define CLK_APMIXED_VENCPLL 6
162 -#define CLK_APMIXED_TVDPLL 7
163 -#define CLK_APMIXED_LVDSPLL 8
164 -#define CLK_APMIXED_AUDPLL 9
165 +#define CLK_APMIXED_UNIVPLL 3
166 +#define CLK_APMIXED_MSDCPLL 4
167 +#define CLK_APMIXED_AUDPLL 5
168 +#define CLK_APMIXED_TRGPLL 6
169 +#define CLK_APMIXED_ETHPLL 7
174 #define CLK_INFRA_IRRX 19
175 #define CLK_INFRA_PMICSPI 22
176 #define CLK_INFRA_PMIC_WRAP 23
177 -#define CLK_INFRA_NR_CLK 24
178 +#define CLK_INFRA_CA7SEL 24
179 +#define CLK_INFRA_NR_CLK 25
184 #define CLK_PERI_UART3_SEL 38
185 #define CLK_PERI_NR_CLK 39
187 +#define CLK_HIFSYS_USB0_PHY 1
188 +#define CLK_HIFSYS_USB1_PHY 2
189 +#define CLK_HIFSYS_PCIE0 3
190 +#define CLK_HIFSYS_PCIE1 4
191 +#define CLK_HIFSYS_PCIE2 5
192 +#define CLK_HIFSYS_NR_CLK 6
194 #endif /* _DT_BINDINGS_CLK_MT7623_H */
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