target/linux/mediatek/patches-4.4/0078-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch

   1 From 9dd4e96d415d1e1910ec42058729380cddb22f9d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 29 Mar 2016 14:32:07 +0200
   4 Subject: [PATCH 78/90] net: mediatek: update the IRQ part of the binding
   5  document
   6
   7 The current binding document only describes a single interrupt. Update the
   8 document by adding the 2 other interrupts.
   9
  10 The driver currently only uses a single interrupt. The HW is however able
  11 to using IRQ grouping to split TX and RX onto separate GIC irqs.
  12
  13 Signed-off-by: John Crispin <blogic@openwrt.org>
  14  Acked-by: Rob Herring <robh@kernel.org>
  15 ---
  16  Documentation/devicetree/bindings/net/mediatek-net.txt |    7 +++++--
  17  1 file changed, 5 insertions(+), 2 deletions(-)
  18
  19 diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
  20 index 5ca7929..32eaaca 100644
  21 --- a/Documentation/devicetree/bindings/net/mediatek-net.txt
  22 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
  23 @@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
  24  Required properties:
  25  - compatible: Should be "mediatek,mt7623-eth"
  26  - reg: Address and length of the register set for the device
  27 -- interrupts: Should contain the frame engines interrupt
  28 +- interrupts: Should contain the three frame engines interrupts in numeric
  29 +       order. These are fe_int0, fe_int1 and fe_int2.
  30  - clocks: the clock used by the core
  31  - clock-names: the names of the clock listed in the clocks property. These are
  32         "ethif", "esw", "gp2", "gp1"
  33 @@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
  34                  <&ethsys CLK_ETHSYS_GP2>,
  35                  <&ethsys CLK_ETHSYS_GP1>;
  36         clock-names = "ethif", "esw", "gp2", "gp1";
  37 -       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
  38 +       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
  39 +                     GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
  40 +                     GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
  41         power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  42         resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
  43         reset-names = "eth";
  44 --
  45 1.7.10.4
  46