target/linux/mediatek/patches-4.4/0062-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch

   1 From c906caf00335b78ae1275eea4bfceca5273f3154 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 31 Mar 2016 02:26:37 +0200
   4 Subject: [PATCH 62/90] clk: mediatek: Export CPU mux clocks for CPU frequency
   5  control
   6
   7 This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
   8 for intermediate clock source switching.
   9
  10 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  11 ---
  12  drivers/clk/mediatek/Makefile          |    2 +-
  13  drivers/clk/mediatek/clk-cpumux.c      |  127 ++++++++++++++++++++++++++++++++
  14  drivers/clk/mediatek/clk-cpumux.h      |   22 ++++++
  15  drivers/clk/mediatek/clk-mt2701.c      |    8 ++
  16  drivers/clk/mediatek/clk-mt8173.c      |   23 ++++++
  17  include/dt-bindings/clock/mt2701-clk.h |    3 +-
  18  include/dt-bindings/clock/mt8173-clk.h |    4 +-
  19  7 files changed, 186 insertions(+), 3 deletions(-)
  20  create mode 100644 drivers/clk/mediatek/clk-cpumux.c
  21  create mode 100644 drivers/clk/mediatek/clk-cpumux.h
  22
  23 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
  24 index 5b2b91b..76bfab6 100644
  25 --- a/drivers/clk/mediatek/Makefile
  26 +++ b/drivers/clk/mediatek/Makefile
  27 @@ -1,4 +1,4 @@
  28 -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
  29 +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
  30  obj-$(CONFIG_RESET_CONTROLLER) += reset.o
  31  obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
  32  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
  33 diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
  34 new file mode 100644
  35 index 0000000..91b5238
  36 --- /dev/null
  37 +++ b/drivers/clk/mediatek/clk-cpumux.c
  38 @@ -0,0 +1,127 @@
  39 +/*
  40 + * Copyright (c) 2015 Linaro Ltd.
  41 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  42 + *
  43 + * This program is free software; you can redistribute it and/or modify
  44 + * it under the terms of the GNU General Public License version 2 as
  45 + * published by the Free Software Foundation.
  46 + *
  47 + * This program is distributed in the hope that it will be useful,
  48 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  49 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  50 + * GNU General Public License for more details.
  51 + */
  52 +
  53 +#include <linux/clk-provider.h>
  54 +#include <linux/mfd/syscon.h>
  55 +#include <linux/slab.h>
  56 +
  57 +#include "clk-mtk.h"
  58 +#include "clk-cpumux.h"
  59 +
  60 +struct mtk_clk_cpumux {
  61 +       struct clk_hw   hw;
  62 +       struct regmap   *regmap;
  63 +       u32             reg;
  64 +       u32             mask;
  65 +       u8              shift;
  66 +};
  67 +
  68 +static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
  69 +{
  70 +       return container_of(_hw, struct mtk_clk_cpumux, hw);
  71 +}
  72 +
  73 +static u8 clk_cpumux_get_parent(struct clk_hw *hw)
  74 +{
  75 +       struct mtk_clk_cpumux *mux = to_clk_mux(hw);
  76 +       int num_parents = clk_hw_get_num_parents(hw);
  77 +       unsigned int val;
  78 +
  79 +       regmap_read(mux->regmap, mux->reg, &val);
  80 +
  81 +       val >>= mux->shift;
  82 +       val &= mux->mask;
  83 +
  84 +       if (val >= num_parents)
  85 +               return -EINVAL;
  86 +
  87 +       return val;
  88 +}
  89 +
  90 +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
  91 +{
  92 +       struct mtk_clk_cpumux *mux = to_clk_mux(hw);
  93 +       u32 mask, val;
  94 +
  95 +       val = index << mux->shift;
  96 +       mask = mux->mask << mux->shift;
  97 +
  98 +       return regmap_update_bits(mux->regmap, mux->reg, mask, val);
  99 +}
 100 +
 101 +static const struct clk_ops clk_cpumux_ops = {
 102 +       .get_parent = clk_cpumux_get_parent,
 103 +       .set_parent = clk_cpumux_set_parent,
 104 +};
 105 +
 106 +static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
 107 +                                          struct regmap *regmap)
 108 +{
 109 +       struct mtk_clk_cpumux *cpumux;
 110 +       struct clk *clk;
 111 +       struct clk_init_data init;
 112 +
 113 +       cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
 114 +       if (!cpumux)
 115 +               return ERR_PTR(-ENOMEM);
 116 +
 117 +       init.name = mux->name;
 118 +       init.ops = &clk_cpumux_ops;
 119 +       init.parent_names = mux->parent_names;
 120 +       init.num_parents = mux->num_parents;
 121 +       init.flags = mux->flags;
 122 +
 123 +       cpumux->reg = mux->mux_reg;
 124 +       cpumux->shift = mux->mux_shift;
 125 +       cpumux->mask = BIT(mux->mux_width) - 1;
 126 +       cpumux->regmap = regmap;
 127 +       cpumux->hw.init = &init;
 128 +
 129 +       clk = clk_register(NULL, &cpumux->hw);
 130 +       if (IS_ERR(clk))
 131 +               kfree(cpumux);
 132 +
 133 +       return clk;
 134 +}
 135 +
 136 +int __init mtk_clk_register_cpumuxes(struct device_node *node,
 137 +                             const struct mtk_composite *clks, int num,
 138 +                             struct clk_onecell_data *clk_data)
 139 +{
 140 +       int i;
 141 +       struct clk *clk;
 142 +       struct regmap *regmap;
 143 +
 144 +       regmap = syscon_node_to_regmap(node);
 145 +       if (IS_ERR(regmap)) {
 146 +               pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
 147 +                      PTR_ERR(regmap));
 148 +               return PTR_ERR(regmap);
 149 +       }
 150 +
 151 +       for (i = 0; i < num; i++) {
 152 +               const struct mtk_composite *mux = &clks[i];
 153 +
 154 +               clk = mtk_clk_register_cpumux(mux, regmap);
 155 +               if (IS_ERR(clk)) {
 156 +                       pr_err("Failed to register clk %s: %ld\n",
 157 +                              mux->name, PTR_ERR(clk));
 158 +                       continue;
 159 +               }
 160 +
 161 +               clk_data->clks[mux->id] = clk;
 162 +       }
 163 +
 164 +       return 0;
 165 +}
 166 diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
 167 new file mode 100644
 168 index 0000000..52c769f
 169 --- /dev/null
 170 +++ b/drivers/clk/mediatek/clk-cpumux.h
 171 @@ -0,0 +1,22 @@
 172 +/*
 173 + * Copyright (c) 2015 Linaro Ltd.
 174 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
 175 + *
 176 + * This program is free software; you can redistribute it and/or modify
 177 + * it under the terms of the GNU General Public License version 2 as
 178 + * published by the Free Software Foundation.
 179 + *
 180 + * This program is distributed in the hope that it will be useful,
 181 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 182 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 183 + * GNU General Public License for more details.
 184 + */
 185 +
 186 +#ifndef __DRV_CLK_CPUMUX_H
 187 +#define __DRV_CLK_CPUMUX_H
 188 +
 189 +int mtk_clk_register_cpumuxes(struct device_node *node,
 190 +                             const struct mtk_composite *clks, int num,
 191 +                             struct clk_onecell_data *clk_data);
 192 +
 193 +#endif /* __DRV_CLK_CPUMUX_H */
 194 diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
 195 index 1634288..5c37fcb 100644
 196 --- a/drivers/clk/mediatek/clk-mt2701.c
 197 +++ b/drivers/clk/mediatek/clk-mt2701.c
 198 @@ -18,6 +18,7 @@
 199
 200  #include "clk-mtk.h"
 201  #include "clk-gate.h"
 202 +#include "clk-cpumux.h"
 203
 204  #include <dt-bindings/clock/mt2701-clk.h>
 205
 206 @@ -465,6 +466,10 @@ static const char * const cpu_parents[] __initconst = {
 207         "mmpll"
 208  };
 209
 210 +static const struct mtk_composite cpu_muxes[] __initconst = {
 211 +       MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
 212 +};
 213 +
 214  static const struct mtk_composite top_muxes[] __initconst = {
 215         MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 216                 0x0040, 0, 3, INVALID_MUX_GATE_BIT),
 217 @@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
 218         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 219                                                 clk_data);
 220
 221 +       mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
 222 +                                               clk_data);
 223 +
 224         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 225         if (r)
 226                 pr_err("%s(): could not register clock provider: %d\n",
 227 diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
 228 index 227e356..b82c0e2 100644
 229 --- a/drivers/clk/mediatek/clk-mt8173.c
 230 +++ b/drivers/clk/mediatek/clk-mt8173.c
 231 @@ -18,6 +18,7 @@
 232
 233  #include "clk-mtk.h"
 234  #include "clk-gate.h"
 235 +#include "clk-cpumux.h"
 236
 237  #include <dt-bindings/clock/mt8173-clk.h>
 238
 239 @@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
 240         "apll2_div5"
 241  };
 242
 243 +static const char * const ca53_parents[] __initconst = {
 244 +       "clk26m",
 245 +       "armca7pll",
 246 +       "mainpll",
 247 +       "univpll"
 248 +};
 249 +
 250 +static const char * const ca57_parents[] __initconst = {
 251 +       "clk26m",
 252 +       "armca15pll",
 253 +       "mainpll",
 254 +       "univpll"
 255 +};
 256 +
 257 +static const struct mtk_composite cpu_muxes[] __initconst = {
 258 +       MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
 259 +       MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
 260 +};
 261 +
 262  static const struct mtk_composite top_muxes[] __initconst = {
 263         /* CLK_CFG_0 */
 264         MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
 265 @@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
 266                                                 clk_data);
 267         mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
 268
 269 +       mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
 270 +                                               clk_data);
 271 +
 272         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 273         if (r)
 274                 pr_err("%s(): could not register clock provider: %d\n",
 275 diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
 276 index 50972d1..a6c63b8 100644
 277 --- a/include/dt-bindings/clock/mt2701-clk.h
 278 +++ b/include/dt-bindings/clock/mt2701-clk.h
 279 @@ -217,7 +217,8 @@
 280  #define CLK_INFRA_PMICWRAP                     17
 281  #define CLK_INFRA_DDCCI                                18
 282  #define CLK_INFRA_CLK_13M                       19
 283 -#define CLK_INFRA_NR                           20
 284 +#define CLK_INFRA_CPUSEL                       20
 285 +#define CLK_INFRA_NR                           21
 286
 287  /* PERICFG */
 288
 289 diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
 290 index 7956ba1..c82ed7c 100644
 291 --- a/include/dt-bindings/clock/mt8173-clk.h
 292 +++ b/include/dt-bindings/clock/mt8173-clk.h
 293 @@ -192,7 +192,9 @@
 294  #define CLK_INFRA_PMICSPI              10
 295  #define CLK_INFRA_PMICWRAP             11
 296  #define CLK_INFRA_CLK_13M              12
 297 -#define CLK_INFRA_NR_CLK               13
 298 +#define CLK_INFRA_CA53SEL              13
 299 +#define CLK_INFRA_CA57SEL              14
 300 +#define CLK_INFRA_NR_CLK               15
 301
 302  /* PERI_SYS */
 303
 304 --
 305 1.7.10.4
 306