target/linux/mediatek/patches-4.4/0061-clk-mediatek-enable-critical-clocks.patch

   1 From 6610fdbea393a4a8ed956b2aaf7012bea3a5069e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 31 Mar 2016 06:46:51 +0200
   4 Subject: [PATCH 61/91] clk: mediatek: enable critical clocks
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/clk/mediatek/clk-mt2701.c |   22 ++++++++++++++++++++--
   9  1 file changed, 20 insertions(+), 2 deletions(-)
  10
  11 diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
  12 index 812b347..1634288 100644
  13 --- a/drivers/clk/mediatek/clk-mt2701.c
  14 +++ b/drivers/clk/mediatek/clk-mt2701.c
  15 @@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[] __initconst = {
  16         GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
  17  };
  18
  19 +static struct clk_onecell_data *mt7623_top_clk_data __initdata;
  20 +static struct clk_onecell_data *mt7623_pll_clk_data __initdata;
  21 +
  22 +static void __init mtk_clk_enable_critical(void)
  23 +{
  24 +       if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
  25 +               return;
  26 +
  27 +       clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
  28 +       clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
  29 +       clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
  30 +       clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
  31 +}
  32 +
  33  static void __init mtk_topckgen_init(struct device_node *node)
  34  {
  35         struct clk_onecell_data *clk_data;
  36 @@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
  37                 return;
  38         }
  39
  40 -       clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
  41 +       mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
  42
  43         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  44                                                                 clk_data);
  45 @@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(struct device_node *node)
  46         if (r)
  47                 pr_err("%s(): could not register clock provider: %d\n",
  48                         __func__, r);
  49 +
  50 +       mtk_clk_enable_critical();
  51  }
  52  CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
  53
  54 @@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
  55         struct clk_onecell_data *clk_data;
  56         int r;
  57
  58 -       clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
  59 +       mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
  60         if (!clk_data)
  61                 return;
  62
  63 @@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
  64         if (r)
  65                 pr_err("%s(): could not register clock provider: %d\n",
  66                         __func__, r);
  67 +
  68 +       mtk_clk_enable_critical();
  69  }
  70  CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
  71                                                         mtk_apmixedsys_init);
  72 --
  73 1.7.10.4
  74