target/linux/mediatek/patches-4.4/0058-mtd-mediatek-driver-for-MTK-Smart-Device-Gen1-NAND.patch

   1 From a97e38f34b59d18d9ca3626c2611c63cc6c6b48a Mon Sep 17 00:00:00 2001
   2 From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
   3 Date: Wed, 2 Mar 2016 12:00:12 -0500
   4 Subject: [PATCH 58/91] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
   5
   6 This patch adds support for mediatek's SDG1 NFC nand controller
   7 embedded in SoC 2701.
   8
   9 UBIFS support has been successfully tested.
  10
  11 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  12 ---
  13  drivers/mtd/nand/Kconfig            |    6 +
  14  drivers/mtd/nand/Makefile           |    1 +
  15  drivers/mtd/nand/mtksdg1_nand.c     | 1535 +++++++++++++++++++++++++++++++++++
  16  drivers/mtd/nand/mtksdg1_nand_ecc.h |   75 ++
  17  drivers/mtd/nand/mtksdg1_nand_nfi.h |  119 +++
  18  5 files changed, 1736 insertions(+)
  19  create mode 100644 drivers/mtd/nand/mtksdg1_nand.c
  20  create mode 100644 drivers/mtd/nand/mtksdg1_nand_ecc.h
  21  create mode 100644 drivers/mtd/nand/mtksdg1_nand_nfi.h
  22
  23 diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
  24 index 2896640..5ec072a 100644
  25 --- a/drivers/mtd/nand/Kconfig
  26 +++ b/drivers/mtd/nand/Kconfig
  27 @@ -546,4 +546,10 @@ config MTD_NAND_HISI504
  28         help
  29           Enables support for NAND controller on Hisilicon SoC Hip04.
  30
  31 +config MTD_NAND_MTKSDG1
  32 +       tristate "Support for NAND controller on MTK Smart Device SoCs"
  33 +       depends on HAS_DMA
  34 +       help
  35 +       Enables support for NAND controller on MTK Smart Device SoCs.
  36 +
  37  endif # MTD_NAND
  38 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
  39 index 2c7f014..2a2620c 100644
  40 --- a/drivers/mtd/nand/Makefile
  41 +++ b/drivers/mtd/nand/Makefile
  42 @@ -55,5 +55,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)  += bcm47xxnflash/
  43  obj-$(CONFIG_MTD_NAND_SUNXI)           += sunxi_nand.o
  44  obj-$(CONFIG_MTD_NAND_HISI504)         += hisi504_nand.o
  45  obj-$(CONFIG_MTD_NAND_BRCMNAND)                += brcmnand/
  46 +obj-$(CONFIG_MTD_NAND_MTKSDG1)         += mtksdg1_nand.o
  47
  48  nand-objs := nand_base.o nand_bbt.o nand_timings.o
  49 diff --git a/drivers/mtd/nand/mtksdg1_nand.c b/drivers/mtd/nand/mtksdg1_nand.c
  50 new file mode 100644
  51 index 0000000..55dd17d
  52 --- /dev/null
  53 +++ b/drivers/mtd/nand/mtksdg1_nand.c
  54 @@ -0,0 +1,1535 @@
  55 +/*
  56 + * MTK smart device NAND Flash controller driver.
  57 + * Copyright (C) 2015-2016 MediaTek Inc.
  58 + * Authors:    Xiaolei Li              <xiaolei.li@mediatek.com>
  59 + *             Jorge Ramirez-Ortiz     <jorge.ramirez-ortiz@linaro.org>
  60 + *
  61 + * This program is free software; you can redistribute it and/or modify
  62 + * it under the terms of the GNU General Public License version 2 as
  63 + * published by the Free Software Foundation.
  64 + *
  65 + * This program is distributed in the hope that it will be useful,
  66 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  67 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  68 + * GNU General Public License for more details.
  69 + */
  70 +
  71 +#include <linux/platform_device.h>
  72 +#include <linux/dma-mapping.h>
  73 +#include <linux/interrupt.h>
  74 +#include <linux/of_mtd.h>
  75 +#include <linux/delay.h>
  76 +#include <linux/clk.h>
  77 +#include <linux/mtd/partitions.h>
  78 +#include <linux/mtd/nand.h>
  79 +#include <linux/mtd/mtd.h>
  80 +#include <linux/module.h>
  81 +
  82 +#include "mtksdg1_nand_nfi.h"
  83 +#include "mtksdg1_nand_ecc.h"
  84 +
  85 +#define MTK_IRQ_ECC            "mtksdg1-nand-ecc"
  86 +#define MTK_IRQ_NFI            "mtksdg1-nand-nfi"
  87 +#define MTK_NAME               "mtksdg1-nand"
  88 +
  89 +#define KB(x)                  ((x) * 1024UL)
  90 +#define MB(x)                  (KB(x) * 1024UL)
  91 +
  92 +#define SECTOR_SHIFT           (10)
  93 +#define SECTOR_SIZE            (1UL << SECTOR_SHIFT)
  94 +#define BYTES_TO_SECTORS(x)    ((x) >> SECTOR_SHIFT)
  95 +#define SECTORS_TO_BYTES(x)    ((x) << SECTOR_SHIFT)
  96 +
  97 +#define MTK_TIMEOUT            (500)
  98 +#define MTK_RESET_TIMEOUT      (1 * HZ)
  99 +
 100 +#define MTK_ECC_PARITY_BITS    (14)
 101 +#define MTK_NAND_MAX_CHIP      (2)
 102 +
 103 +#define MTK_OOB_ON             (1)
 104 +#define MTK_OOB_OFF            (0)
 105 +
 106 +/* raw accesses do not use ECC (ecc = !raw) */
 107 +#define MTK_ECC_OFF            (1)
 108 +#define MTK_ECC_ON             (0)
 109 +
 110 +struct mtk_nfc_clk {
 111 +       struct clk *nfiecc_clk;
 112 +       struct clk *nfi_clk;
 113 +       struct clk *pad_clk;
 114 +};
 115 +
 116 +struct mtk_nfc_saved_reg {
 117 +       struct {
 118 +               u32 enccnfg;
 119 +               u32 deccnfg;
 120 +       } ecc;
 121 +       struct {
 122 +               u32 emp_thresh;
 123 +               u16 pagefmt;
 124 +               u32 acccon;
 125 +               u16 cnrnb;
 126 +               u16 csel;
 127 +       } nfi;
 128 +};
 129 +
 130 +struct mtk_nfc_host {
 131 +       struct mtk_nfc_clk clk;
 132 +       struct nand_chip chip;
 133 +       struct device *dev;
 134 +
 135 +       struct {
 136 +               struct completion complete;
 137 +               void __iomem *base;
 138 +       } nfi;
 139 +
 140 +       struct {
 141 +               struct completion complete;
 142 +               void __iomem *base;
 143 +               u32 dec_sec;
 144 +       } ecc;
 145 +
 146 +       u32 fdm_reg[MTKSDG1_NFI_FDM_REG_SIZE / sizeof(u32)];
 147 +       bool switch_oob;
 148 +       u32 row_nob;
 149 +       u8 *buffer;
 150 +
 151 +#ifdef CONFIG_PM_SLEEP
 152 +       struct mtk_nfc_saved_reg saved_reg;
 153 +#endif
 154 +};
 155 +
 156 +static struct nand_ecclayout nand_2k_64 = {
 157 +       .oobfree = { {0, 16} },
 158 +};
 159 +
 160 +static struct nand_ecclayout nand_4k_128 = {
 161 +       .oobfree = { {0, 32} },
 162 +};
 163 +
 164 +/* NFI register access */
 165 +static inline void mtk_nfi_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
 166 +{
 167 +       writel(val, host->nfi.base + reg);
 168 +}
 169 +static inline void mtk_nfi_writew(struct mtk_nfc_host *host, u16 val, u32 reg)
 170 +{
 171 +       writew(val, host->nfi.base + reg);
 172 +}
 173 +static inline u32 mtk_nfi_readl(struct mtk_nfc_host *host, u32 reg)
 174 +{
 175 +       return readl_relaxed(host->nfi.base + reg);
 176 +}
 177 +static inline u16 mtk_nfi_readw(struct mtk_nfc_host *host, u32 reg)
 178 +{
 179 +       return readw_relaxed(host->nfi.base + reg);
 180 +}
 181 +static inline u8 mtk_nfi_readb(struct mtk_nfc_host *host, u32 reg)
 182 +{
 183 +       return readb_relaxed(host->nfi.base + reg);
 184 +}
 185 +
 186 +/* ECC register access */
 187 +static inline void mtk_ecc_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
 188 +{
 189 +       writel(val, host->ecc.base + reg);
 190 +}
 191 +static inline void mtk_ecc_writew(struct mtk_nfc_host *host, u16 val, u32 reg)
 192 +{
 193 +       writew(val, host->ecc.base + reg);
 194 +}
 195 +static inline u32 mtk_ecc_readl(struct mtk_nfc_host *host, u32 reg)
 196 +{
 197 +       return readl_relaxed(host->ecc.base + reg);
 198 +}
 199 +static inline u16 mtk_ecc_readw(struct mtk_nfc_host *host, u32 reg)
 200 +{
 201 +       return readw_relaxed(host->ecc.base + reg);
 202 +}
 203 +
 204 +static void mtk_nfc_hw_reset(struct mtk_nfc_host *host)
 205 +{
 206 +       unsigned long timeout = MTK_RESET_TIMEOUT;
 207 +       struct device *dev = host->dev;
 208 +       u32 val;
 209 +
 210 +       /* reset the state machine, data fifo and fdm data */
 211 +       mtk_nfi_writel(host, CON_FIFO_FLUSH | CON_NFI_RST, MTKSDG1_NFI_CON);
 212 +       timeout += jiffies;
 213 +       do {
 214 +               val = mtk_nfi_readl(host, MTKSDG1_NFI_MASTER_STA);
 215 +               val &= MASTER_STA_MASK;
 216 +               if (!val)
 217 +                       return;
 218 +               usleep_range(50, 100);
 219 +
 220 +       } while (time_before(jiffies, timeout));
 221 +
 222 +       dev_warn(dev, "nfi master active after in reset [0x%x] = 0x%x\n",
 223 +               MTKSDG1_NFI_MASTER_STA, val);
 224 +};
 225 +
 226 +static int mtk_nfc_set_command(struct mtk_nfc_host *host, u8 command)
 227 +{
 228 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 229 +       struct device *dev = host->dev;
 230 +       u32 val;
 231 +
 232 +       mtk_nfi_writel(host, command, MTKSDG1_NFI_CMD);
 233 +
 234 +       /* wait for the NFI core to enter command mode */
 235 +       timeout += jiffies;
 236 +       do {
 237 +               val = mtk_nfi_readl(host, MTKSDG1_NFI_STA);
 238 +               val &= STA_CMD;
 239 +               if (!val)
 240 +                       return 0;
 241 +               cpu_relax();
 242 +
 243 +       } while (time_before(jiffies, timeout));
 244 +       dev_warn(dev, "nfi core timed out entering command mode\n");
 245 +
 246 +       return -EIO;
 247 +}
 248 +
 249 +static int mtk_nfc_set_address(struct mtk_nfc_host *host, u32 column, u32 row,
 250 +               u8 colnob, u8 row_nob)
 251 +{
 252 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 253 +       struct device *dev = host->dev;
 254 +       u32 addr_nob, val;
 255 +
 256 +       addr_nob = colnob | (row_nob << ADDR_ROW_NOB_SHIFT);
 257 +       mtk_nfi_writel(host, column, MTKSDG1_NFI_COLADDR);
 258 +       mtk_nfi_writel(host, row, MTKSDG1_NFI_ROWADDR);
 259 +       mtk_nfi_writel(host, addr_nob, MTKSDG1_NFI_ADDRNOB);
 260 +
 261 +       /* wait for the NFI core to enter address mode */
 262 +       timeout += jiffies;
 263 +       do {
 264 +               val = mtk_nfi_readl(host, MTKSDG1_NFI_STA);
 265 +               val &= STA_ADDR;
 266 +               if (!val)
 267 +                       return 0;
 268 +               cpu_relax();
 269 +
 270 +       } while (time_before(jiffies, timeout));
 271 +
 272 +       dev_warn(dev, "nfi core timed out entering address mode\n");
 273 +
 274 +       return -EIO;
 275 +}
 276 +
 277 +static inline void mtk_ecc_encoder_idle(struct mtk_nfc_host *host)
 278 +{
 279 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 280 +       struct device *dev = host->dev;
 281 +       u32 val;
 282 +
 283 +       timeout += jiffies;
 284 +       do {
 285 +               val = mtk_ecc_readl(host, MTKSDG1_ECC_ENCIDLE);
 286 +               val &= ENC_IDLE;
 287 +               if (val)
 288 +                       return;
 289 +               cpu_relax();
 290 +
 291 +       } while (time_before(jiffies, timeout));
 292 +
 293 +       dev_warn(dev, "hw init ecc encoder not idle\n");
 294 +}
 295 +
 296 +static inline void mtk_ecc_decoder_idle(struct mtk_nfc_host *host)
 297 +{
 298 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 299 +       struct device *dev = host->dev;
 300 +       u32 val;
 301 +
 302 +       timeout += jiffies;
 303 +       do {
 304 +               val = mtk_ecc_readw(host, MTKSDG1_ECC_DECIDLE);
 305 +               val &= DEC_IDLE;
 306 +               if (val)
 307 +                       return;
 308 +               cpu_relax();
 309 +
 310 +       } while (time_before(jiffies, timeout));
 311 +
 312 +       dev_warn(dev, "hw init ecc decoder not idle\n");
 313 +}
 314 +
 315 +static int mtk_nfc_transfer_done(struct mtk_nfc_host *host, u32 sectors)
 316 +{
 317 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 318 +       u32 cnt;
 319 +
 320 +       /* wait for the sector count */
 321 +       timeout += jiffies;
 322 +       do {
 323 +               cnt = mtk_nfi_readl(host, MTKSDG1_NFI_ADDRCNTR);
 324 +               cnt &= CNTR_MASK;
 325 +               if (cnt >= sectors)
 326 +                       return 0;
 327 +               cpu_relax();
 328 +
 329 +       } while (time_before(jiffies, timeout));
 330 +
 331 +       return  -EIO;
 332 +}
 333 +
 334 +static int mtk_nfc_subpage_done(struct mtk_nfc_host *host, int sectors)
 335 +{
 336 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 337 +       u32 val;
 338 +
 339 +       timeout += jiffies;
 340 +       do {
 341 +               val = mtk_nfi_readl(host, MTKSDG1_NFI_BYTELEN);
 342 +               val &= CNTR_MASK;
 343 +               if (val >= sectors)
 344 +                       return 0;
 345 +               cpu_relax();
 346 +
 347 +       } while (time_before(jiffies, timeout));
 348 +
 349 +       return -EIO;
 350 +}
 351 +
 352 +static inline int mtk_nfc_data_ready(struct mtk_nfc_host *host)
 353 +{
 354 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 355 +       u8 val;
 356 +
 357 +       timeout += jiffies;
 358 +       do {
 359 +               val = mtk_nfi_readw(host, MTKSDG1_NFI_PIO_DIRDY);
 360 +               val &= PIO_DI_RDY;
 361 +               if (val)
 362 +                       return 0;
 363 +               cpu_relax();
 364 +
 365 +       } while (time_before(jiffies, timeout));
 366 +
 367 +       /* data _MUST_ not be accessed */
 368 +       return -EIO;
 369 +}
 370 +
 371 +static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
 372 +{
 373 +       struct nand_chip *chip = mtd_to_nand(mtd);
 374 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 375 +       struct device *dev = host->dev;
 376 +       u32 dec_size, enc_size;
 377 +       u32 ecc_bit, ecc_level;
 378 +       u32 spare, fmt;
 379 +       u32 reg;
 380 +
 381 +       host->row_nob = 1;
 382 +       if (chip->chipsize > MB(32))
 383 +               host->row_nob = chip->chipsize > MB(128) ? 3 : 2;
 384 +
 385 +       spare = mtd->oobsize / BYTES_TO_SECTORS(mtd->writesize);
 386 +       switch (spare) {
 387 +       case 16:
 388 +               ecc_bit = ECC_CNFG_4BIT;
 389 +               ecc_level = 4;
 390 +               break;
 391 +       case 32:
 392 +               ecc_bit = ECC_CNFG_12BIT;
 393 +               ecc_level = 12;
 394 +               break;
 395 +       default:
 396 +               dev_err(dev, "invalid spare size per sector: %d\n", spare);
 397 +               return -EINVAL;
 398 +       }
 399 +
 400 +       chip->ecc.strength = ecc_level;
 401 +       chip->ecc.size = SECTOR_SIZE;
 402 +
 403 +       switch (mtd->writesize) {
 404 +       case KB(2):
 405 +               fmt = PAGEFMT_512_2K;
 406 +               chip->ecc.layout = &nand_2k_64;
 407 +               break;
 408 +       case KB(4):
 409 +               fmt = PAGEFMT_2K_4K;
 410 +               chip->ecc.layout = &nand_4k_128;
 411 +               break;
 412 +       case KB(8):
 413 +               fmt = PAGEFMT_4K_8K;
 414 +               break;
 415 +       default:
 416 +               dev_err(dev, "invalid page size: %d\n", mtd->writesize);
 417 +               return -EINVAL;
 418 +       }
 419 +
 420 +       /* configure PAGE FMT */
 421 +       reg = fmt;
 422 +       reg |= PAGEFMT_SPARE_16 << PAGEFMT_SPARE_SHIFT;
 423 +       reg |= MTKSDG1_NFI_FDM_REG_SIZE << PAGEFMT_FDM_SHIFT;
 424 +       reg |= MTKSDG1_NFI_FDM_REG_SIZE << PAGEFMT_FDM_ECC_SHIFT;
 425 +       mtk_nfi_writew(host, reg, MTKSDG1_NFI_PAGEFMT);
 426 +
 427 +       /* configure ECC encoder (in bits) */
 428 +       enc_size = (SECTOR_SIZE + MTKSDG1_NFI_FDM_REG_SIZE) << 3;
 429 +       reg = ecc_bit | ECC_NFI_MODE | (enc_size << ECC_MS_SHIFT);
 430 +       mtk_ecc_writel(host, reg, MTKSDG1_ECC_ENCCNFG);
 431 +
 432 +       /* configure ECC decoder (inbits) */
 433 +       dec_size = enc_size + ecc_level * MTK_ECC_PARITY_BITS;
 434 +       reg = ecc_bit | ECC_NFI_MODE | (dec_size << ECC_MS_SHIFT);
 435 +       reg |= (DEC_CNFG_CORRECT | DEC_EMPTY_EN);
 436 +       mtk_ecc_writel(host, reg, MTKSDG1_ECC_DECCNFG);
 437 +
 438 +       return 0;
 439 +}
 440 +
 441 +static void mtk_nfc_device_reset(struct mtk_nfc_host *host)
 442 +{
 443 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
 444 +       struct device *dev = host->dev;
 445 +       u16 chip;
 446 +       int rc;
 447 +
 448 +       mtk_nfc_hw_reset(host);
 449 +
 450 +       /* enable reset done interrupt */
 451 +       mtk_nfi_writew(host, INTR_RST_DONE_EN, MTKSDG1_NFI_INTR_EN);
 452 +
 453 +       /* configure FSM for reset operation */
 454 +       mtk_nfi_writew(host, CNFG_OP_RESET, MTKSDG1_NFI_CNFG);
 455 +
 456 +       init_completion(&host->nfi.complete);
 457 +
 458 +       mtk_nfc_set_command(host, NAND_CMD_RESET);
 459 +       rc = wait_for_completion_timeout(&host->nfi.complete, timeout);
 460 +       if (!rc) {
 461 +               chip = mtk_nfi_readw(host, MTKSDG1_NFI_CSEL);
 462 +               dev_err(dev, "device(%d) reset timeout\n", chip);
 463 +       }
 464 +}
 465 +
 466 +static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip)
 467 +{
 468 +       struct nand_chip *nand = mtd_to_nand(mtd);
 469 +       struct mtk_nfc_host *host = nand_get_controller_data(nand);
 470 +
 471 +       if (chip < 0)
 472 +               return;
 473 +
 474 +       mtk_nfi_writel(host, chip, MTKSDG1_NFI_CSEL);
 475 +}
 476 +
 477 +static inline bool mtk_nfc_cmd_supported(unsigned command)
 478 +{
 479 +       switch (command) {
 480 +       case NAND_CMD_RESET:
 481 +       case NAND_CMD_READID:
 482 +       case NAND_CMD_STATUS:
 483 +       case NAND_CMD_READOOB:
 484 +       case NAND_CMD_ERASE1:
 485 +       case NAND_CMD_ERASE2:
 486 +       case NAND_CMD_SEQIN:
 487 +       case NAND_CMD_PAGEPROG:
 488 +       case NAND_CMD_CACHEDPROG:
 489 +       case NAND_CMD_READ0:
 490 +               return true;
 491 +       default:
 492 +               return false;
 493 +       }
 494 +}
 495 +
 496 +static void mtk_nfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
 497 +               int page_addr)
 498 +{
 499 +       struct mtk_nfc_host *host = nand_get_controller_data(mtd_to_nand(mtd));
 500 +       unsigned long const cmd_timeout = msecs_to_jiffies(MTK_TIMEOUT);
 501 +       struct completion *p = &host->nfi.complete;
 502 +       u32 val;
 503 +       int rc;
 504 +
 505 +       if (mtk_nfc_cmd_supported(command))
 506 +               mtk_nfc_hw_reset(host);
 507 +
 508 +       switch (command) {
 509 +       case NAND_CMD_RESET:
 510 +               mtk_nfc_device_reset(host);
 511 +               break;
 512 +       case NAND_CMD_READID:
 513 +               val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_SRD;
 514 +               mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
 515 +               mtk_nfc_set_command(host, NAND_CMD_READID);
 516 +               mtk_nfc_set_address(host, column, 0, 1, 0);
 517 +               mtk_nfi_writel(host, CON_SRD, MTKSDG1_NFI_CON);
 518 +               break;
 519 +       case NAND_CMD_STATUS:
 520 +               val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_SRD;
 521 +               mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
 522 +               mtk_nfc_set_command(host, NAND_CMD_STATUS);
 523 +               mtk_nfi_writel(host, CON_SRD, MTKSDG1_NFI_CON);
 524 +               break;
 525 +       case NAND_CMD_READOOB:
 526 +               val = CNFG_READ_EN | CNFG_BYTE_RW | CNFG_OP_READ;
 527 +               mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
 528 +               mtk_nfc_set_command(host, NAND_CMD_READ0);
 529 +               column += mtd->writesize;
 530 +               mtk_nfc_set_address(host, column, page_addr, 2, host->row_nob);
 531 +               val = CON_BRD | (1 << CON_SEC_SHIFT);
 532 +               mtk_nfi_writel(host, val, MTKSDG1_NFI_CON);
 533 +               break;
 534 +       case NAND_CMD_ERASE1:
 535 +               mtk_nfi_writew(host, INTR_ERS_DONE_EN, MTKSDG1_NFI_INTR_EN);
 536 +               mtk_nfi_writew(host, CNFG_OP_ERASE, MTKSDG1_NFI_CNFG);
 537 +               mtk_nfc_set_command(host, NAND_CMD_ERASE1);
 538 +               mtk_nfc_set_address(host, 0, page_addr, 0, host->row_nob);
 539 +               break;
 540 +       case NAND_CMD_ERASE2:
 541 +               init_completion(p);
 542 +               mtk_nfc_set_command(host, NAND_CMD_ERASE2);
 543 +               rc = wait_for_completion_timeout(p, cmd_timeout);
 544 +               if (!rc)
 545 +                       dev_err(host->dev, "erase command timeout\n");
 546 +               break;
 547 +       case NAND_CMD_SEQIN:
 548 +               mtk_nfi_writew(host, CNFG_OP_PRGM, MTKSDG1_NFI_CNFG);
 549 +               mtk_nfc_set_command(host, NAND_CMD_SEQIN);
 550 +               mtk_nfc_set_address(host, column, page_addr, 2, host->row_nob);
 551 +               break;
 552 +       case NAND_CMD_PAGEPROG:
 553 +       case NAND_CMD_CACHEDPROG:
 554 +               mtk_nfi_writew(host, INTR_BUSY_RT_EN, MTKSDG1_NFI_INTR_EN);
 555 +               init_completion(p);
 556 +               mtk_nfc_set_command(host, command);
 557 +               rc = wait_for_completion_timeout(p, cmd_timeout);
 558 +               if (!rc)
 559 +                       dev_err(host->dev, "pageprogr command timeout\n");
 560 +               break;
 561 +       case NAND_CMD_READ0:
 562 +               val = CNFG_OP_READ | CNFG_READ_EN;
 563 +               mtk_nfi_writew(host, val, MTKSDG1_NFI_CNFG);
 564 +               mtk_nfc_set_command(host, NAND_CMD_READ0);
 565 +               break;
 566 +       default:
 567 +               dev_warn(host->dev, "command 0x%x not supported\n", command);
 568 +               break;
 569 +       }
 570 +}
 571 +
 572 +static uint8_t mtk_nfc_read_byte(struct mtd_info *mtd)
 573 +{
 574 +       struct nand_chip *chip = mtd_to_nand(mtd);
 575 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 576 +       int rc;
 577 +
 578 +       rc = mtk_nfc_data_ready(host);
 579 +       if (rc < 0) {
 580 +               dev_err(host->dev, "data not ready\n");
 581 +               return NAND_STATUS_FAIL;
 582 +       }
 583 +
 584 +       return mtk_nfi_readb(host, MTKSDG1_NFI_DATAR);
 585 +}
 586 +
 587 +static void mtk_nfc_write_fdm(struct nand_chip *chip, u32 sectors)
 588 +{
 589 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 590 +       u8 *src, *dst;
 591 +       int i, j, reg;
 592 +
 593 +       for (i = 0; i < sectors ; i++) {
 594 +               /* read FDM from OOB into private area */
 595 +               src = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
 596 +               dst = (u8 *)host->fdm_reg;
 597 +               memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
 598 +
 599 +               /* write FDM to registers */
 600 +               for (j = 0; j < ARRAY_SIZE(host->fdm_reg); j++) {
 601 +                       reg = MTKSDG1_NFI_FDM0L + i * MTKSDG1_NFI_FDM_REG_SIZE;
 602 +                       reg += j * sizeof(host->fdm_reg[0]);
 603 +                       mtk_nfi_writel(host, host->fdm_reg[j], reg);
 604 +               }
 605 +       }
 606 +}
 607 +
 608 +static int mtk_nfc_write_page(struct mtd_info *mtd,
 609 +                       struct nand_chip *chip, const uint8_t *buf,
 610 +                       int oob_on, int page, int raw)
 611 +{
 612 +
 613 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 614 +       struct completion *nfi = &host->nfi.complete;
 615 +       struct device *dev = host->dev;
 616 +       const bool use_ecc = !raw;
 617 +       void *q = (void *) buf;
 618 +       dma_addr_t dma_addr;
 619 +       size_t dmasize;
 620 +       u32 reg;
 621 +       int ret;
 622 +
 623 +       dmasize = mtd->writesize + (raw ? mtd->oobsize : 0);
 624 +
 625 +       dma_addr = dma_map_single(dev, q, dmasize, DMA_TO_DEVICE);
 626 +       if (dma_mapping_error(host->dev, dma_addr)) {
 627 +               dev_err(host->dev, "dma mapping error\n");
 628 +               return -EINVAL;
 629 +       }
 630 +
 631 +       reg = mtk_nfi_readw(host, MTKSDG1_NFI_CNFG);
 632 +       reg |= CNFG_AHB | CNFG_DMA_BURST_EN;
 633 +       if (use_ecc) {
 634 +               /**
 635 +                * OOB will be generated
 636 +                *  - FDM: from register
 637 +                *  - ECC: from HW
 638 +                */
 639 +               reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
 640 +               mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
 641 +
 642 +               mtk_ecc_encoder_idle(host);
 643 +               mtk_ecc_writew(host, ENC_EN, MTKSDG1_ECC_ENCCON);
 644 +
 645 +               /* write OOB into the FDM registers (OOB area in MTK NAND) */
 646 +               if (oob_on)
 647 +                       mtk_nfc_write_fdm(chip, chip->ecc.steps);
 648 +       } else {
 649 +               /* OOB is part of the DMA transfer */
 650 +               mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
 651 +       }
 652 +
 653 +       mtk_nfi_writel(host, chip->ecc.steps << CON_SEC_SHIFT, MTKSDG1_NFI_CON);
 654 +       mtk_nfi_writel(host, lower_32_bits(dma_addr), MTKSDG1_NFI_STRADDR);
 655 +       mtk_nfi_writew(host, INTR_AHB_DONE_EN, MTKSDG1_NFI_INTR_EN);
 656 +
 657 +       init_completion(nfi);
 658 +
 659 +       /* start DMA */
 660 +       reg = mtk_nfi_readl(host, MTKSDG1_NFI_CON) | CON_BWR;
 661 +       mtk_nfi_writel(host, reg, MTKSDG1_NFI_CON);
 662 +
 663 +       ret = wait_for_completion_timeout(nfi, msecs_to_jiffies(MTK_TIMEOUT));
 664 +       if (!ret) {
 665 +               dev_err(dev, "program ahb done timeout\n");
 666 +               mtk_nfi_writew(host, 0, MTKSDG1_NFI_INTR_EN);
 667 +               ret = -ETIMEDOUT;
 668 +               goto timeout;
 669 +       }
 670 +
 671 +       ret = mtk_nfc_transfer_done(host, chip->ecc.steps);
 672 +       if (ret < 0)
 673 +               dev_err(dev, "hwecc write timeout\n");
 674 +timeout:
 675 +       dma_unmap_single(host->dev, dma_addr, dmasize, DMA_TO_DEVICE);
 676 +
 677 +       if (use_ecc) {
 678 +               mtk_ecc_encoder_idle(host);
 679 +               mtk_ecc_writew(host, ENC_DE, MTKSDG1_ECC_ENCCON);
 680 +       }
 681 +
 682 +       mtk_nfi_writel(host, 0, MTKSDG1_NFI_CON);
 683 +
 684 +       return ret;
 685 +}
 686 +
 687 +static int mtk_nfc_write_page_hwecc(struct mtd_info *mtd,
 688 +                       struct nand_chip *chip, const uint8_t *buf,
 689 +                       int oob_on, int page)
 690 +{
 691 +       return mtk_nfc_write_page(mtd, chip, buf, oob_on, page, MTK_ECC_ON);
 692 +}
 693 +
 694 +static int mtk_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 695 +                                       const uint8_t *buf, int oob_on, int pg)
 696 +{
 697 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 698 +       uint8_t *src, *dst;
 699 +       size_t len;
 700 +       u32 i;
 701 +
 702 +       memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
 703 +
 704 +       /* MTK internal 4KB page data layout:
 705 +        * ----------------------------------
 706 +        * PAGE = 4KB, SECTOR = 1KB, OOB=128B
 707 +        * page = sector_oob1 + sector_oob2 + sector_oob3 + sector_oob4
 708 +        * sector_oob = data (1KB) + FDM (8B) + ECC parity (21B) + free (3B)
 709 +        *
 710 +        */
 711 +       len = SECTOR_SIZE + mtd->oobsize / chip->ecc.steps;
 712 +
 713 +       for (i = 0; i < chip->ecc.steps; i++) {
 714 +
 715 +               if (buf) {
 716 +                       src = (uint8_t *) buf + i * SECTOR_SIZE;
 717 +                       dst = host->buffer + i * len;
 718 +                       memcpy(dst, src, SECTOR_SIZE);
 719 +               }
 720 +
 721 +               if (oob_on) {
 722 +                       src = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
 723 +                       dst = host->buffer + i * len + SECTOR_SIZE;
 724 +                       memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
 725 +               }
 726 +       }
 727 +
 728 +       return mtk_nfc_write_page(mtd, chip, host->buffer, MTK_OOB_OFF, pg,
 729 +                               MTK_ECC_OFF);
 730 +}
 731 +
 732 +static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data)
 733 +{
 734 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 735 +       struct completion *ecc = &host->ecc.complete;
 736 +       u32 reg, parity_bytes, i;
 737 +       dma_addr_t dma_addr;
 738 +       u32 *parity_region;
 739 +       int rc, ret = 0;
 740 +       size_t dmasize;
 741 +
 742 +       dmasize = SECTOR_SIZE + MTKSDG1_NFI_FDM_REG_SIZE;
 743 +       dma_addr = dma_map_single(host->dev, data, dmasize, DMA_TO_DEVICE);
 744 +       if (dma_mapping_error(host->dev, dma_addr)) {
 745 +               dev_err(host->dev, "dma mapping error\n");
 746 +               return -EINVAL;
 747 +       }
 748 +
 749 +       /* enable the encoder in DMA mode to calculate the ECC bytes  */
 750 +       reg = mtk_ecc_readl(host, MTKSDG1_ECC_ENCCNFG);
 751 +       reg &= (~ECC_ENC_MODE_MASK);
 752 +       reg |= ECC_DMA_MODE;
 753 +       mtk_ecc_writel(host, reg, MTKSDG1_ECC_ENCCNFG);
 754 +
 755 +       mtk_ecc_writel(host, ENC_IRQEN, MTKSDG1_ECC_ENCIRQ_EN);
 756 +       mtk_ecc_writel(host, lower_32_bits(dma_addr), MTKSDG1_ECC_ENCDIADDR);
 757 +
 758 +       init_completion(ecc);
 759 +       mtk_ecc_writew(host, ENC_EN, MTKSDG1_ECC_ENCCON);
 760 +
 761 +       rc = wait_for_completion_timeout(ecc, msecs_to_jiffies(MTK_TIMEOUT));
 762 +       if (!rc) {
 763 +               dev_err(host->dev, "ecc encode done timeout\n");
 764 +               mtk_ecc_writel(host, 0, MTKSDG1_ECC_ENCIRQ_EN);
 765 +               ret = -ETIMEDOUT;
 766 +               goto timeout;
 767 +       }
 768 +
 769 +       mtk_ecc_encoder_idle(host);
 770 +
 771 +       /**
 772 +        * Program ECC bytes to OOB
 773 +        *      per sector oob = FDM + ECC + SPARE
 774 +        */
 775 +
 776 +       parity_region = (u32 *) (data + SECTOR_SIZE + MTKSDG1_NFI_FDM_REG_SIZE);
 777 +       parity_bytes = (chip->ecc.strength * MTK_ECC_PARITY_BITS + 7) >> 3;
 778 +
 779 +       /* write the parity bytes generated by the ECC back to the OOB region */
 780 +       for (i = 0; i < parity_bytes; i += sizeof(u32))
 781 +               *parity_region++ = mtk_ecc_readl(host, MTKSDG1_ECC_ENCPAR0 + i);
 782 +
 783 +timeout:
 784 +
 785 +       dma_unmap_single(host->dev, dma_addr, dmasize, DMA_TO_DEVICE);
 786 +
 787 +       mtk_ecc_writew(host, 0, MTKSDG1_ECC_ENCCON);
 788 +       reg = mtk_ecc_readl(host, MTKSDG1_ECC_ENCCNFG);
 789 +       reg &= (~ECC_ENC_MODE_MASK);
 790 +       reg |= ECC_NFI_MODE;
 791 +       mtk_ecc_writel(host, reg, MTKSDG1_ECC_ENCCNFG);
 792 +
 793 +       return ret;
 794 +}
 795 +
 796 +static int mtk_nfc_write_subpage_hwecc(struct mtd_info *mtd,
 797 +               struct nand_chip *chip, uint32_t offset, uint32_t data_len,
 798 +               const uint8_t *buf, int oob_on, int pg)
 799 +{
 800 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 801 +       uint8_t *src, *dst;
 802 +       u32 start, end;
 803 +       size_t len;
 804 +       int i, ret;
 805 +
 806 +       start = BYTES_TO_SECTORS(offset);
 807 +       end = BYTES_TO_SECTORS(offset + data_len + SECTOR_SIZE - 1);
 808 +
 809 +       len = SECTOR_SIZE + mtd->oobsize / chip->ecc.steps;
 810 +
 811 +       memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
 812 +       for (i = 0; i < chip->ecc.steps; i++) {
 813 +
 814 +               /* write data */
 815 +               src = (uint8_t *) buf + i * SECTOR_SIZE;
 816 +               dst = host->buffer + i * len;
 817 +               memcpy(dst, src, SECTOR_SIZE);
 818 +
 819 +               if (i < start)
 820 +                       continue;
 821 +
 822 +               if (i >= end)
 823 +                       continue;
 824 +
 825 +               /* write fdm */
 826 +               if (oob_on) {
 827 +                       src = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
 828 +                       dst = host->buffer + i * len + SECTOR_SIZE;
 829 +                       memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
 830 +               }
 831 +
 832 +               /* point to the start of data */
 833 +               src = host->buffer + i * len;
 834 +
 835 +               /* program the CRC back to the OOB */
 836 +               ret = mtk_nfc_sector_encode(chip, src);
 837 +               if (ret < 0)
 838 +                       return ret;
 839 +       }
 840 +
 841 +       /* use the data in the private buffer (now with FDM and CRC) to perform
 842 +        * a raw write
 843 +        */
 844 +       src = host->buffer;
 845 +       return mtk_nfc_write_page(mtd, chip, src, MTK_OOB_OFF, pg, MTK_ECC_OFF);
 846 +}
 847 +
 848 +static int mtk_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 849 +                               int page)
 850 +{
 851 +       u8 *buf = chip->buffers->databuf;
 852 +       int ret;
 853 +
 854 +       memset(buf, 0xff, mtd->writesize);
 855 +       chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 856 +       ret = mtk_nfc_write_page_hwecc(mtd, chip, buf, MTK_OOB_ON, page);
 857 +       if (ret < 0)
 858 +               return -EIO;
 859 +
 860 +       chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 861 +       ret = chip->waitfunc(mtd, chip);
 862 +
 863 +       return ret & NAND_STATUS_FAIL ? -EIO : 0;
 864 +}
 865 +
 866 +static int mtk_nfc_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
 867 +                                       int page)
 868 +{
 869 +       int ret;
 870 +
 871 +       chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 872 +       ret = mtk_nfc_write_page_raw(mtd, chip, NULL, MTK_OOB_ON, page);
 873 +       if (ret < 0)
 874 +               return -EIO;
 875 +
 876 +       chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 877 +       ret = chip->waitfunc(mtd, chip);
 878 +
 879 +       return ret & NAND_STATUS_FAIL ? -EIO : 0;
 880 +}
 881 +
 882 +static int mtk_nfc_ecc_check(struct mtd_info *mtd, struct nand_chip *chip,
 883 +                               u32 sectors)
 884 +{
 885 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 886 +       u32 offset, i, err, max_bitflip;
 887 +
 888 +       max_bitflip = 0;
 889 +
 890 +       for (i = 0; i < sectors; i++) {
 891 +               offset = (i >> 2) << 2;
 892 +               err = mtk_ecc_readl(host, MTKSDG1_ECC_DECENUM0 + offset);
 893 +               err = err >> ((i % 4) * 8);
 894 +               err &= ERR_MASK;
 895 +               if (err == ERR_MASK) {
 896 +                       /* uncorrectable errors */
 897 +                       mtd->ecc_stats.failed++;
 898 +                       continue;
 899 +               }
 900 +
 901 +               mtd->ecc_stats.corrected += err;
 902 +               max_bitflip = max_t(u32, max_bitflip, err);
 903 +       }
 904 +
 905 +       return max_bitflip;
 906 +}
 907 +
 908 +static void mtk_nfc_read_fdm(struct nand_chip *chip, u32 sectors)
 909 +{
 910 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 911 +       int i, j, reg;
 912 +       u8 *dst, *src;
 913 +
 914 +       for (i = 0; i < sectors; i++) {
 915 +               /* read FDM register into host memory */
 916 +               for (j = 0; j < ARRAY_SIZE(host->fdm_reg); j++) {
 917 +                       reg = MTKSDG1_NFI_FDM0L + i * MTKSDG1_NFI_FDM_REG_SIZE;
 918 +                       reg += j * sizeof(host->fdm_reg[0]);
 919 +                       host->fdm_reg[j] = mtk_nfi_readl(host, reg);
 920 +               }
 921 +
 922 +               /* copy FDM register from host to OOB */
 923 +               src = (u8 *)host->fdm_reg;
 924 +               dst = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
 925 +               memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
 926 +       }
 927 +}
 928 +
 929 +static int mtk_nfc_update_oob(struct mtd_info *mtd, struct nand_chip *chip,
 930 +                               u8 *buf, u32 sectors)
 931 +{
 932 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
 933 +       int i, bitflips = 0;
 934 +
 935 +       /* if the page is empty, no bitflips and clear data and oob */
 936 +       if (mtk_nfi_readl(host, MTKSDG1_NFI_STA) & STA_EMP_PAGE) {
 937 +               memset(buf, 0xff, SECTORS_TO_BYTES(sectors));
 938 +
 939 +               /* empty page: update OOB with 0xFF */
 940 +               for (i = 0; i < sectors; i++) {
 941 +                       memset(chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE,
 942 +                               0xff, MTKSDG1_NFI_FDM_REG_SIZE);
 943 +               }
 944 +       } else {
 945 +               /* update OOB with HW info */
 946 +               mtk_nfc_read_fdm(chip, sectors);
 947 +
 948 +               /* return the bitflips */
 949 +               bitflips = mtk_nfc_ecc_check(mtd, chip, sectors);
 950 +       }
 951 +
 952 +       return bitflips;
 953 +}
 954 +
 955 +static int mtk_nfc_block_markbad(struct mtd_info *mtd, loff_t ofs)
 956 +{
 957 +       struct nand_chip *chip = mtd_to_nand(mtd);
 958 +       u8 *buf = chip->buffers->databuf;
 959 +       int rc, i, pg;
 960 +
 961 +       /* block_markbad writes 0x00 at data and OOB */
 962 +       memset(buf, 0x00, mtd->writesize + mtd->oobsize);
 963 +
 964 +       /* Write to first/last page(s) if necessary */
 965 +       if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 966 +               ofs += mtd->erasesize - mtd->writesize;
 967 +
 968 +       i = 0;
 969 +       do {
 970 +               pg = (int)(ofs >> chip->page_shift);
 971 +
 972 +               /**
 973 +                *  write 0x00 to DATA & OOB in flash
 974 +                *  No need to reorganize the page since it is all 0x00
 975 +                */
 976 +               chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, pg);
 977 +               rc = mtk_nfc_write_page(mtd, chip, buf, MTK_OOB_OFF, pg,
 978 +                       MTK_ECC_OFF);
 979 +               if (rc < 0)
 980 +                       return rc;
 981 +
 982 +               chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 983 +               rc = chip->waitfunc(mtd, chip);
 984 +               rc = rc & NAND_STATUS_FAIL ? -EIO : 0;
 985 +               if (rc < 0)
 986 +                       return rc;
 987 +
 988 +               ofs += mtd->writesize;
 989 +               i++;
 990 +
 991 +       } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 992 +
 993 +       return 0;
 994 +}
 995 +
 996 +static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 997 +               uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
 998 +               int page, int raw)
 999 +{
1000 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
1001 +       unsigned long timeout = msecs_to_jiffies(MTK_TIMEOUT);
1002 +       u32 reg, column, spare, sectors, start, end;
1003 +       struct completion *nfi, *ecc;
1004 +       const bool use_ecc = !raw;
1005 +       int bitflips = -EIO;
1006 +       dma_addr_t dma_addr;
1007 +       size_t len;
1008 +       u8 *buf;
1009 +       int rc;
1010 +
1011 +       nfi = &host->nfi.complete;
1012 +       ecc = &host->ecc.complete;
1013 +
1014 +       start = BYTES_TO_SECTORS(data_offs);
1015 +       end = BYTES_TO_SECTORS(data_offs + readlen + SECTOR_SIZE - 1);
1016 +       sectors = end - start;
1017 +
1018 +       spare = mtd->oobsize / chip->ecc.steps;
1019 +       column =  start * (SECTOR_SIZE + spare);
1020 +
1021 +       len = SECTORS_TO_BYTES(sectors) + (raw ? sectors * spare : 0);
1022 +       buf = bufpoi + SECTORS_TO_BYTES(start);
1023 +
1024 +       /* map the device memory */
1025 +       dma_addr = dma_map_single(host->dev, buf, len, DMA_FROM_DEVICE);
1026 +       if (dma_mapping_error(host->dev, dma_addr)) {
1027 +               dev_err(host->dev, "dma mapping error\n");
1028 +               return -EINVAL;
1029 +       }
1030 +
1031 +       /* configure the transfer  */
1032 +       reg = mtk_nfi_readw(host, MTKSDG1_NFI_CNFG);
1033 +       reg |= CNFG_DMA_BURST_EN | CNFG_AHB;
1034 +       if (use_ecc) {
1035 +               reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
1036 +               mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
1037 +
1038 +               /* enable encoder */
1039 +               mtk_ecc_decoder_idle(host);
1040 +               mtk_ecc_writel(host, DEC_EN, MTKSDG1_ECC_DECCON);
1041 +       } else
1042 +               mtk_nfi_writew(host, reg, MTKSDG1_NFI_CNFG);
1043 +
1044 +       mtk_nfi_writel(host, sectors << CON_SEC_SHIFT, MTKSDG1_NFI_CON);
1045 +       mtk_nfi_writew(host, INTR_BUSY_RT_EN, MTKSDG1_NFI_INTR_EN);
1046 +
1047 +       init_completion(nfi);
1048 +
1049 +       mtk_nfc_set_address(host, column, page, 2, host->row_nob);
1050 +       mtk_nfc_set_command(host, NAND_CMD_READSTART);
1051 +       rc = wait_for_completion_timeout(nfi, timeout);
1052 +       if (!rc) {
1053 +               dev_err(host->dev, "read busy return timeout\n");
1054 +               goto error;
1055 +       }
1056 +
1057 +       mtk_nfi_writew(host, INTR_AHB_DONE_EN, MTKSDG1_NFI_INTR_EN);
1058 +       mtk_nfi_writel(host, lower_32_bits(dma_addr), MTKSDG1_NFI_STRADDR);
1059 +
1060 +       if (use_ecc) {
1061 +               /* program ECC with sector count */
1062 +               host->ecc.dec_sec = sectors;
1063 +               init_completion(ecc);
1064 +               mtk_ecc_writew(host, DEC_IRQEN, MTKSDG1_ECC_DECIRQ_EN);
1065 +       }
1066 +
1067 +       init_completion(nfi);
1068 +
1069 +       /* start DMA */
1070 +       reg = mtk_nfi_readl(host, MTKSDG1_NFI_CON) | CON_BRD;
1071 +       mtk_nfi_writel(host, reg, MTKSDG1_NFI_CON);
1072 +
1073 +       rc = wait_for_completion_timeout(nfi, timeout);
1074 +       if (!rc)
1075 +               dev_warn(host->dev, "read ahb/dma done timeout\n");
1076 +
1077 +       /* DMA interrupt didn't trigger, check page done just in case */
1078 +       rc = mtk_nfc_subpage_done(host, sectors);
1079 +       if (rc < 0) {
1080 +               dev_err(host->dev, "subpage done timeout\n");
1081 +               goto error;
1082 +       }
1083 +
1084 +       /* raw transfer successful */
1085 +       bitflips = 0;
1086 +
1087 +       if (use_ecc) {
1088 +               rc = wait_for_completion_timeout(ecc, timeout);
1089 +               if (!rc) {
1090 +                       dev_err(host->dev, "ecc decode timeout\n");
1091 +                       host->ecc.dec_sec = 0;
1092 +                       bitflips = -ETIMEDOUT;
1093 +                       goto error;
1094 +               }
1095 +               bitflips = mtk_nfc_update_oob(mtd, chip, buf, sectors);
1096 +       }
1097 +
1098 +error:
1099 +       dma_unmap_single(host->dev, dma_addr, len, DMA_FROM_DEVICE);
1100 +
1101 +       if (use_ecc) {
1102 +               /* make sure the ECC dec irq  is disabled */
1103 +               mtk_ecc_writew(host, 0, MTKSDG1_ECC_DECIRQ_EN);
1104 +               mtk_ecc_decoder_idle(host);
1105 +
1106 +               /* disable ECC dec */
1107 +               mtk_ecc_writew(host, 0, MTKSDG1_ECC_DECCON);
1108 +       }
1109 +
1110 +       mtk_nfi_writel(host, 0, MTKSDG1_NFI_CON);
1111 +
1112 +       return bitflips;
1113 +}
1114 +
1115 +static int mtk_nfc_read_subpage_hwecc(struct mtd_info *mtd,
1116 +                               struct nand_chip *chip, uint32_t data_offs,
1117 +                               uint32_t readlen, uint8_t *bufpoi, int page)
1118 +{
1119 +       return mtk_nfc_read_subpage(mtd, chip, data_offs, readlen,
1120 +                                       bufpoi, page, MTK_ECC_ON);
1121 +}
1122 +
1123 +static int mtk_nfc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1124 +                               uint8_t *buf, int oob_on, int page)
1125 +{
1126 +       return mtk_nfc_read_subpage_hwecc(mtd, chip, 0, mtd->writesize,
1127 +                                               buf, page);
1128 +}
1129 +
1130 +static int mtk_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1131 +                               uint8_t *buf, int oob_on, int page)
1132 +{
1133 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
1134 +       uint8_t *src, *dst;
1135 +       int i, ret;
1136 +       size_t len;
1137 +
1138 +       dst = host->buffer;
1139 +       memset(dst, 0xff, mtd->writesize + mtd->oobsize);
1140 +       ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, dst, page, 1);
1141 +       if (ret < 0)
1142 +               return ret;
1143 +
1144 +       len = SECTOR_SIZE + mtd->oobsize / chip->ecc.steps;
1145 +
1146 +       /* copy to the output buffer */
1147 +       for (i = 0; i < chip->ecc.steps; i++) {
1148 +
1149 +               /* copy sector data */
1150 +               if (buf) {
1151 +                       src = host->buffer + i * len;
1152 +                       dst = buf + i * SECTOR_SIZE;
1153 +                       memcpy(dst, src, SECTOR_SIZE);
1154 +               }
1155 +
1156 +               /* copy FDM data to OOB */
1157 +               if (oob_on) {
1158 +                       src = host->buffer + i * len + SECTOR_SIZE;
1159 +                       dst = chip->oob_poi + i * MTKSDG1_NFI_FDM_REG_SIZE;
1160 +                       memcpy(dst, src, MTKSDG1_NFI_FDM_REG_SIZE);
1161 +               }
1162 +       }
1163 +
1164 +       return ret;
1165 +}
1166 +
1167 +static void mtk_nfc_switch_oob(struct mtd_info *mtd, struct nand_chip *chip,
1168 +                                       uint8_t *buf)
1169 +{
1170 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
1171 +       size_t spare;
1172 +       u32 sectors;
1173 +       u8 *bufpoi;
1174 +       int len;
1175 +
1176 +       spare = mtd->oobsize / chip->ecc.steps;
1177 +       sectors = mtd->writesize / (SECTOR_SIZE + spare);
1178 +
1179 +       /**
1180 +        * MTK: DATA+oob1, DATA+oob2, DATA+oob3 ...
1181 +        * LNX: DATA+OOB
1182 +        */
1183 +       /* point to the last oob_i from the NAND device*/
1184 +       bufpoi = buf + mtd->writesize - (sectors * spare);
1185 +       len = sizeof(host->fdm_reg);
1186 +
1187 +       /* copy NAND oob to private area */
1188 +       memcpy(host->fdm_reg, bufpoi, len);
1189 +
1190 +       /* copy oob_poi to NAND */
1191 +       memcpy(bufpoi, chip->oob_poi, len);
1192 +
1193 +       /* copy NAND oob to oob_poi */
1194 +       memcpy(chip->oob_poi, host->fdm_reg, sizeof(host->fdm_reg));
1195 +       memset(host->fdm_reg, 0x00, len);
1196 +}
1197 +
1198 +static int mtk_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1199 +                               int page)
1200 +{
1201 +       struct mtk_nfc_host *host = nand_get_controller_data(chip);
1202 +       u8 *buf = chip->buffers->databuf;
1203 +       struct mtd_ecc_stats stats;
1204 +       int ret;
1205 +
1206 +       stats = mtd->ecc_stats;
1207 +
1208 +       memset(buf, 0xff, mtd->writesize);
1209 +       chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1210 +
1211 +       ret = mtk_nfc_read_page_hwecc(mtd, chip, buf, 1, page);
1212 +
1213 +       if (host->switch_oob)
1214 +               mtk_nfc_switch_oob(mtd, chip, buf);
1215 +
1216 +       if (ret < mtd->bitflip_threshold)
1217 +               mtd->ecc_stats.corrected = stats.corrected;
1218 +
1219 +       return ret;
1220 +}
1221 +
1222 +static int mtk_nfc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1223 +                               int page)
1224 +{
1225 +       chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1226 +
1227 +       return mtk_nfc_read_page_raw(mtd, chip, NULL, MTK_OOB_ON, page);
1228 +}
1229 +
1230 +static inline void mtk_nfc_hw_init(struct mtk_nfc_host *host)
1231 +{
1232 +       mtk_nfi_writel(host, 0x10804211, MTKSDG1_NFI_ACCCON);
1233 +       mtk_nfi_writew(host, 0xf1, MTKSDG1_NFI_CNRNB);
1234 +       mtk_nfc_hw_reset(host);
1235 +
1236 +       /* clear interrupt */
1237 +       mtk_nfi_readl(host, MTKSDG1_NFI_INTR_STA);
1238 +       mtk_nfi_writel(host, 0, MTKSDG1_NFI_INTR_EN);
1239 +
1240 +       /* ECC encoder init */
1241 +       mtk_ecc_encoder_idle(host);
1242 +       mtk_ecc_writew(host, ENC_DE, MTKSDG1_ECC_ENCCON);
1243 +
1244 +       /* ECC decoder init */
1245 +       mtk_ecc_decoder_idle(host);
1246 +       mtk_ecc_writel(host, DEC_DE, MTKSDG1_ECC_DECCON);
1247 +}
1248 +
1249 +static irqreturn_t mtk_nfi_irq(int irq, void *devid)
1250 +{
1251 +       struct mtk_nfc_host *host = devid;
1252 +       u16 sta, ien;
1253 +
1254 +       sta = mtk_nfi_readw(host, MTKSDG1_NFI_INTR_STA);
1255 +       ien = mtk_nfi_readw(host, MTKSDG1_NFI_INTR_EN);
1256 +
1257 +       if (!(sta & ien))
1258 +               return IRQ_NONE;
1259 +
1260 +       mtk_nfi_writew(host, ~sta & ien, MTKSDG1_NFI_INTR_EN);
1261 +       complete(&host->nfi.complete);
1262 +
1263 +       return IRQ_HANDLED;
1264 +}
1265 +
1266 +static irqreturn_t mtk_ecc_irq(int irq, void *devid)
1267 +{
1268 +       struct mtk_nfc_host *host = devid;
1269 +       u32 reg_val, mask;
1270 +
1271 +       reg_val = mtk_ecc_readw(host, MTKSDG1_ECC_DECIRQ_STA);
1272 +       if (reg_val & DEC_IRQEN) {
1273 +               if (host->ecc.dec_sec) {
1274 +                       mask = 1 << (host->ecc.dec_sec - 1);
1275 +                       reg_val = mtk_ecc_readw(host, MTKSDG1_ECC_DECDONE);
1276 +                       if (mask & reg_val) {
1277 +                               host->ecc.dec_sec = 0;
1278 +                               complete(&host->ecc.complete);
1279 +                               mtk_ecc_writew(host, 0, MTKSDG1_ECC_DECIRQ_EN);
1280 +                       }
1281 +               } else
1282 +                       dev_warn(host->dev, "spurious DEC_IRQ\n");
1283 +
1284 +               return IRQ_HANDLED;
1285 +       }
1286 +
1287 +       reg_val = mtk_ecc_readl(host, MTKSDG1_ECC_ENCIRQ_STA);
1288 +       if (reg_val & ENC_IRQEN) {
1289 +               complete(&host->ecc.complete);
1290 +               mtk_ecc_writel(host, 0, MTKSDG1_ECC_ENCIRQ_EN);
1291 +
1292 +               return IRQ_HANDLED;
1293 +       }
1294 +
1295 +       return IRQ_NONE;
1296 +}
1297 +
1298 +static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk)
1299 +{
1300 +       int ret;
1301 +
1302 +       ret = clk_prepare_enable(clk->nfi_clk);
1303 +       if (ret) {
1304 +               dev_err(dev, "failed to enable nfi clk\n");
1305 +               return ret;
1306 +       }
1307 +
1308 +       ret = clk_prepare_enable(clk->nfiecc_clk);
1309 +       if (ret) {
1310 +               dev_err(dev, "failed to enable nfiecc clk\n");
1311 +               goto out_nfiecc_clk_disable;
1312 +       }
1313 +
1314 +       ret = clk_prepare_enable(clk->pad_clk);
1315 +       if (ret) {
1316 +               dev_err(dev, "failed to enable pad clk\n");
1317 +               goto out_pad_clk_disable;
1318 +       }
1319 +
1320 +       return 0;
1321 +
1322 +out_pad_clk_disable:
1323 +       clk_disable_unprepare(clk->nfiecc_clk);
1324 +
1325 +out_nfiecc_clk_disable:
1326 +       clk_disable_unprepare(clk->nfi_clk);
1327 +
1328 +       return ret;
1329 +}
1330 +
1331 +static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk)
1332 +{
1333 +       clk_disable_unprepare(clk->nfi_clk);
1334 +       clk_disable_unprepare(clk->nfiecc_clk);
1335 +       clk_disable_unprepare(clk->pad_clk);
1336 +}
1337 +
1338 +static int mtk_nfc_probe(struct platform_device *pdev)
1339 +{
1340 +       struct device *dev = &pdev->dev;
1341 +       struct device_node *np = dev->of_node;
1342 +       struct mtk_nfc_host *host;
1343 +       struct nand_chip *chip;
1344 +       struct mtd_info *mtd;
1345 +       struct resource *res;
1346 +       int ret, irq;
1347 +       size_t len;
1348 +
1349 +       host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1350 +       if (!host)
1351 +               return -ENOMEM;
1352 +
1353 +       chip = &host->chip;
1354 +       mtd = nand_to_mtd(chip);
1355 +       host->dev = dev;
1356 +
1357 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358 +       host->nfi.base = devm_ioremap_resource(dev, res);
1359 +       if (IS_ERR(host->nfi.base)) {
1360 +               ret = PTR_ERR(host->nfi.base);
1361 +               dev_err(dev, "no nfi base\n");
1362 +               return ret;
1363 +       }
1364 +
1365 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1366 +       host->ecc.base = devm_ioremap_resource(dev, res);
1367 +       if (IS_ERR(host->ecc.base)) {
1368 +               ret = PTR_ERR(host->ecc.base);
1369 +               dev_err(dev, "no ecc base\n");
1370 +               return ret;
1371 +       }
1372 +
1373 +       host->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1374 +       if (IS_ERR(host->clk.nfi_clk)) {
1375 +               dev_err(dev, "no clk\n");
1376 +               ret = PTR_ERR(host->clk.nfi_clk);
1377 +               return ret;
1378 +       }
1379 +
1380 +       host->clk.nfiecc_clk = devm_clk_get(dev, "nfiecc_clk");
1381 +       if (IS_ERR(host->clk.nfiecc_clk)) {
1382 +               dev_err(dev, "no ecc clk\n");
1383 +               ret = PTR_ERR(host->clk.nfiecc_clk);
1384 +               return ret;
1385 +       }
1386 +
1387 +       host->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1388 +       if (IS_ERR(host->clk.pad_clk)) {
1389 +               dev_err(dev, "no pad clk\n");
1390 +               ret = PTR_ERR(host->clk.pad_clk);
1391 +               return ret;
1392 +       }
1393 +
1394 +       ret = mtk_nfc_enable_clk(dev, &host->clk);
1395 +       if (ret)
1396 +               return ret;
1397 +
1398 +       irq = platform_get_irq(pdev, 0);
1399 +       if (irq < 0) {
1400 +               dev_err(dev, "no nfi irq resource\n");
1401 +               ret = -EINVAL;
1402 +               goto clk_disable;
1403 +       }
1404 +
1405 +       ret = devm_request_irq(dev, irq, mtk_nfi_irq, 0x0, MTK_IRQ_NFI, host);
1406 +       if (ret) {
1407 +               dev_err(dev, "failed to request nfi irq\n");
1408 +               goto clk_disable;
1409 +       }
1410 +
1411 +       irq = platform_get_irq(pdev, 1);
1412 +       if (irq < 0) {
1413 +               dev_err(dev, "no ecc irq resource\n");
1414 +               ret = -EINVAL;
1415 +               goto clk_disable;
1416 +       }
1417 +
1418 +       ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, MTK_IRQ_ECC, host);
1419 +       if (ret) {
1420 +               dev_err(dev, "failed to request ecc irq\n");
1421 +               goto clk_disable;
1422 +       }
1423 +
1424 +       ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1425 +       if (ret) {
1426 +               dev_err(dev, "failed to set dma mask\n");
1427 +               goto clk_disable;
1428 +       }
1429 +
1430 +       platform_set_drvdata(pdev, host);
1431 +
1432 +       mtd_set_of_node(mtd, np);
1433 +       mtd->owner = THIS_MODULE;
1434 +       mtd->dev.parent = dev;
1435 +       mtd->name = MTK_NAME;
1436 +
1437 +       nand_set_controller_data(chip, host);
1438 +       chip->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ;
1439 +       chip->block_markbad = mtk_nfc_block_markbad;
1440 +       chip->select_chip = mtk_nfc_select_chip;
1441 +       chip->read_byte = mtk_nfc_read_byte;
1442 +       chip->cmdfunc = mtk_nfc_cmdfunc;
1443 +       chip->ecc.mode = NAND_ECC_HW;
1444 +       chip->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
1445 +       chip->ecc.write_page_raw = mtk_nfc_write_page_raw;
1446 +       chip->ecc.write_page = mtk_nfc_write_page_hwecc;
1447 +       chip->ecc.write_oob_raw = mtk_nfc_write_oob_raw;
1448 +       chip->ecc.write_oob = mtk_nfc_write_oob;
1449 +       chip->ecc.read_subpage = mtk_nfc_read_subpage_hwecc;
1450 +       chip->ecc.read_page_raw = mtk_nfc_read_page_raw;
1451 +       chip->ecc.read_oob_raw = mtk_nfc_read_oob_raw;
1452 +       chip->ecc.read_page = mtk_nfc_read_page_hwecc;
1453 +       chip->ecc.read_oob = mtk_nfc_read_oob;
1454 +
1455 +       mtk_nfc_hw_init(host);
1456 +
1457 +       ret = nand_scan_ident(mtd, MTK_NAND_MAX_CHIP, NULL);
1458 +       if (ret) {
1459 +               ret = -ENODEV;
1460 +               goto clk_disable;
1461 +       }
1462 +
1463 +       ret = mtk_nfc_hw_runtime_config(mtd);
1464 +       if (ret < 0) {
1465 +               dev_err(dev, "nand device not supported\n");
1466 +               goto clk_disable;
1467 +       }
1468 +
1469 +       len = mtd->writesize + mtd->oobsize;
1470 +       host->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1471 +       if (!host->buffer) {
1472 +               ret = -ENOMEM;
1473 +               goto clk_disable;
1474 +       }
1475 +
1476 +       /* required to create bbt table if not present */
1477 +       host->switch_oob = true;
1478 +       ret = nand_scan_tail(mtd);
1479 +       if (ret) {
1480 +               ret = -ENODEV;
1481 +               goto clk_disable;
1482 +       }
1483 +       host->switch_oob = false;
1484 +
1485 +       ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
1486 +       if (ret) {
1487 +               dev_err(dev, "mtd parse partition error\n");
1488 +               goto nand_free;
1489 +       }
1490 +
1491 +       return 0;
1492 +
1493 +nand_free:
1494 +       nand_release(mtd);
1495 +
1496 +clk_disable:
1497 +       mtk_nfc_disable_clk(&host->clk);
1498 +
1499 +       return ret;
1500 +}
1501 +
1502 +static int mtk_nfc_remove(struct platform_device *pdev)
1503 +{
1504 +       struct mtk_nfc_host *host = platform_get_drvdata(pdev);
1505 +       struct mtd_info *mtd = nand_to_mtd(&host->chip);
1506 +
1507 +       nand_release(mtd);
1508 +       mtk_nfc_disable_clk(&host->clk);
1509 +
1510 +       return 0;
1511 +}
1512 +
1513 +#ifdef CONFIG_PM_SLEEP
1514 +static int mtk_nfc_suspend(struct device *dev)
1515 +{
1516 +       struct mtk_nfc_host *host = dev_get_drvdata(dev);
1517 +       struct mtk_nfc_saved_reg *reg = &host->saved_reg;
1518 +
1519 +       reg->nfi.emp_thresh = mtk_nfi_readl(host, MTKSDG1_NFI_EMPTY_THRESH);
1520 +       reg->ecc.enccnfg = mtk_ecc_readl(host, MTKSDG1_ECC_ENCCNFG);
1521 +       reg->ecc.deccnfg = mtk_ecc_readl(host, MTKSDG1_ECC_DECCNFG);
1522 +       reg->nfi.pagefmt = mtk_nfi_readw(host, MTKSDG1_NFI_PAGEFMT);
1523 +       reg->nfi.acccon = mtk_nfi_readl(host, MTKSDG1_NFI_ACCCON);
1524 +       reg->nfi.cnrnb = mtk_nfi_readw(host, MTKSDG1_NFI_CNRNB);
1525 +       reg->nfi.csel = mtk_nfi_readw(host, MTKSDG1_NFI_CSEL);
1526 +
1527 +       mtk_nfc_disable_clk(&host->clk);
1528 +
1529 +       return 0;
1530 +}
1531 +
1532 +static int mtk_nfc_resume(struct device *dev)
1533 +{
1534 +       struct mtk_nfc_host *host = dev_get_drvdata(dev);
1535 +       struct mtk_nfc_saved_reg *reg = &host->saved_reg;
1536 +       struct nand_chip *chip = &host->chip;
1537 +       struct mtd_info *mtd = nand_to_mtd(chip);
1538 +       int ret;
1539 +       u32 i;
1540 +
1541 +       udelay(200);
1542 +
1543 +       ret = mtk_nfc_enable_clk(dev, &host->clk);
1544 +       if (ret)
1545 +               return ret;
1546 +
1547 +       for (i = 0; i < chip->numchips; i++) {
1548 +               chip->select_chip(mtd, i);
1549 +               chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1550 +       }
1551 +
1552 +       mtk_nfi_writel(host, reg->nfi.emp_thresh, MTKSDG1_NFI_EMPTY_THRESH);
1553 +       mtk_nfi_writew(host, reg->nfi.pagefmt, MTKSDG1_NFI_PAGEFMT);
1554 +       mtk_ecc_writel(host, reg->ecc.enccnfg, MTKSDG1_ECC_ENCCNFG);
1555 +       mtk_ecc_writel(host, reg->ecc.deccnfg, MTKSDG1_ECC_DECCNFG);
1556 +       mtk_nfi_writel(host, reg->nfi.acccon, MTKSDG1_NFI_ACCCON);
1557 +       mtk_nfi_writew(host, reg->nfi.cnrnb, MTKSDG1_NFI_CNRNB);
1558 +       mtk_nfi_writew(host, reg->nfi.csel, MTKSDG1_NFI_CSEL);
1559 +
1560 +       return 0;
1561 +}
1562 +
1563 +static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
1564 +#endif
1565 +
1566 +static const struct of_device_id mtk_nfc_id_table[] = {
1567 +       { .compatible = "mediatek,mt2701-nfc" },
1568 +       {}
1569 +};
1570 +MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
1571 +
1572 +static struct platform_driver mtk_nfc_driver = {
1573 +       .probe  = mtk_nfc_probe,
1574 +       .remove = mtk_nfc_remove,
1575 +       .driver = {
1576 +               .name  = MTK_NAME,
1577 +               .of_match_table = mtk_nfc_id_table,
1578 +#ifdef CONFIG_PM_SLEEP
1579 +               .pm = &mtk_nfc_pm_ops,
1580 +#endif
1581 +       },
1582 +};
1583 +
1584 +module_platform_driver(mtk_nfc_driver);
1585 +
1586 +MODULE_LICENSE("GPL");
1587 +MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
1588 +MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");
1589 +
1590 diff --git a/drivers/mtd/nand/mtksdg1_nand_ecc.h b/drivers/mtd/nand/mtksdg1_nand_ecc.h
1591 new file mode 100644
1592 index 0000000..d90b196
1593 --- /dev/null
1594 +++ b/drivers/mtd/nand/mtksdg1_nand_ecc.h
1595 @@ -0,0 +1,75 @@
1596 +/*
1597 + * MTK smart device ECC engine register.
1598 + * Copyright (C) 2015-2016 MediaTek Inc.
1599 + * Author: Xiaolei.Li <xiaolei.li@mediatek.com>
1600 + *
1601 + * This program is free software; you can redistribute it and/or modify
1602 + * it under the terms of the GNU General Public License version 2 as
1603 + * published by the Free Software Foundation.
1604 + *
1605 + * This program is distributed in the hope that it will be useful,
1606 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1607 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1608 + * GNU General Public License for more details.
1609 + */
1610 +
1611 +#ifndef MTKSDG1_NAND_ECC_H
1612 +#define MTKSDG1_NAND_ECC_H
1613 +
1614 +/* ECC engine register definition */
1615 +#define MTKSDG1_ECC_ENCCON             (0x00)
1616 +#define                ENC_EN                  (1)
1617 +#define                ENC_DE                  (0)
1618 +
1619 +#define MTKSDG1_ECC_ENCCNFG            (0x04)
1620 +#define                ECC_CNFG_4BIT           (0)
1621 +#define                ECC_CNFG_12BIT          (4)
1622 +#define                ECC_NFI_MODE            BIT(5)
1623 +#define                ECC_DMA_MODE            (0)
1624 +#define                ECC_ENC_MODE_MASK       (0x3 << 5)
1625 +#define                ECC_MS_SHIFT            (16)
1626 +
1627 +#define MTKSDG1_ECC_ENCDIADDR          (0x08)
1628 +
1629 +#define MTKSDG1_ECC_ENCIDLE            (0x0C)
1630 +#define                ENC_IDLE                BIT(0)
1631 +
1632 +#define MTKSDG1_ECC_ENCPAR0            (0x10)
1633 +#define MTKSDG1_ECC_ENCSTA             (0x7C)
1634 +
1635 +#define MTKSDG1_ECC_ENCIRQ_EN          (0x80)
1636 +#define                ENC_IRQEN               BIT(0)
1637 +
1638 +#define MTKSDG1_ECC_ENCIRQ_STA         (0x84)
1639 +
1640 +#define MTKSDG1_ECC_DECCON             (0x100)
1641 +#define                DEC_EN                  (1)
1642 +#define                DEC_DE                  (0)
1643 +
1644 +#define MTKSDG1_ECC_DECCNFG            (0x104)
1645 +#define                DEC_EMPTY_EN            BIT(31)
1646 +#define                DEC_CNFG_FER            (0x1 << 12)
1647 +#define                DEC_CNFG_EL             (0x2 << 12)
1648 +#define                DEC_CNFG_CORRECT        (0x3 << 12)
1649 +
1650 +#define MTKSDG1_ECC_DECIDLE            (0x10C)
1651 +#define                DEC_IDLE                BIT(0)
1652 +
1653 +#define MTKSDG1_ECC_DECFER             (0x110)
1654 +
1655 +#define MTKSDG1_ECC_DECENUM0           (0x114)
1656 +#define                ERR_MASK                (0x3f)
1657 +
1658 +#define MTKSDG1_ECC_DECDONE            (0x124)
1659 +
1660 +#define MTKSDG1_ECC_DECEL0             (0x128)
1661 +
1662 +#define MTKSDG1_ECC_DECIRQ_EN          (0x200)
1663 +#define                DEC_IRQEN               BIT(0)
1664 +
1665 +#define MTKSDG1_ECC_DECIRQ_STA         (0x204)
1666 +
1667 +#define MTKSDG1_ECC_DECFSM             (0x208)
1668 +#define                DECFSM_MASK             (0x7f0f0f0f)
1669 +#define                DECFSM_IDLE             (0x01010101)
1670 +#endif
1671 diff --git a/drivers/mtd/nand/mtksdg1_nand_nfi.h b/drivers/mtd/nand/mtksdg1_nand_nfi.h
1672 new file mode 100644
1673 index 0000000..a9aa6f6
1674 --- /dev/null
1675 +++ b/drivers/mtd/nand/mtksdg1_nand_nfi.h
1676 @@ -0,0 +1,119 @@
1677 +/*
1678 + * MTK smart device NAND Flash controller register.
1679 + * Copyright (C) 2015-2016 MediaTek Inc.
1680 + * Author: Xiaolei.Li <xiaolei.li@mediatek.com>
1681 + *
1682 + * This program is free software; you can redistribute it and/or modify
1683 + * it under the terms of the GNU General Public License version 2 as
1684 + * published by the Free Software Foundation.
1685 + *
1686 + * This program is distributed in the hope that it will be useful,
1687 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1688 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1689 + * GNU General Public License for more details.
1690 + */
1691 +
1692 +#ifndef MTKSDG1_NAND_NFI_H
1693 +#define MTKSDG1_NAND_NFI_H
1694 +
1695 +/* NAND controller register definition */
1696 +#define MTKSDG1_NFI_CNFG               (0x00)
1697 +#define                CNFG_AHB                BIT(0)
1698 +#define                CNFG_READ_EN            BIT(1)
1699 +#define                CNFG_DMA_BURST_EN       BIT(2)
1700 +#define                CNFG_BYTE_RW            BIT(6)
1701 +#define                CNFG_HW_ECC_EN          BIT(8)
1702 +#define                CNFG_AUTO_FMT_EN        BIT(9)
1703 +#define                CNFG_OP_IDLE            (0 << 12)
1704 +#define                CNFG_OP_READ            (1 << 12)
1705 +#define                CNFG_OP_SRD             (2 << 12)
1706 +#define                CNFG_OP_PRGM            (3 << 12)
1707 +#define                CNFG_OP_ERASE           (4 << 12)
1708 +#define                CNFG_OP_RESET           (5 << 12)
1709 +#define                CNFG_OP_CUST            (6 << 12)
1710 +
1711 +#define MTKSDG1_NFI_PAGEFMT            (0x04)
1712 +#define                PAGEFMT_FDM_ECC_SHIFT   (12)
1713 +#define                PAGEFMT_FDM_SHIFT       (8)
1714 +#define                PAGEFMT_SPARE_16        (0)
1715 +#define                PAGEFMT_SPARE_32        (4)
1716 +#define                PAGEFMT_SPARE_SHIFT     (4)
1717 +#define                PAGEFMT_SEC_SEL_512     BIT(2)
1718 +#define                PAGEFMT_512_2K          (0)
1719 +#define                PAGEFMT_2K_4K           (1)
1720 +#define                PAGEFMT_4K_8K           (2)
1721 +
1722 +/* NFI control */
1723 +#define MTKSDG1_NFI_CON                        (0x08)
1724 +#define                CON_FIFO_FLUSH          BIT(0)
1725 +#define                CON_NFI_RST             BIT(1)
1726 +#define                CON_SRD                 BIT(4)  /* single read */
1727 +#define                CON_BRD                 BIT(8)  /* burst  read */
1728 +#define                CON_BWR                 BIT(9)  /* burst  write */
1729 +#define                CON_SEC_SHIFT           (12)
1730 +
1731 +/* Timming control register */
1732 +#define MTKSDG1_NFI_ACCCON             (0x0C)
1733 +
1734 +#define MTKSDG1_NFI_INTR_EN            (0x10)
1735 +#define                INTR_RD_DONE_EN         BIT(0)
1736 +#define                INTR_WR_DONE_EN         BIT(1)
1737 +#define                INTR_RST_DONE_EN        BIT(2)
1738 +#define                INTR_ERS_DONE_EN        BIT(3)
1739 +#define                INTR_BUSY_RT_EN         BIT(4)
1740 +#define                INTR_AHB_DONE_EN        BIT(6)
1741 +
1742 +#define MTKSDG1_NFI_INTR_STA           (0x14)
1743 +
1744 +#define MTKSDG1_NFI_CMD                        (0x20)
1745 +
1746 +#define MTKSDG1_NFI_ADDRNOB            (0x30)
1747 +#define                ADDR_ROW_NOB_SHIFT      (4)
1748 +
1749 +#define MTKSDG1_NFI_COLADDR            (0x34)
1750 +#define MTKSDG1_NFI_ROWADDR            (0x38)
1751 +#define MTKSDG1_NFI_STRDATA            (0x40)
1752 +#define MTKSDG1_NFI_CNRNB              (0x44)
1753 +#define MTKSDG1_NFI_DATAW              (0x50)
1754 +#define MTKSDG1_NFI_DATAR              (0x54)
1755 +#define MTKSDG1_NFI_PIO_DIRDY          (0x58)
1756 +#define                PIO_DI_RDY              (0x01)
1757 +
1758 +/* NFI state*/
1759 +#define MTKSDG1_NFI_STA                        (0x60)
1760 +#define                STA_CMD                 BIT(0)
1761 +#define                STA_ADDR                BIT(1)
1762 +#define                STA_DATAR               BIT(2)
1763 +#define                STA_DATAW               BIT(3)
1764 +#define                STA_EMP_PAGE            BIT(12)
1765 +
1766 +#define MTKSDG1_NFI_FIFOSTA            (0x64)
1767 +
1768 +#define MTKSDG1_NFI_ADDRCNTR           (0x70)
1769 +#define                CNTR_MASK               GENMASK(16, 12)
1770 +
1771 +#define MTKSDG1_NFI_STRADDR            (0x80)
1772 +#define MTKSDG1_NFI_BYTELEN            (0x84)
1773 +#define MTKSDG1_NFI_CSEL               (0x90)
1774 +#define MTKSDG1_NFI_IOCON              (0x94)
1775 +
1776 +/* FDM data for sector: FDM0[L,H] - FDMF[L,H] */
1777 +#define MTKSDG1_NFI_FDM_MAX_SEC                (0x10)
1778 +#define MTKSDG1_NFI_FDM_REG_SIZE       (8)
1779 +#define MTKSDG1_NFI_FDM0L              (0xA0)
1780 +#define MTKSDG1_NFI_FDM0M              (0xA4)
1781 +
1782 +
1783 +#define MTKSDG1_NFI_FIFODATA0          (0x190)
1784 +#define MTKSDG1_NFI_DEBUG_CON1         (0x220)
1785 +#define MTKSDG1_NFI_MASTER_STA         (0x224)
1786 +#define                MASTER_STA_MASK         (0x0FFF)
1787 +
1788 +#define MTKSDG1_NFI_RANDOM_CNFG                (0x238)
1789 +#define MTKSDG1_NFI_EMPTY_THRESH       (0x23C)
1790 +#define MTKSDG1_NFI_NAND_TYPE          (0x240)
1791 +#define MTKSDG1_NFI_ACCCON1            (0x244)
1792 +#define MTKSDG1_NFI_DELAY_CTRL         (0x248)
1793 +
1794 +#endif
1795 +
1796 --
1797 1.7.10.4
1798