target/linux/mediatek/patches-4.4/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch

   1 From 97478bae3a11b5e87d61b88267e915f7c5ddf4e9 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 6 Jan 2016 21:55:10 +0100
   4 Subject: [PATCH 24/81] dt-bindings: add MediaTek PCIe binding documentation
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  .../devicetree/bindings/pci/mediatek-pcie.txt      |  140 ++++++++++++++++++++
   9  arch/arm/boot/dts/mt7623.dtsi                      |   12 ++
  10  2 files changed, 152 insertions(+)
  11  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  12
  13 --- /dev/null
  14 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  15 @@ -0,0 +1,140 @@
  16 +Mediatek PCIe controller
  17 +
  18 +Required properties:
  19 +- compatible: Should be one of:
  20 +       - "mediatek,mt2701-pcie"
  21 +       - "mediatek,mt7623-pcie"
  22 +- device_type: Must be "pci"
  23 +- reg: A list of physical base address and length for each set of controller
  24 +  registers. A list of register ranges to use. Must contain an
  25 +    entry for each entry in the reg-names property.
  26 +- reg-names: Must include the following entries:
  27 +  "pcie": PCIe registers
  28 +  "pcie phy0": PCIe PHY0 registers
  29 +  "pcie phy1": PCIe PHY0 registers
  30 +  "pcie phy2": PCIe PHY0 registers
  31 +- interrupts: A list of interrupt outputs of the controller. Must contain an
  32 +  entry for each entry in the interrupt-names property.
  33 +- interrupt-names: Must include the following entries:
  34 +  "pcie0": The interrupt that is asserted for port0
  35 +  "pcie1": The interrupt that is asserted for port1
  36 +  "pcie2": The interrupt that is asserted for port2
  37 +- bus-range: Range of bus numbers associated with this controller
  38 +- #address-cells: Address representation for root ports (must be 3)
  39 +- #size-cells: Size representation for root ports (must be 2)
  40 +- ranges: Describes the translation of addresses for root ports and standard
  41 +  PCI regions. The entries must be 6 cells each.
  42 +  Please refer to the standard PCI bus binding document for a more detailed
  43 +  explanation.
  44 +- #interrupt-cells: Size representation for interrupts (must be 1)
  45 +- clocks: Must contain an entry for each entry in clock-names.
  46 +  See ../clocks/clock-bindings.txt for details.
  47 +- clock-names: Must include the following entries:
  48 +  - pcie0
  49 +  - pcie1
  50 +  - pcie2
  51 +- resets: Must contain an entry for each entry in reset-names.
  52 +  See ../reset/reset.txt for details.
  53 +- reset-names: Must include the following entries:
  54 +  - pcie0
  55 +  - pcie1
  56 +  - pcie2
  57 +- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range.
  58 +Root ports are defined as subnodes of the PCIe controller node.
  59 +
  60 +Required properties:
  61 +- device_type: Must be "pci"
  62 +- assigned-addresses: Address and size of the port configuration registers
  63 +- reg: PCI bus address of the root port
  64 +- #address-cells: Must be 3
  65 +- #size-cells: Must be 2
  66 +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
  67 +  property is sufficient.
  68 +
  69 +Example:
  70 +
  71 +SoC DTSI:
  72 +
  73 +       hifsys: clock-controller@1a000000 {
  74 +               compatible = "mediatek,mt7623-hifsys",
  75 +                            "mediatek,mt2701-hifsys",
  76 +                            "syscon";
  77 +               reg = <0 0x1a000000 0 0x1000>;
  78 +               #clock-cells = <1>;
  79 +               #reset-cells = <1>;
  80 +       };
  81 +
  82 +       pcie-controller@1a140000 {
  83 +               compatible = "mediatek,mt7623-pcie";
  84 +               device_type = "pci";
  85 +               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
  86 +                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
  87 +                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
  88 +                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
  89 +               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
  90 +               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
  91 +                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
  92 +                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  93 +               interrupt-names = "pcie0", "pcie1", "pcie2";
  94 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
  95 +               clock-names = "pcie";
  96 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
  97 +               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
  98 +                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
  99 +                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 100 +               reset-names = "pcie0", "pice1", "pcie2";
 101 +
 102 +               bus-range = <0x00 0xff>;
 103 +               #address-cells = <3>;
 104 +               #size-cells = <2>;
 105 +
 106 +                mediatek,hifsys = <&hifsys>;
 107 +
 108 +               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
 109 +                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
 110 +
 111 +               status = "disabled";
 112 +
 113 +               pcie@1,0 {
 114 +                       device_type = "pci";
 115 +                       reg = <0x0800 0 0 0 0>;
 116 +
 117 +                       #address-cells = <3>;
 118 +                       #size-cells = <2>;
 119 +                       ranges;
 120 +
 121 +                       status = "disabled";
 122 +               };
 123 +
 124 +               pcie@2,0{
 125 +                       device_type = "pci";
 126 +                       reg = <0x1000 0 0 0 0>;
 127 +
 128 +                       #address-cells = <3>;
 129 +                       #size-cells = <2>;
 130 +                       ranges;
 131 +
 132 +                       status = "disabled";
 133 +               };
 134 +
 135 +               pcie@3,0{
 136 +                       device_type = "pci";
 137 +                       reg = <0x1800 0 0 0 0>;
 138 +
 139 +                       #address-cells = <3>;
 140 +                       #size-cells = <2>;
 141 +                       ranges;
 142 +
 143 +                       status = "disabled";
 144 +               };
 145 +       };
 146 +
 147 +Board DTS:
 148 +
 149 +       pcie-controller {
 150 +               status = "okay";
 151 +
 152 +               pci@1,0 {
 153 +                       status = "okay";
 154 +               };
 155 +       };
 156 --- a/arch/arm/boot/dts/mt7623.dtsi
 157 +++ b/arch/arm/boot/dts/mt7623.dtsi
 158 @@ -292,6 +292,18 @@
 159                 status = "disabled";
 160         };
 161
 162 +       nand: nfi@1100d000 {
 163 +               compatible = "mediatek,mt2701-nfc";
 164 +               reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
 165 +               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
 166 +                            <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 167 +               clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
 168 +                        <&pericfg CLK_PERI_NFI_PAD>;
 169 +               clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
 170 +               nand-on-flash-bbt;
 171 +               status = "disabled";
 172 +       };
 173 +
 174         mmc0: mmc@11230000 {
 175                 compatible = "mediatek,mt7623-mmc",
 176                              "mediatek,mt8135-mmc";