target/linux/mediatek/patches-4.4/0020-arm64-dts-mediatek-add-xHCI-usb-phy-for-mt8173.patch

   1 From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
   2 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
   3 Date: Tue, 17 Nov 2015 17:18:41 +0800
   4 Subject: [PATCH 20/66] arm64: dts: mediatek: add xHCI & usb phy for mt8173
   5
   6 add xHCI and phy drivers for MT8173-EVB
   7
   8 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
   9 ---
  10  arch/arm64/boot/dts/mediatek/mt8173-evb.dts |   16 ++++++++++
  11  arch/arm64/boot/dts/mediatek/mt8173.dtsi    |   42 +++++++++++++++++++++++++++
  12  2 files changed, 58 insertions(+)
  13
  14 diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
  15 index 811cb76..9b1482a 100644
  16 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
  17 +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
  18 @@ -13,6 +13,7 @@
  19   */
  20
  21  /dts-v1/;
  22 +#include <dt-bindings/gpio/gpio.h>
  23  #include "mt8173.dtsi"
  24
  25  / {
  26 @@ -32,6 +33,15 @@
  27         };
  28
  29         chosen { };
  30 +
  31 +       usb_p1_vbus: regulator@0 {
  32 +               compatible = "regulator-fixed";
  33 +               regulator-name = "usb_vbus";
  34 +               regulator-min-microvolt = <5000000>;
  35 +               regulator-max-microvolt = <5000000>;
  36 +               gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
  37 +               enable-active-high;
  38 +       };
  39  };
  40
  41  &i2c1 {
  42 @@ -408,3 +418,9 @@
  43  &uart0 {
  44         status = "okay";
  45  };
  46 +
  47 +&usb30 {
  48 +       vusb33-supply = <&mt6397_vusb_reg>;
  49 +       vbus-supply = <&usb_p1_vbus>;
  50 +       mediatek,wakeup-src = <1>;
  51 +};
  52 diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
  53 index 4dd5f93..c1fd275 100644
  54 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
  55 +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
  56 @@ -14,6 +14,7 @@
  57  #include <dt-bindings/clock/mt8173-clk.h>
  58  #include <dt-bindings/interrupt-controller/irq.h>
  59  #include <dt-bindings/interrupt-controller/arm-gic.h>
  60 +#include <dt-bindings/phy/phy.h>
  61  #include <dt-bindings/power/mt8173-power.h>
  62  #include <dt-bindings/reset-controller/mt8173-resets.h>
  63  #include "mt8173-pinfunc.h"
  64 @@ -510,6 +511,47 @@
  65                         status = "disabled";
  66                 };
  67
  68 +               usb30: usb@11270000 {
  69 +                       compatible = "mediatek,mt8173-xhci";
  70 +                       reg = <0 0x11270000 0 0x1000>,
  71 +                             <0 0x11280700 0 0x0100>;
  72 +                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
  73 +                       power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
  74 +                       clocks = <&topckgen CLK_TOP_USB30_SEL>,
  75 +                                <&pericfg CLK_PERI_USB0>,
  76 +                                <&pericfg CLK_PERI_USB1>;
  77 +                       clock-names = "sys_ck",
  78 +                                     "wakeup_deb_p0",
  79 +                                     "wakeup_deb_p1";
  80 +                       phys = <&phy_port0 PHY_TYPE_USB3>,
  81 +                              <&phy_port1 PHY_TYPE_USB2>;
  82 +                       mediatek,syscon-wakeup = <&pericfg>;
  83 +                       status = "okay";
  84 +               };
  85 +
  86 +               u3phy: usb-phy@11290000 {
  87 +                       compatible = "mediatek,mt8173-u3phy";
  88 +                       reg = <0 0x11290000 0 0x800>;
  89 +                       clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
  90 +                       clock-names = "u3phya_ref";
  91 +                       #address-cells = <2>;
  92 +                       #size-cells = <2>;
  93 +                       ranges;
  94 +                       status = "okay";
  95 +
  96 +                       phy_port0: port@11290800 {
  97 +                               reg = <0 0x11290800 0 0x800>;
  98 +                               #phy-cells = <1>;
  99 +                               status = "okay";
 100 +                       };
 101 +
 102 +                       phy_port1: port@11291000 {
 103 +                               reg = <0 0x11291000 0 0x800>;
 104 +                               #phy-cells = <1>;
 105 +                               status = "okay";
 106 +                       };
 107 +               };
 108 +
 109                 mmsys: clock-controller@14000000 {
 110                         compatible = "mediatek,mt8173-mmsys", "syscon";
 111                         reg = <0 0x14000000 0 0x1000>;
 112 --
 113 1.7.10.4
 114