target/linux/mediatek/patches-4.4/0019-xhci-mediatek-support-MTK-xHCI-host-controller.patch

   1 From 651d8fff94718c7e48b8a40d7774878eb8ed62ee Mon Sep 17 00:00:00 2001
   2 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
   3 Date: Tue, 17 Nov 2015 17:18:40 +0800
   4 Subject: [PATCH 19/81] xhci: mediatek: support MTK xHCI host controller
   5
   6 There some vendor quirks for MTK xhci host controller:
   7 1. It defines some extra SW scheduling parameters for HW
   8   to minimize the scheduling effort for synchronous and
   9   interrupt endpoints. The parameters are put into reseved
  10   DWs of slot context and endpoint context.
  11 2. Its IMODI unit for Interrupter Moderation register is
  12   8 times as much as that defined in xHCI spec.
  13 3. Its TDS in  Normal TRB defines a number of packets that
  14   remains to be transferred for a TD after processing all
  15   Max packets in all previous TRBs.
  16
  17 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  18 Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
  19 Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  20 ---
  21  drivers/usb/host/Kconfig        |    9 +
  22  drivers/usb/host/Makefile       |    4 +
  23  drivers/usb/host/xhci-mtk-sch.c |  415 +++++++++++++++++++++
  24  drivers/usb/host/xhci-mtk.c     |  763 +++++++++++++++++++++++++++++++++++++++
  25  drivers/usb/host/xhci-mtk.h     |  162 +++++++++
  26  drivers/usb/host/xhci-ring.c    |   16 +-
  27  drivers/usb/host/xhci.c         |   19 +-
  28  drivers/usb/host/xhci.h         |    1 +
  29  8 files changed, 1383 insertions(+), 6 deletions(-)
  30  create mode 100644 drivers/usb/host/xhci-mtk-sch.c
  31  create mode 100644 drivers/usb/host/xhci-mtk.c
  32  create mode 100644 drivers/usb/host/xhci-mtk.h
  33
  34 --- a/drivers/usb/host/Kconfig
  35 +++ b/drivers/usb/host/Kconfig
  36 @@ -41,6 +41,15 @@ config USB_XHCI_PLATFORM
  37
  38           If unsure, say N.
  39
  40 +config USB_XHCI_MTK
  41 +       tristate "xHCI support for Mediatek MT65xx"
  42 +       select MFD_SYSCON
  43 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  44 +       ---help---
  45 +         Say 'Y' to enable the support for the xHCI host controller
  46 +         found in Mediatek MT65xx SoCs.
  47 +         If unsure, say N.
  48 +
  49  config USB_XHCI_MVEBU
  50         tristate "xHCI support for Marvell Armada 375/38x"
  51         select USB_XHCI_PLATFORM
  52 --- a/drivers/usb/host/Makefile
  53 +++ b/drivers/usb/host/Makefile
  54 @@ -13,6 +13,9 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
  55  xhci-hcd-y := xhci.o xhci-mem.o
  56  xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
  57  xhci-hcd-y += xhci-trace.o
  58 +ifneq ($(CONFIG_USB_XHCI_MTK), )
  59 +       xhci-hcd-y += xhci-mtk-sch.o
  60 +endif
  61
  62  xhci-plat-hcd-y := xhci-plat.o
  63  ifneq ($(CONFIG_USB_XHCI_MVEBU), )
  64 @@ -64,6 +67,7 @@ obj-$(CONFIG_USB_FHCI_HCD)    += fhci.o
  65  obj-$(CONFIG_USB_XHCI_HCD)     += xhci-hcd.o
  66  obj-$(CONFIG_USB_XHCI_PCI)     += xhci-pci.o
  67  obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
  68 +obj-$(CONFIG_USB_XHCI_MTK)     += xhci-mtk.o
  69  obj-$(CONFIG_USB_SL811_HCD)    += sl811-hcd.o
  70  obj-$(CONFIG_USB_SL811_CS)     += sl811_cs.o
  71  obj-$(CONFIG_USB_U132_HCD)     += u132-hcd.o
  72 --- /dev/null
  73 +++ b/drivers/usb/host/xhci-mtk-sch.c
  74 @@ -0,0 +1,415 @@
  75 +/*
  76 + * Copyright (c) 2015 MediaTek Inc.
  77 + * Author:
  78 + *  Zhigang.Wei <zhigang.wei@mediatek.com>
  79 + *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
  80 + *
  81 + * This software is licensed under the terms of the GNU General Public
  82 + * License version 2, as published by the Free Software Foundation, and
  83 + * may be copied, distributed, and modified under those terms.
  84 + *
  85 + * This program is distributed in the hope that it will be useful,
  86 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  87 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  88 + * GNU General Public License for more details.
  89 + *
  90 + */
  91 +
  92 +#include <linux/kernel.h>
  93 +#include <linux/module.h>
  94 +#include <linux/slab.h>
  95 +
  96 +#include "xhci.h"
  97 +#include "xhci-mtk.h"
  98 +
  99 +#define SS_BW_BOUNDARY 51000
 100 +/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */
 101 +#define HS_BW_BOUNDARY 6144
 102 +/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
 103 +#define FS_PAYLOAD_MAX 188
 104 +
 105 +/* mtk scheduler bitmasks */
 106 +#define EP_BPKTS(p)    ((p) & 0x3f)
 107 +#define EP_BCSCOUNT(p) (((p) & 0x7) << 8)
 108 +#define EP_BBM(p)      ((p) << 11)
 109 +#define EP_BOFFSET(p)  ((p) & 0x3fff)
 110 +#define EP_BREPEAT(p)  (((p) & 0x7fff) << 16)
 111 +
 112 +static int is_fs_or_ls(enum usb_device_speed speed)
 113 +{
 114 +       return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
 115 +}
 116 +
 117 +/*
 118 +* get the index of bandwidth domains array which @ep belongs to.
 119 +*
 120 +* the bandwidth domain array is saved to @sch_array of struct xhci_hcd_mtk,
 121 +* each HS root port is treated as a single bandwidth domain,
 122 +* but each SS root port is treated as two bandwidth domains, one for IN eps,
 123 +* one for OUT eps.
 124 +* @real_port value is defined as follow according to xHCI spec:
 125 +* 1 for SSport0, ..., N+1 for SSportN, N+2 for HSport0, N+3 for HSport1, etc
 126 +* so the bandwidth domain array is organized as follow for simplification:
 127 +* SSport0-OUT, SSport0-IN, ..., SSportX-OUT, SSportX-IN, HSport0, ..., HSportY
 128 +*/
 129 +static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev,
 130 +       struct usb_host_endpoint *ep)
 131 +{
 132 +       struct xhci_virt_device *virt_dev;
 133 +       int bw_index;
 134 +
 135 +       virt_dev = xhci->devs[udev->slot_id];
 136 +
 137 +       if (udev->speed == USB_SPEED_SUPER) {
 138 +               if (usb_endpoint_dir_out(&ep->desc))
 139 +                       bw_index = (virt_dev->real_port - 1) * 2;
 140 +               else
 141 +                       bw_index = (virt_dev->real_port - 1) * 2 + 1;
 142 +       } else {
 143 +               /* add one more for each SS port */
 144 +               bw_index = virt_dev->real_port + xhci->num_usb3_ports - 1;
 145 +       }
 146 +
 147 +       return bw_index;
 148 +}
 149 +
 150 +static void setup_sch_info(struct usb_device *udev,
 151 +               struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep)
 152 +{
 153 +       u32 ep_type;
 154 +       u32 ep_interval;
 155 +       u32 max_packet_size;
 156 +       u32 max_burst;
 157 +       u32 mult;
 158 +       u32 esit_pkts;
 159 +
 160 +       ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
 161 +       ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info));
 162 +       max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
 163 +       max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2));
 164 +       mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info));
 165 +
 166 +       sch_ep->esit = 1 << ep_interval;
 167 +       sch_ep->offset = 0;
 168 +       sch_ep->burst_mode = 0;
 169 +
 170 +       if (udev->speed == USB_SPEED_HIGH) {
 171 +               sch_ep->cs_count = 0;
 172 +
 173 +               /*
 174 +                * usb_20 spec section5.9
 175 +                * a single microframe is enough for HS synchromous endpoints
 176 +                * in a interval
 177 +                */
 178 +               sch_ep->num_budget_microframes = 1;
 179 +               sch_ep->repeat = 0;
 180 +
 181 +               /*
 182 +                * xHCI spec section6.2.3.4
 183 +                * @max_burst is the number of additional transactions
 184 +                * opportunities per microframe
 185 +                */
 186 +               sch_ep->pkts = max_burst + 1;
 187 +               sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
 188 +       } else if (udev->speed == USB_SPEED_SUPER) {
 189 +               /* usb3_r1 spec section4.4.7 & 4.4.8 */
 190 +               sch_ep->cs_count = 0;
 191 +               esit_pkts = (mult + 1) * (max_burst + 1);
 192 +               if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
 193 +                       sch_ep->pkts = esit_pkts;
 194 +                       sch_ep->num_budget_microframes = 1;
 195 +                       sch_ep->repeat = 0;
 196 +               }
 197 +
 198 +               if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
 199 +                       if (esit_pkts <= sch_ep->esit)
 200 +                               sch_ep->pkts = 1;
 201 +                       else
 202 +                               sch_ep->pkts = roundup_pow_of_two(esit_pkts)
 203 +                                       / sch_ep->esit;
 204 +
 205 +                       sch_ep->num_budget_microframes =
 206 +                               DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
 207 +
 208 +                       if (sch_ep->num_budget_microframes > 1)
 209 +                               sch_ep->repeat = 1;
 210 +                       else
 211 +                               sch_ep->repeat = 0;
 212 +               }
 213 +               sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
 214 +       } else if (is_fs_or_ls(udev->speed)) {
 215 +
 216 +               /*
 217 +                * usb_20 spec section11.18.4
 218 +                * assume worst cases
 219 +                */
 220 +               sch_ep->repeat = 0;
 221 +               sch_ep->pkts = 1; /* at most one packet for each microframe */
 222 +               if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
 223 +                       sch_ep->cs_count = 3; /* at most need 3 CS*/
 224 +                       /* one for SS and one for budgeted transaction */
 225 +                       sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
 226 +                       sch_ep->bw_cost_per_microframe = max_packet_size;
 227 +               }
 228 +               if (ep_type == ISOC_OUT_EP) {
 229 +
 230 +                       /*
 231 +                        * the best case FS budget assumes that 188 FS bytes
 232 +                        * occur in each microframe
 233 +                        */
 234 +                       sch_ep->num_budget_microframes = DIV_ROUND_UP(
 235 +                               max_packet_size, FS_PAYLOAD_MAX);
 236 +                       sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
 237 +                       sch_ep->cs_count = sch_ep->num_budget_microframes;
 238 +               }
 239 +               if (ep_type == ISOC_IN_EP) {
 240 +                       /* at most need additional two CS. */
 241 +                       sch_ep->cs_count = DIV_ROUND_UP(
 242 +                               max_packet_size, FS_PAYLOAD_MAX) + 2;
 243 +                       sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
 244 +                       sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
 245 +               }
 246 +       }
 247 +}
 248 +
 249 +/* Get maximum bandwidth when we schedule at offset slot. */
 250 +static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw,
 251 +       struct mu3h_sch_ep_info *sch_ep, u32 offset)
 252 +{
 253 +       u32 num_esit;
 254 +       u32 max_bw = 0;
 255 +       int i;
 256 +       int j;
 257 +
 258 +       num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
 259 +       for (i = 0; i < num_esit; i++) {
 260 +               u32 base = offset + i * sch_ep->esit;
 261 +
 262 +               for (j = 0; j < sch_ep->num_budget_microframes; j++) {
 263 +                       if (sch_bw->bus_bw[base + j] > max_bw)
 264 +                               max_bw = sch_bw->bus_bw[base + j];
 265 +               }
 266 +       }
 267 +       return max_bw;
 268 +}
 269 +
 270 +static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
 271 +       struct mu3h_sch_ep_info *sch_ep, int bw_cost)
 272 +{
 273 +       u32 num_esit;
 274 +       u32 base;
 275 +       int i;
 276 +       int j;
 277 +
 278 +       num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
 279 +       for (i = 0; i < num_esit; i++) {
 280 +               base = sch_ep->offset + i * sch_ep->esit;
 281 +               for (j = 0; j < sch_ep->num_budget_microframes; j++)
 282 +                       sch_bw->bus_bw[base + j] += bw_cost;
 283 +       }
 284 +}
 285 +
 286 +static int check_sch_bw(struct usb_device *udev,
 287 +       struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep)
 288 +{
 289 +       u32 offset;
 290 +       u32 esit;
 291 +       u32 num_budget_microframes;
 292 +       u32 min_bw;
 293 +       u32 min_index;
 294 +       u32 worst_bw;
 295 +       u32 bw_boundary;
 296 +
 297 +       if (sch_ep->esit > XHCI_MTK_MAX_ESIT)
 298 +               sch_ep->esit = XHCI_MTK_MAX_ESIT;
 299 +
 300 +       esit = sch_ep->esit;
 301 +       num_budget_microframes = sch_ep->num_budget_microframes;
 302 +
 303 +       /*
 304 +        * Search through all possible schedule microframes.
 305 +        * and find a microframe where its worst bandwidth is minimum.
 306 +        */
 307 +       min_bw = ~0;
 308 +       min_index = 0;
 309 +       for (offset = 0; offset < esit; offset++) {
 310 +               if ((offset + num_budget_microframes) > sch_ep->esit)
 311 +                       break;
 312 +
 313 +               /*
 314 +                * usb_20 spec section11.18:
 315 +                * must never schedule Start-Split in Y6
 316 +                */
 317 +               if (is_fs_or_ls(udev->speed) && (offset % 8 == 6))
 318 +                       continue;
 319 +
 320 +               worst_bw = get_max_bw(sch_bw, sch_ep, offset);
 321 +               if (min_bw > worst_bw) {
 322 +                       min_bw = worst_bw;
 323 +                       min_index = offset;
 324 +               }
 325 +               if (min_bw == 0)
 326 +                       break;
 327 +       }
 328 +       sch_ep->offset = min_index;
 329 +
 330 +       bw_boundary = (udev->speed == USB_SPEED_SUPER)
 331 +                               ? SS_BW_BOUNDARY : HS_BW_BOUNDARY;
 332 +
 333 +       /* check bandwidth */
 334 +       if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary)
 335 +               return -ERANGE;
 336 +
 337 +       /* update bus bandwidth info */
 338 +       update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe);
 339 +
 340 +       return 0;
 341 +}
 342 +
 343 +static bool need_bw_sch(struct usb_host_endpoint *ep,
 344 +       enum usb_device_speed speed, int has_tt)
 345 +{
 346 +       /* only for periodic endpoints */
 347 +       if (usb_endpoint_xfer_control(&ep->desc)
 348 +               || usb_endpoint_xfer_bulk(&ep->desc))
 349 +               return false;
 350 +
 351 +       /*
 352 +        * for LS & FS periodic endpoints which its device don't attach
 353 +        * to TT are also ignored, root-hub will schedule them directly
 354 +        */
 355 +       if (is_fs_or_ls(speed) && !has_tt)
 356 +               return false;
 357 +
 358 +       return true;
 359 +}
 360 +
 361 +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk)
 362 +{
 363 +       struct mu3h_sch_bw_info *sch_array;
 364 +       int num_usb_bus;
 365 +       int i;
 366 +
 367 +       /* ss IN and OUT are separated */
 368 +       num_usb_bus = mtk->num_u3_ports * 2 + mtk->num_u2_ports;
 369 +
 370 +       sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
 371 +       if (sch_array == NULL)
 372 +               return -ENOMEM;
 373 +
 374 +       for (i = 0; i < num_usb_bus; i++)
 375 +               INIT_LIST_HEAD(&sch_array[i].bw_ep_list);
 376 +
 377 +       mtk->sch_array = sch_array;
 378 +
 379 +       return 0;
 380 +}
 381 +EXPORT_SYMBOL_GPL(xhci_mtk_sch_init);
 382 +
 383 +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk)
 384 +{
 385 +       kfree(mtk->sch_array);
 386 +}
 387 +EXPORT_SYMBOL_GPL(xhci_mtk_sch_exit);
 388 +
 389 +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 390 +               struct usb_host_endpoint *ep)
 391 +{
 392 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 393 +       struct xhci_hcd *xhci;
 394 +       struct xhci_ep_ctx *ep_ctx;
 395 +       struct xhci_slot_ctx *slot_ctx;
 396 +       struct xhci_virt_device *virt_dev;
 397 +       struct mu3h_sch_bw_info *sch_bw;
 398 +       struct mu3h_sch_ep_info *sch_ep;
 399 +       struct mu3h_sch_bw_info *sch_array;
 400 +       unsigned int ep_index;
 401 +       int bw_index;
 402 +       int ret = 0;
 403 +
 404 +       xhci = hcd_to_xhci(hcd);
 405 +       virt_dev = xhci->devs[udev->slot_id];
 406 +       ep_index = xhci_get_endpoint_index(&ep->desc);
 407 +       slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
 408 +       ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
 409 +       sch_array = mtk->sch_array;
 410 +
 411 +       xhci_dbg(xhci, "%s() type:%d, speed:%d, mpkt:%d, dir:%d, ep:%p\n",
 412 +               __func__, usb_endpoint_type(&ep->desc), udev->speed,
 413 +               GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
 414 +               usb_endpoint_dir_in(&ep->desc), ep);
 415 +
 416 +       if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
 417 +               return 0;
 418 +
 419 +       bw_index = get_bw_index(xhci, udev, ep);
 420 +       sch_bw = &sch_array[bw_index];
 421 +
 422 +       sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_NOIO);
 423 +       if (!sch_ep)
 424 +               return -ENOMEM;
 425 +
 426 +       setup_sch_info(udev, ep_ctx, sch_ep);
 427 +
 428 +       ret = check_sch_bw(udev, sch_bw, sch_ep);
 429 +       if (ret) {
 430 +               xhci_err(xhci, "Not enough bandwidth!\n");
 431 +               kfree(sch_ep);
 432 +               return -ENOSPC;
 433 +       }
 434 +
 435 +       list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
 436 +       sch_ep->ep = ep;
 437 +
 438 +       ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
 439 +               | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
 440 +       ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
 441 +               | EP_BREPEAT(sch_ep->repeat));
 442 +
 443 +       xhci_dbg(xhci, " PKTS:%x, CSCOUNT:%x, BM:%x, OFFSET:%x, REPEAT:%x\n",
 444 +                       sch_ep->pkts, sch_ep->cs_count, sch_ep->burst_mode,
 445 +                       sch_ep->offset, sch_ep->repeat);
 446 +
 447 +       return 0;
 448 +}
 449 +EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
 450 +
 451 +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 452 +               struct usb_host_endpoint *ep)
 453 +{
 454 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 455 +       struct xhci_hcd *xhci;
 456 +       struct xhci_slot_ctx *slot_ctx;
 457 +       struct xhci_virt_device *virt_dev;
 458 +       struct mu3h_sch_bw_info *sch_array;
 459 +       struct mu3h_sch_bw_info *sch_bw;
 460 +       struct mu3h_sch_ep_info *sch_ep;
 461 +       int bw_index;
 462 +
 463 +       xhci = hcd_to_xhci(hcd);
 464 +       virt_dev = xhci->devs[udev->slot_id];
 465 +       slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
 466 +       sch_array = mtk->sch_array;
 467 +
 468 +       xhci_dbg(xhci, "%s() type:%d, speed:%d, mpks:%d, dir:%d, ep:%p\n",
 469 +               __func__, usb_endpoint_type(&ep->desc), udev->speed,
 470 +               GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
 471 +               usb_endpoint_dir_in(&ep->desc), ep);
 472 +
 473 +       if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
 474 +               return;
 475 +
 476 +       bw_index = get_bw_index(xhci, udev, ep);
 477 +       sch_bw = &sch_array[bw_index];
 478 +
 479 +       list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
 480 +               if (sch_ep->ep == ep) {
 481 +                       update_bus_bw(sch_bw, sch_ep,
 482 +                               -sch_ep->bw_cost_per_microframe);
 483 +                       list_del(&sch_ep->endpoint);
 484 +                       kfree(sch_ep);
 485 +                       break;
 486 +               }
 487 +       }
 488 +}
 489 +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
 490 --- /dev/null
 491 +++ b/drivers/usb/host/xhci-mtk.c
 492 @@ -0,0 +1,763 @@
 493 +/*
 494 + * MediaTek xHCI Host Controller Driver
 495 + *
 496 + * Copyright (c) 2015 MediaTek Inc.
 497 + * Author:
 498 + *  Chunfeng Yun <chunfeng.yun@mediatek.com>
 499 + *
 500 + * This software is licensed under the terms of the GNU General Public
 501 + * License version 2, as published by the Free Software Foundation, and
 502 + * may be copied, distributed, and modified under those terms.
 503 + *
 504 + * This program is distributed in the hope that it will be useful,
 505 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 506 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 507 + * GNU General Public License for more details.
 508 + *
 509 + */
 510 +
 511 +#include <linux/clk.h>
 512 +#include <linux/dma-mapping.h>
 513 +#include <linux/iopoll.h>
 514 +#include <linux/kernel.h>
 515 +#include <linux/mfd/syscon.h>
 516 +#include <linux/module.h>
 517 +#include <linux/of.h>
 518 +#include <linux/phy/phy.h>
 519 +#include <linux/platform_device.h>
 520 +#include <linux/pm_runtime.h>
 521 +#include <linux/regmap.h>
 522 +#include <linux/regulator/consumer.h>
 523 +
 524 +#include "xhci.h"
 525 +#include "xhci-mtk.h"
 526 +
 527 +/* ip_pw_ctrl0 register */
 528 +#define CTRL0_IP_SW_RST        BIT(0)
 529 +
 530 +/* ip_pw_ctrl1 register */
 531 +#define CTRL1_IP_HOST_PDN      BIT(0)
 532 +
 533 +/* ip_pw_ctrl2 register */
 534 +#define CTRL2_IP_DEV_PDN       BIT(0)
 535 +
 536 +/* ip_pw_sts1 register */
 537 +#define STS1_IP_SLEEP_STS      BIT(30)
 538 +#define STS1_XHCI_RST          BIT(11)
 539 +#define STS1_SYS125_RST        BIT(10)
 540 +#define STS1_REF_RST           BIT(8)
 541 +#define STS1_SYSPLL_STABLE     BIT(0)
 542 +
 543 +/* ip_xhci_cap register */
 544 +#define CAP_U3_PORT_NUM(p)     ((p) & 0xff)
 545 +#define CAP_U2_PORT_NUM(p)     (((p) >> 8) & 0xff)
 546 +
 547 +/* u3_ctrl_p register */
 548 +#define CTRL_U3_PORT_HOST_SEL  BIT(2)
 549 +#define CTRL_U3_PORT_PDN       BIT(1)
 550 +#define CTRL_U3_PORT_DIS       BIT(0)
 551 +
 552 +/* u2_ctrl_p register */
 553 +#define CTRL_U2_PORT_HOST_SEL  BIT(2)
 554 +#define CTRL_U2_PORT_PDN       BIT(1)
 555 +#define CTRL_U2_PORT_DIS       BIT(0)
 556 +
 557 +/* u2_phy_pll register */
 558 +#define CTRL_U2_FORCE_PLL_STB  BIT(28)
 559 +
 560 +#define PERI_WK_CTRL0          0x400
 561 +#define UWK_CTR0_0P_LS_PE      BIT(8)  /* posedge */
 562 +#define UWK_CTR0_0P_LS_NE      BIT(7)  /* negedge for 0p linestate*/
 563 +#define UWK_CTL1_1P_LS_C(x)    (((x) & 0xf) << 1)
 564 +#define UWK_CTL1_1P_LS_E       BIT(0)
 565 +
 566 +#define PERI_WK_CTRL1          0x404
 567 +#define UWK_CTL1_IS_C(x)       (((x) & 0xf) << 26)
 568 +#define UWK_CTL1_IS_E          BIT(25)
 569 +#define UWK_CTL1_0P_LS_C(x)    (((x) & 0xf) << 21)
 570 +#define UWK_CTL1_0P_LS_E       BIT(20)
 571 +#define UWK_CTL1_IDDIG_C(x)    (((x) & 0xf) << 11)  /* cycle debounce */
 572 +#define UWK_CTL1_IDDIG_E       BIT(10) /* enable debounce */
 573 +#define UWK_CTL1_IDDIG_P       BIT(9)  /* polarity */
 574 +#define UWK_CTL1_0P_LS_P       BIT(7)
 575 +#define UWK_CTL1_IS_P          BIT(6)  /* polarity for ip sleep */
 576 +
 577 +enum ssusb_wakeup_src {
 578 +       SSUSB_WK_IP_SLEEP = 1,
 579 +       SSUSB_WK_LINE_STATE = 2,
 580 +};
 581 +
 582 +static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
 583 +{
 584 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 585 +       u32 value, check_val;
 586 +       int ret;
 587 +       int i;
 588 +
 589 +       /* power on host ip */
 590 +       value = readl(&ippc->ip_pw_ctr1);
 591 +       value &= ~CTRL1_IP_HOST_PDN;
 592 +       writel(value, &ippc->ip_pw_ctr1);
 593 +
 594 +       /* power on and enable all u3 ports */
 595 +       for (i = 0; i < mtk->num_u3_ports; i++) {
 596 +               value = readl(&ippc->u3_ctrl_p[i]);
 597 +               value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
 598 +               value |= CTRL_U3_PORT_HOST_SEL;
 599 +               writel(value, &ippc->u3_ctrl_p[i]);
 600 +       }
 601 +
 602 +       /* power on and enable all u2 ports */
 603 +       for (i = 0; i < mtk->num_u2_ports; i++) {
 604 +               value = readl(&ippc->u2_ctrl_p[i]);
 605 +               value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
 606 +               value |= CTRL_U2_PORT_HOST_SEL;
 607 +               writel(value, &ippc->u2_ctrl_p[i]);
 608 +       }
 609 +
 610 +       /*
 611 +        * wait for clocks to be stable, and clock domains reset to
 612 +        * be inactive after power on and enable ports
 613 +        */
 614 +       check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
 615 +                       STS1_SYS125_RST | STS1_XHCI_RST;
 616 +
 617 +       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 618 +                         (check_val == (value & check_val)), 100, 20000);
 619 +       if (ret) {
 620 +               dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
 621 +               return ret;
 622 +       }
 623 +
 624 +       return 0;
 625 +}
 626 +
 627 +static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
 628 +{
 629 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 630 +       u32 value;
 631 +       int ret;
 632 +       int i;
 633 +
 634 +       /* power down all u3 ports */
 635 +       for (i = 0; i < mtk->num_u3_ports; i++) {
 636 +               value = readl(&ippc->u3_ctrl_p[i]);
 637 +               value |= CTRL_U3_PORT_PDN;
 638 +               writel(value, &ippc->u3_ctrl_p[i]);
 639 +       }
 640 +
 641 +       /* power down all u2 ports */
 642 +       for (i = 0; i < mtk->num_u2_ports; i++) {
 643 +               value = readl(&ippc->u2_ctrl_p[i]);
 644 +               value |= CTRL_U2_PORT_PDN;
 645 +               writel(value, &ippc->u2_ctrl_p[i]);
 646 +       }
 647 +
 648 +       /* power down host ip */
 649 +       value = readl(&ippc->ip_pw_ctr1);
 650 +       value |= CTRL1_IP_HOST_PDN;
 651 +       writel(value, &ippc->ip_pw_ctr1);
 652 +
 653 +       /* wait for host ip to sleep */
 654 +       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 655 +                         (value & STS1_IP_SLEEP_STS), 100, 100000);
 656 +       if (ret) {
 657 +               dev_err(mtk->dev, "ip sleep failed!!!\n");
 658 +               return ret;
 659 +       }
 660 +       return 0;
 661 +}
 662 +
 663 +static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
 664 +{
 665 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 666 +       u32 value;
 667 +
 668 +       /* reset whole ip */
 669 +       value = readl(&ippc->ip_pw_ctr0);
 670 +       value |= CTRL0_IP_SW_RST;
 671 +       writel(value, &ippc->ip_pw_ctr0);
 672 +       udelay(1);
 673 +       value = readl(&ippc->ip_pw_ctr0);
 674 +       value &= ~CTRL0_IP_SW_RST;
 675 +       writel(value, &ippc->ip_pw_ctr0);
 676 +
 677 +       /*
 678 +        * device ip is default power-on in fact
 679 +        * power down device ip, otherwise ip-sleep will fail
 680 +        */
 681 +       value = readl(&ippc->ip_pw_ctr2);
 682 +       value |= CTRL2_IP_DEV_PDN;
 683 +       writel(value, &ippc->ip_pw_ctr2);
 684 +
 685 +       value = readl(&ippc->ip_xhci_cap);
 686 +       mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
 687 +       mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
 688 +       dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
 689 +                       mtk->num_u2_ports, mtk->num_u3_ports);
 690 +
 691 +       return xhci_mtk_host_enable(mtk);
 692 +}
 693 +
 694 +static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
 695 +{
 696 +       int ret;
 697 +
 698 +       ret = clk_prepare_enable(mtk->sys_clk);
 699 +       if (ret) {
 700 +               dev_err(mtk->dev, "failed to enable sys_clk\n");
 701 +               goto sys_clk_err;
 702 +       }
 703 +
 704 +       if (mtk->wakeup_src) {
 705 +               ret = clk_prepare_enable(mtk->wk_deb_p0);
 706 +               if (ret) {
 707 +                       dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
 708 +                       goto usb_p0_err;
 709 +               }
 710 +
 711 +               ret = clk_prepare_enable(mtk->wk_deb_p1);
 712 +               if (ret) {
 713 +                       dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
 714 +                       goto usb_p1_err;
 715 +               }
 716 +       }
 717 +       return 0;
 718 +
 719 +usb_p1_err:
 720 +       clk_disable_unprepare(mtk->wk_deb_p0);
 721 +usb_p0_err:
 722 +       clk_disable_unprepare(mtk->sys_clk);
 723 +sys_clk_err:
 724 +       return -EINVAL;
 725 +}
 726 +
 727 +static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
 728 +{
 729 +       if (mtk->wakeup_src) {
 730 +               clk_disable_unprepare(mtk->wk_deb_p1);
 731 +               clk_disable_unprepare(mtk->wk_deb_p0);
 732 +       }
 733 +       clk_disable_unprepare(mtk->sys_clk);
 734 +}
 735 +
 736 +/* only clocks can be turn off for ip-sleep wakeup mode */
 737 +static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
 738 +{
 739 +       u32 tmp;
 740 +       struct regmap *pericfg = mtk->pericfg;
 741 +
 742 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 743 +       tmp &= ~UWK_CTL1_IS_P;
 744 +       tmp &= ~(UWK_CTL1_IS_C(0xf));
 745 +       tmp |= UWK_CTL1_IS_C(0x8);
 746 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 747 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
 748 +
 749 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 750 +       dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
 751 +               __func__, tmp);
 752 +}
 753 +
 754 +static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
 755 +{
 756 +       u32 tmp;
 757 +
 758 +       regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
 759 +       tmp &= ~UWK_CTL1_IS_E;
 760 +       regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
 761 +}
 762 +
 763 +/*
 764 +* for line-state wakeup mode, phy's power should not power-down
 765 +* and only support cable plug in/out
 766 +*/
 767 +static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
 768 +{
 769 +       u32 tmp;
 770 +       struct regmap *pericfg = mtk->pericfg;
 771 +
 772 +       /* line-state of u2-port0 */
 773 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 774 +       tmp &= ~UWK_CTL1_0P_LS_P;
 775 +       tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
 776 +       tmp |= UWK_CTL1_0P_LS_C(0x8);
 777 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 778 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 779 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
 780 +
 781 +       /* line-state of u2-port1 */
 782 +       regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 783 +       tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
 784 +       tmp |= UWK_CTL1_1P_LS_C(0x8);
 785 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 786 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
 787 +}
 788 +
 789 +static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
 790 +{
 791 +       u32 tmp;
 792 +       struct regmap *pericfg = mtk->pericfg;
 793 +
 794 +       /* line-state of u2-port0 */
 795 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 796 +       tmp &= ~UWK_CTL1_0P_LS_E;
 797 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 798 +
 799 +       /* line-state of u2-port1 */
 800 +       regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 801 +       tmp &= ~UWK_CTL1_1P_LS_E;
 802 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 803 +}
 804 +
 805 +static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
 806 +{
 807 +       if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 808 +               usb_wakeup_ip_sleep_en(mtk);
 809 +       else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 810 +               usb_wakeup_line_state_en(mtk);
 811 +}
 812 +
 813 +static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
 814 +{
 815 +       if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 816 +               usb_wakeup_ip_sleep_dis(mtk);
 817 +       else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 818 +               usb_wakeup_line_state_dis(mtk);
 819 +}
 820 +
 821 +static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
 822 +                               struct device_node *dn)
 823 +{
 824 +       struct device *dev = mtk->dev;
 825 +
 826 +       /*
 827 +       * wakeup function is optional, so it is not an error if this property
 828 +       * does not exist, and in such case, no need to get relative
 829 +       * properties anymore.
 830 +       */
 831 +       of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
 832 +       if (!mtk->wakeup_src)
 833 +               return 0;
 834 +
 835 +       mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
 836 +       if (IS_ERR(mtk->wk_deb_p0)) {
 837 +               dev_err(dev, "fail to get wakeup_deb_p0\n");
 838 +               return PTR_ERR(mtk->wk_deb_p0);
 839 +       }
 840 +
 841 +       mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
 842 +       if (IS_ERR(mtk->wk_deb_p1)) {
 843 +               dev_err(dev, "fail to get wakeup_deb_p1\n");
 844 +               return PTR_ERR(mtk->wk_deb_p1);
 845 +       }
 846 +
 847 +       mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
 848 +                                               "mediatek,syscon-wakeup");
 849 +       if (IS_ERR(mtk->pericfg)) {
 850 +               dev_err(dev, "fail to get pericfg regs\n");
 851 +               return PTR_ERR(mtk->pericfg);
 852 +       }
 853 +
 854 +       return 0;
 855 +}
 856 +
 857 +static int xhci_mtk_setup(struct usb_hcd *hcd);
 858 +static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
 859 +       .extra_priv_size = sizeof(struct xhci_hcd),
 860 +       .reset = xhci_mtk_setup,
 861 +};
 862 +
 863 +static struct hc_driver __read_mostly xhci_mtk_hc_driver;
 864 +
 865 +static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
 866 +{
 867 +       int i;
 868 +       int ret;
 869 +
 870 +       for (i = 0; i < mtk->num_phys; i++) {
 871 +               ret = phy_init(mtk->phys[i]);
 872 +               if (ret)
 873 +                       goto exit_phy;
 874 +       }
 875 +       return 0;
 876 +
 877 +exit_phy:
 878 +       for (; i > 0; i--)
 879 +               phy_exit(mtk->phys[i - 1]);
 880 +
 881 +       return ret;
 882 +}
 883 +
 884 +static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
 885 +{
 886 +       int i;
 887 +
 888 +       for (i = 0; i < mtk->num_phys; i++)
 889 +               phy_exit(mtk->phys[i]);
 890 +
 891 +       return 0;
 892 +}
 893 +
 894 +static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
 895 +{
 896 +       int i;
 897 +       int ret;
 898 +
 899 +       for (i = 0; i < mtk->num_phys; i++) {
 900 +               ret = phy_power_on(mtk->phys[i]);
 901 +               if (ret)
 902 +                       goto power_off_phy;
 903 +       }
 904 +       return 0;
 905 +
 906 +power_off_phy:
 907 +       for (; i > 0; i--)
 908 +               phy_power_off(mtk->phys[i - 1]);
 909 +
 910 +       return ret;
 911 +}
 912 +
 913 +static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
 914 +{
 915 +       unsigned int i;
 916 +
 917 +       for (i = 0; i < mtk->num_phys; i++)
 918 +               phy_power_off(mtk->phys[i]);
 919 +}
 920 +
 921 +static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
 922 +{
 923 +       int ret;
 924 +
 925 +       ret = regulator_enable(mtk->vbus);
 926 +       if (ret) {
 927 +               dev_err(mtk->dev, "failed to enable vbus\n");
 928 +               return ret;
 929 +       }
 930 +
 931 +       ret = regulator_enable(mtk->vusb33);
 932 +       if (ret) {
 933 +               dev_err(mtk->dev, "failed to enable vusb33\n");
 934 +               regulator_disable(mtk->vbus);
 935 +               return ret;
 936 +       }
 937 +       return 0;
 938 +}
 939 +
 940 +static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
 941 +{
 942 +       regulator_disable(mtk->vbus);
 943 +       regulator_disable(mtk->vusb33);
 944 +}
 945 +
 946 +static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
 947 +{
 948 +       struct usb_hcd *hcd = xhci_to_hcd(xhci);
 949 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 950 +
 951 +       /*
 952 +        * As of now platform drivers don't provide MSI support so we ensure
 953 +        * here that the generic code does not try to make a pci_dev from our
 954 +        * dev struct in order to setup MSI
 955 +        */
 956 +       xhci->quirks |= XHCI_PLAT;
 957 +       xhci->quirks |= XHCI_MTK_HOST;
 958 +       /*
 959 +        * MTK host controller gives a spurious successful event after a
 960 +        * short transfer. Ignore it.
 961 +        */
 962 +       xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 963 +       if (mtk->lpm_support)
 964 +               xhci->quirks |= XHCI_LPM_SUPPORT;
 965 +}
 966 +
 967 +/* called during probe() after chip reset completes */
 968 +static int xhci_mtk_setup(struct usb_hcd *hcd)
 969 +{
 970 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 971 +       int ret;
 972 +
 973 +       if (usb_hcd_is_primary_hcd(hcd)) {
 974 +               ret = xhci_mtk_ssusb_config(mtk);
 975 +               if (ret)
 976 +                       return ret;
 977 +               ret = xhci_mtk_sch_init(mtk);
 978 +               if (ret)
 979 +                       return ret;
 980 +       }
 981 +
 982 +       return xhci_gen_setup(hcd, xhci_mtk_quirks);
 983 +}
 984 +
 985 +static int xhci_mtk_probe(struct platform_device *pdev)
 986 +{
 987 +       struct device *dev = &pdev->dev;
 988 +       struct device_node *node = dev->of_node;
 989 +       struct xhci_hcd_mtk *mtk;
 990 +       const struct hc_driver *driver;
 991 +       struct xhci_hcd *xhci;
 992 +       struct resource *res;
 993 +       struct usb_hcd *hcd;
 994 +       struct phy *phy;
 995 +       int phy_num;
 996 +       int ret = -ENODEV;
 997 +       int irq;
 998 +
 999 +       if (usb_disabled())
1000 +               return -ENODEV;
1001 +
1002 +       driver = &xhci_mtk_hc_driver;
1003 +       mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
1004 +       if (!mtk)
1005 +               return -ENOMEM;
1006 +
1007 +       mtk->dev = dev;
1008 +       mtk->vbus = devm_regulator_get(dev, "vbus");
1009 +       if (IS_ERR(mtk->vbus)) {
1010 +               dev_err(dev, "fail to get vbus\n");
1011 +               return PTR_ERR(mtk->vbus);
1012 +       }
1013 +
1014 +       mtk->vusb33 = devm_regulator_get(dev, "vusb33");
1015 +       if (IS_ERR(mtk->vusb33)) {
1016 +               dev_err(dev, "fail to get vusb33\n");
1017 +               return PTR_ERR(mtk->vusb33);
1018 +       }
1019 +
1020 +       mtk->sys_clk = devm_clk_get(dev, "sys_ck");
1021 +       if (IS_ERR(mtk->sys_clk)) {
1022 +               dev_err(dev, "fail to get sys_ck\n");
1023 +               return PTR_ERR(mtk->sys_clk);
1024 +       }
1025 +
1026 +       mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
1027 +
1028 +       ret = usb_wakeup_of_property_parse(mtk, node);
1029 +       if (ret)
1030 +               return ret;
1031 +
1032 +       mtk->num_phys = of_count_phandle_with_args(node,
1033 +                       "phys", "#phy-cells");
1034 +       if (mtk->num_phys > 0) {
1035 +               mtk->phys = devm_kcalloc(dev, mtk->num_phys,
1036 +                                       sizeof(*mtk->phys), GFP_KERNEL);
1037 +               if (!mtk->phys)
1038 +                       return -ENOMEM;
1039 +       } else {
1040 +               mtk->num_phys = 0;
1041 +       }
1042 +       pm_runtime_enable(dev);
1043 +       pm_runtime_get_sync(dev);
1044 +       device_enable_async_suspend(dev);
1045 +
1046 +       ret = xhci_mtk_ldos_enable(mtk);
1047 +       if (ret)
1048 +               goto disable_pm;
1049 +
1050 +       ret = xhci_mtk_clks_enable(mtk);
1051 +       if (ret)
1052 +               goto disable_ldos;
1053 +
1054 +       irq = platform_get_irq(pdev, 0);
1055 +       if (irq < 0)
1056 +               goto disable_clk;
1057 +
1058 +       /* Initialize dma_mask and coherent_dma_mask to 32-bits */
1059 +       ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
1060 +       if (ret)
1061 +               goto disable_clk;
1062 +
1063 +       if (!dev->dma_mask)
1064 +               dev->dma_mask = &dev->coherent_dma_mask;
1065 +       else
1066 +               dma_set_mask(dev, DMA_BIT_MASK(32));
1067 +
1068 +       hcd = usb_create_hcd(driver, dev, dev_name(dev));
1069 +       if (!hcd) {
1070 +               ret = -ENOMEM;
1071 +               goto disable_clk;
1072 +       }
1073 +
1074 +       /*
1075 +        * USB 2.0 roothub is stored in the platform_device.
1076 +        * Swap it with mtk HCD.
1077 +        */
1078 +       mtk->hcd = platform_get_drvdata(pdev);
1079 +       platform_set_drvdata(pdev, mtk);
1080 +
1081 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 +       hcd->regs = devm_ioremap_resource(dev, res);
1083 +       if (IS_ERR(hcd->regs)) {
1084 +               ret = PTR_ERR(hcd->regs);
1085 +               goto put_usb2_hcd;
1086 +       }
1087 +       hcd->rsrc_start = res->start;
1088 +       hcd->rsrc_len = resource_size(res);
1089 +
1090 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1091 +       mtk->ippc_regs = devm_ioremap_resource(dev, res);
1092 +       if (IS_ERR(mtk->ippc_regs)) {
1093 +               ret = PTR_ERR(mtk->ippc_regs);
1094 +               goto put_usb2_hcd;
1095 +       }
1096 +
1097 +       for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
1098 +               phy = devm_of_phy_get_by_index(dev, node, phy_num);
1099 +               if (IS_ERR(phy)) {
1100 +                       ret = PTR_ERR(phy);
1101 +                       goto put_usb2_hcd;
1102 +               }
1103 +               mtk->phys[phy_num] = phy;
1104 +       }
1105 +
1106 +       ret = xhci_mtk_phy_init(mtk);
1107 +       if (ret)
1108 +               goto put_usb2_hcd;
1109 +
1110 +       ret = xhci_mtk_phy_power_on(mtk);
1111 +       if (ret)
1112 +               goto exit_phys;
1113 +
1114 +       device_init_wakeup(dev, true);
1115 +
1116 +       xhci = hcd_to_xhci(hcd);
1117 +       xhci->main_hcd = hcd;
1118 +       xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
1119 +                       dev_name(dev), hcd);
1120 +       if (!xhci->shared_hcd) {
1121 +               ret = -ENOMEM;
1122 +               goto power_off_phys;
1123 +       }
1124 +
1125 +       if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
1126 +               xhci->shared_hcd->can_do_streams = 1;
1127 +
1128 +       ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
1129 +       if (ret)
1130 +               goto put_usb3_hcd;
1131 +
1132 +       ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
1133 +       if (ret)
1134 +               goto dealloc_usb2_hcd;
1135 +
1136 +       return 0;
1137 +
1138 +dealloc_usb2_hcd:
1139 +       usb_remove_hcd(hcd);
1140 +
1141 +put_usb3_hcd:
1142 +       xhci_mtk_sch_exit(mtk);
1143 +       usb_put_hcd(xhci->shared_hcd);
1144 +
1145 +power_off_phys:
1146 +       xhci_mtk_phy_power_off(mtk);
1147 +       device_init_wakeup(dev, false);
1148 +
1149 +exit_phys:
1150 +       xhci_mtk_phy_exit(mtk);
1151 +
1152 +put_usb2_hcd:
1153 +       usb_put_hcd(hcd);
1154 +
1155 +disable_clk:
1156 +       xhci_mtk_clks_disable(mtk);
1157 +
1158 +disable_ldos:
1159 +       xhci_mtk_ldos_disable(mtk);
1160 +
1161 +disable_pm:
1162 +       pm_runtime_put_sync(dev);
1163 +       pm_runtime_disable(dev);
1164 +       return ret;
1165 +}
1166 +
1167 +static int xhci_mtk_remove(struct platform_device *dev)
1168 +{
1169 +       struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
1170 +       struct usb_hcd  *hcd = mtk->hcd;
1171 +       struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1172 +
1173 +       usb_remove_hcd(xhci->shared_hcd);
1174 +       xhci_mtk_phy_power_off(mtk);
1175 +       xhci_mtk_phy_exit(mtk);
1176 +       device_init_wakeup(&dev->dev, false);
1177 +
1178 +       usb_remove_hcd(hcd);
1179 +       usb_put_hcd(xhci->shared_hcd);
1180 +       usb_put_hcd(hcd);
1181 +       xhci_mtk_sch_exit(mtk);
1182 +       xhci_mtk_clks_disable(mtk);
1183 +       xhci_mtk_ldos_disable(mtk);
1184 +       pm_runtime_put_sync(&dev->dev);
1185 +       pm_runtime_disable(&dev->dev);
1186 +
1187 +       return 0;
1188 +}
1189 +
1190 +#ifdef CONFIG_PM_SLEEP
1191 +static int xhci_mtk_suspend(struct device *dev)
1192 +{
1193 +       struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
1194 +
1195 +       xhci_mtk_host_disable(mtk);
1196 +       xhci_mtk_phy_power_off(mtk);
1197 +       xhci_mtk_clks_disable(mtk);
1198 +       usb_wakeup_enable(mtk);
1199 +       return 0;
1200 +}
1201 +
1202 +static int xhci_mtk_resume(struct device *dev)
1203 +{
1204 +       struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
1205 +
1206 +       usb_wakeup_disable(mtk);
1207 +       xhci_mtk_clks_enable(mtk);
1208 +       xhci_mtk_phy_power_on(mtk);
1209 +       xhci_mtk_host_enable(mtk);
1210 +       return 0;
1211 +}
1212 +
1213 +static const struct dev_pm_ops xhci_mtk_pm_ops = {
1214 +       SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
1215 +};
1216 +#define DEV_PM_OPS     (&xhci_mtk_pm_ops)
1217 +#else
1218 +#define DEV_PM_OPS     NULL
1219 +#endif /* CONFIG_PM */
1220 +
1221 +#ifdef CONFIG_OF
1222 +static const struct of_device_id mtk_xhci_of_match[] = {
1223 +       { .compatible = "mediatek,mt8173-xhci"},
1224 +       { },
1225 +};
1226 +MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
1227 +#endif
1228 +
1229 +static struct platform_driver mtk_xhci_driver = {
1230 +       .probe  = xhci_mtk_probe,
1231 +       .remove = xhci_mtk_remove,
1232 +       .driver = {
1233 +               .name = "xhci-mtk",
1234 +               .pm = DEV_PM_OPS,
1235 +               .of_match_table = of_match_ptr(mtk_xhci_of_match),
1236 +       },
1237 +};
1238 +MODULE_ALIAS("platform:xhci-mtk");
1239 +
1240 +static int __init xhci_mtk_init(void)
1241 +{
1242 +       xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
1243 +       return platform_driver_register(&mtk_xhci_driver);
1244 +}
1245 +module_init(xhci_mtk_init);
1246 +
1247 +static void __exit xhci_mtk_exit(void)
1248 +{
1249 +       platform_driver_unregister(&mtk_xhci_driver);
1250 +}
1251 +module_exit(xhci_mtk_exit);
1252 +
1253 +MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1254 +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
1255 +MODULE_LICENSE("GPL v2");
1256 --- /dev/null
1257 +++ b/drivers/usb/host/xhci-mtk.h
1258 @@ -0,0 +1,162 @@
1259 +/*
1260 + * Copyright (c) 2015 MediaTek Inc.
1261 + * Author:
1262 + *  Zhigang.Wei <zhigang.wei@mediatek.com>
1263 + *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
1264 + *
1265 + * This software is licensed under the terms of the GNU General Public
1266 + * License version 2, as published by the Free Software Foundation, and
1267 + * may be copied, distributed, and modified under those terms.
1268 + *
1269 + * This program is distributed in the hope that it will be useful,
1270 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1271 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1272 + * GNU General Public License for more details.
1273 + *
1274 + */
1275 +
1276 +#ifndef _XHCI_MTK_H_
1277 +#define _XHCI_MTK_H_
1278 +
1279 +#include "xhci.h"
1280 +
1281 +/**
1282 + * To simplify scheduler algorithm, set a upper limit for ESIT,
1283 + * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
1284 + * round down to the limit value, that means allocating more
1285 + * bandwidth to it.
1286 + */
1287 +#define XHCI_MTK_MAX_ESIT      64
1288 +
1289 +/**
1290 + * struct mu3h_sch_bw_info: schedule information for bandwidth domain
1291 + *
1292 + * @bus_bw: array to keep track of bandwidth already used at each uframes
1293 + * @bw_ep_list: eps in the bandwidth domain
1294 + *
1295 + * treat a HS root port as a bandwidth domain, but treat a SS root port as
1296 + * two bandwidth domains, one for IN eps and another for OUT eps.
1297 + */
1298 +struct mu3h_sch_bw_info {
1299 +       u32 bus_bw[XHCI_MTK_MAX_ESIT];
1300 +       struct list_head bw_ep_list;
1301 +};
1302 +
1303 +/**
1304 + * struct mu3h_sch_ep_info: schedule information for endpoint
1305 + *
1306 + * @esit: unit is 125us, equal to 2 << Interval field in ep-context
1307 + * @num_budget_microframes: number of continuous uframes
1308 + *             (@repeat==1) scheduled within the interval
1309 + * @bw_cost_per_microframe: bandwidth cost per microframe
1310 + * @endpoint: linked into bandwidth domain which it belongs to
1311 + * @ep: address of usb_host_endpoint struct
1312 + * @offset: which uframe of the interval that transfer should be
1313 + *             scheduled first time within the interval
1314 + * @repeat: the time gap between two uframes that transfers are
1315 + *             scheduled within a interval. in the simple algorithm, only
1316 + *             assign 0 or 1 to it; 0 means using only one uframe in a
1317 + *             interval, and 1 means using @num_budget_microframes
1318 + *             continuous uframes
1319 + * @pkts: number of packets to be transferred in the scheduled uframes
1320 + * @cs_count: number of CS that host will trigger
1321 + * @burst_mode: burst mode for scheduling. 0: normal burst mode,
1322 + *             distribute the bMaxBurst+1 packets for a single burst
1323 + *             according to @pkts and @repeat, repeate the burst multiple
1324 + *             times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
1325 + *             according to @pkts and @repeat. normal mode is used by
1326 + *             default
1327 + */
1328 +struct mu3h_sch_ep_info {
1329 +       u32 esit;
1330 +       u32 num_budget_microframes;
1331 +       u32 bw_cost_per_microframe;
1332 +       struct list_head endpoint;
1333 +       void *ep;
1334 +       /*
1335 +        * mtk xHCI scheduling information put into reserved DWs
1336 +        * in ep context
1337 +        */
1338 +       u32 offset;
1339 +       u32 repeat;
1340 +       u32 pkts;
1341 +       u32 cs_count;
1342 +       u32 burst_mode;
1343 +};
1344 +
1345 +#define MU3C_U3_PORT_MAX 4
1346 +#define MU3C_U2_PORT_MAX 5
1347 +
1348 +/**
1349 + * struct mu3c_ippc_regs: MTK ssusb ip port control registers
1350 + * @ip_pw_ctr0~3: ip power and clock control registers
1351 + * @ip_pw_sts1~2: ip power and clock status registers
1352 + * @ip_xhci_cap: ip xHCI capability register
1353 + * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
1354 + * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
1355 + * @u2_phy_pll: usb2 phy pll control register
1356 + */
1357 +struct mu3c_ippc_regs {
1358 +       __le32 ip_pw_ctr0;
1359 +       __le32 ip_pw_ctr1;
1360 +       __le32 ip_pw_ctr2;
1361 +       __le32 ip_pw_ctr3;
1362 +       __le32 ip_pw_sts1;
1363 +       __le32 ip_pw_sts2;
1364 +       __le32 reserved0[3];
1365 +       __le32 ip_xhci_cap;
1366 +       __le32 reserved1[2];
1367 +       __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
1368 +       __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
1369 +       __le32 reserved2;
1370 +       __le32 u2_phy_pll;
1371 +       __le32 reserved3[33]; /* 0x80 ~ 0xff */
1372 +};
1373 +
1374 +struct xhci_hcd_mtk {
1375 +       struct device *dev;
1376 +       struct usb_hcd *hcd;
1377 +       struct mu3h_sch_bw_info *sch_array;
1378 +       struct mu3c_ippc_regs __iomem *ippc_regs;
1379 +       int num_u2_ports;
1380 +       int num_u3_ports;
1381 +       struct regulator *vusb33;
1382 +       struct regulator *vbus;
1383 +       struct clk *sys_clk;    /* sys and mac clock */
1384 +       struct clk *wk_deb_p0;  /* port0's wakeup debounce clock */
1385 +       struct clk *wk_deb_p1;
1386 +       struct regmap *pericfg;
1387 +       struct phy **phys;
1388 +       int num_phys;
1389 +       int wakeup_src;
1390 +       bool lpm_support;
1391 +};
1392 +
1393 +static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
1394 +{
1395 +       return dev_get_drvdata(hcd->self.controller);
1396 +}
1397 +
1398 +#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
1399 +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
1400 +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
1401 +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
1402 +               struct usb_host_endpoint *ep);
1403 +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
1404 +               struct usb_host_endpoint *ep);
1405 +
1406 +#else
1407 +static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
1408 +       struct usb_device *udev, struct usb_host_endpoint *ep)
1409 +{
1410 +       return 0;
1411 +}
1412 +
1413 +static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
1414 +       struct usb_device *udev, struct usb_host_endpoint *ep)
1415 +{
1416 +}
1417 +
1418 +#endif
1419 +
1420 +#endif         /* _XHCI_MTK_H_ */
1421 --- a/drivers/usb/host/xhci-ring.c
1422 +++ b/drivers/usb/host/xhci-ring.c
1423 @@ -68,6 +68,7 @@
1424  #include <linux/slab.h>
1425  #include "xhci.h"
1426  #include "xhci-trace.h"
1427 +#include "xhci-mtk.h"
1428
1429  /*
1430   * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
1431 @@ -3065,17 +3066,22 @@ static u32 xhci_td_remainder(struct xhci
1432  {
1433         u32 maxp, total_packet_count;
1434
1435 -       if (xhci->hci_version < 0x100)
1436 +       /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */
1437 +       if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
1438                 return ((td_total_len - transferred) >> 10);
1439
1440 -       maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
1441 -       total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
1442 -
1443         /* One TRB with a zero-length data packet. */
1444         if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
1445             trb_buff_len == td_total_len)
1446                 return 0;
1447
1448 +       /* for MTK xHCI, TD size doesn't include this TRB */
1449 +       if (xhci->quirks & XHCI_MTK_HOST)
1450 +               trb_buff_len = 0;
1451 +
1452 +       maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
1453 +       total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
1454 +
1455         /* Queueing functions don't count the current TRB into transferred */
1456         return (total_packet_count - ((transferred + trb_buff_len) / maxp));
1457  }
1458 @@ -3463,7 +3469,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
1459                 field |= 0x1;
1460
1461         /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
1462 -       if (xhci->hci_version >= 0x100) {
1463 +       if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
1464                 if (urb->transfer_buffer_length > 0) {
1465                         if (setup->bRequestType & USB_DIR_IN)
1466                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
1467 --- a/drivers/usb/host/xhci.c
1468 +++ b/drivers/usb/host/xhci.c
1469 @@ -31,6 +31,7 @@
1470
1471  #include "xhci.h"
1472  #include "xhci-trace.h"
1473 +#include "xhci-mtk.h"
1474
1475  #define DRIVER_AUTHOR "Sarah Sharp"
1476  #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
1477 @@ -634,7 +635,11 @@ int xhci_run(struct usb_hcd *hcd)
1478                         "// Set the interrupt modulation register");
1479         temp = readl(&xhci->ir_set->irq_control);
1480         temp &= ~ER_IRQ_INTERVAL_MASK;
1481 -       temp |= (u32) 160;
1482 +       /*
1483 +        * the increment interval is 8 times as much as that defined
1484 +        * in xHCI spec on MTK's controller
1485 +        */
1486 +       temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
1487         writel(temp, &xhci->ir_set->irq_control);
1488
1489         /* Set the HCD state before we enable the irqs */
1490 @@ -1700,6 +1705,9 @@ int xhci_drop_endpoint(struct usb_hcd *h
1491
1492         xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1493
1494 +       if (xhci->quirks & XHCI_MTK_HOST)
1495 +               xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1496 +
1497         xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1498                         (unsigned int) ep->desc.bEndpointAddress,
1499                         udev->slot_id,
1500 @@ -1795,6 +1803,15 @@ int xhci_add_endpoint(struct usb_hcd *hc
1501                 return -ENOMEM;
1502         }
1503
1504 +       if (xhci->quirks & XHCI_MTK_HOST) {
1505 +               ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1506 +               if (ret < 0) {
1507 +                       xhci_free_or_cache_endpoint_ring(xhci,
1508 +                               virt_dev, ep_index);
1509 +                       return ret;
1510 +               }
1511 +       }
1512 +
1513         ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1514         new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1515
1516 --- a/drivers/usb/host/xhci.h
1517 +++ b/drivers/usb/host/xhci.h
1518 @@ -1630,6 +1630,7 @@ struct xhci_hcd {
1519  /* For controllers with a broken beyond repair streams implementation */
1520  #define XHCI_BROKEN_STREAMS    (1 << 19)
1521  #define XHCI_PME_STUCK_QUIRK   (1 << 20)
1522 +#define XHCI_MTK_HOST          (1 << 21)
1523         unsigned int            num_active_eps;
1524         unsigned int            limit_active_eps;
1525         /* There are two roothubs to keep track of bus suspend info for */