target/linux/mediatek/patches-4.4/0009-clk-mediatek-Add-MT2701-clock-support.patch

   1 From f2c07eaa2df52f9acac9ffc3457d3d81079dd723 Mon Sep 17 00:00:00 2001
   2 From: Shunli Wang <shunli.wang@mediatek.com>
   3 Date: Tue, 5 Jan 2016 14:30:20 +0800
   4 Subject: [PATCH 09/78] clk: mediatek: Add MT2701 clock support
   5
   6 Add MT2701 clock support, include topckgen, apmixedsys,
   7 infracfg, pericfg and subsystem clocks.
   8
   9 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  10 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  11 ---
  12  drivers/clk/mediatek/Kconfig      |    8 +
  13  drivers/clk/mediatek/Makefile     |    1 +
  14  drivers/clk/mediatek/clk-gate.c   |   56 ++
  15  drivers/clk/mediatek/clk-gate.h   |    2 +
  16  drivers/clk/mediatek/clk-mt2701.c | 1210 +++++++++++++++++++++++++++++++++++++
  17  drivers/clk/mediatek/clk-mtk.c    |   25 +
  18  drivers/clk/mediatek/clk-mtk.h    |   35 +-
  19  7 files changed, 1334 insertions(+), 3 deletions(-)
  20  create mode 100644 drivers/clk/mediatek/clk-mt2701.c
  21
  22 diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
  23 index dc224e6..6c7cdc0 100644
  24 --- a/drivers/clk/mediatek/Kconfig
  25 +++ b/drivers/clk/mediatek/Kconfig
  26 @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
  27         ---help---
  28           Mediatek SoCs' clock support.
  29
  30 +config COMMON_CLK_MT2701
  31 +       bool "Clock driver for Mediatek MT2701 and MT7623"
  32 +       depends on COMMON_CLK
  33 +       select COMMON_CLK_MEDIATEK
  34 +       default ARCH_MEDIATEK
  35 +       ---help---
  36 +         This driver supports Mediatek MT2701 and MT7623 clocks.
  37 +
  38  config COMMON_CLK_MT8135
  39         bool "Clock driver for Mediatek MT8135"
  40         depends on COMMON_CLK
  41 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
  42 index 32e7222..5b2b91b 100644
  43 --- a/drivers/clk/mediatek/Makefile
  44 +++ b/drivers/clk/mediatek/Makefile
  45 @@ -1,4 +1,5 @@
  46  obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
  47  obj-$(CONFIG_RESET_CONTROLLER) += reset.o
  48 +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
  49  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
  50  obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
  51 diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
  52 index 576bdb7..38badb4 100644
  53 --- a/drivers/clk/mediatek/clk-gate.c
  54 +++ b/drivers/clk/mediatek/clk-gate.c
  55 @@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
  56         regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
  57  }
  58
  59 +static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
  60 +{
  61 +       struct mtk_clk_gate *cg = to_clk_gate(hw);
  62 +       u32 val;
  63 +
  64 +       regmap_read(cg->regmap, cg->sta_ofs, &val);
  65 +       val |= BIT(cg->bit);
  66 +       regmap_write(cg->regmap, cg->sta_ofs, val);
  67 +}
  68 +
  69 +static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
  70 +{
  71 +       struct mtk_clk_gate *cg = to_clk_gate(hw);
  72 +       u32 val;
  73 +
  74 +       regmap_read(cg->regmap, cg->sta_ofs, &val);
  75 +       val &= ~(BIT(cg->bit));
  76 +       regmap_write(cg->regmap, cg->sta_ofs, val);
  77 +}
  78 +
  79  static int mtk_cg_enable(struct clk_hw *hw)
  80  {
  81         mtk_cg_clr_bit(hw);
  82 @@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
  83         mtk_cg_clr_bit(hw);
  84  }
  85
  86 +static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
  87 +{
  88 +       mtk_cg_clr_bit_no_setclr(hw);
  89 +
  90 +       return 0;
  91 +}
  92 +
  93 +static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
  94 +{
  95 +       mtk_cg_set_bit_no_setclr(hw);
  96 +}
  97 +
  98 +static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
  99 +{
 100 +       mtk_cg_set_bit_no_setclr(hw);
 101 +
 102 +       return 0;
 103 +}
 104 +
 105 +static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
 106 +{
 107 +       mtk_cg_clr_bit_no_setclr(hw);
 108 +}
 109 +
 110  const struct clk_ops mtk_clk_gate_ops_setclr = {
 111         .is_enabled     = mtk_cg_bit_is_cleared,
 112         .enable         = mtk_cg_enable,
 113 @@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
 114         .disable        = mtk_cg_disable_inv,
 115  };
 116
 117 +const struct clk_ops mtk_clk_gate_ops_no_setclr = {
 118 +       .is_enabled     = mtk_cg_bit_is_cleared,
 119 +       .enable         = mtk_cg_enable_no_setclr,
 120 +       .disable        = mtk_cg_disable_no_setclr,
 121 +};
 122 +
 123 +const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
 124 +       .is_enabled     = mtk_cg_bit_is_set,
 125 +       .enable         = mtk_cg_enable_inv_no_setclr,
 126 +       .disable        = mtk_cg_disable_inv_no_setclr,
 127 +};
 128 +
 129  struct clk * __init mtk_clk_register_gate(
 130                 const char *name,
 131                 const char *parent_name,
 132 diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
 133 index 11e25c9..7f7ef34 100644
 134 --- a/drivers/clk/mediatek/clk-gate.h
 135 +++ b/drivers/clk/mediatek/clk-gate.h
 136 @@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
 137
 138  extern const struct clk_ops mtk_clk_gate_ops_setclr;
 139  extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
 140 +extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
 141 +extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
 142
 143  struct clk *mtk_clk_register_gate(
 144                 const char *name,
 145 diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
 146 new file mode 100644
 147 index 0000000..2f521f4
 148 --- /dev/null
 149 +++ b/drivers/clk/mediatek/clk-mt2701.c
 150 @@ -0,0 +1,1210 @@
 151 +/*
 152 + * Copyright (c) 2014 MediaTek Inc.
 153 + * Author: Shunli Wang <shunli.wang@mediatek.com>
 154 + *
 155 + * This program is free software; you can redistribute it and/or modify
 156 + * it under the terms of the GNU General Public License version 2 as
 157 + * published by the Free Software Foundation.
 158 + *
 159 + * This program is distributed in the hope that it will be useful,
 160 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 161 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 162 + * GNU General Public License for more details.
 163 + */
 164 +
 165 +#include <linux/clk.h>
 166 +#include <linux/of.h>
 167 +#include <linux/of_address.h>
 168 +
 169 +#include "clk-mtk.h"
 170 +#include "clk-gate.h"
 171 +
 172 +#include <dt-bindings/clock/mt2701-clk.h>
 173 +
 174 +static DEFINE_SPINLOCK(lock);
 175 +
 176 +static const struct mtk_fixed_clk top_fixed_clks[] __initconst = {
 177 +       FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m", 108 * MHZ),
 178 +       FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m", 400 * MHZ),
 179 +       FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m", 295750000),
 180 +       FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m", 340 * MHZ),
 181 +       FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m", 340 * MHZ),
 182 +       FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m", 340 * MHZ),
 183 +       FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m", 300 * MHZ),
 184 +       FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m", 27 * MHZ),
 185 +       FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m", 416 * MHZ),
 186 +};
 187 +
 188 +static const struct mtk_fixed_factor top_fixed_divs[] __initconst = {
 189 +       FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
 190 +       FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
 191 +       FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
 192 +       FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
 193 +       FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
 194 +       FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
 195 +       FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
 196 +       FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
 197 +       FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
 198 +       FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
 199 +       FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
 200 +       FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
 201 +       FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
 202 +       FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
 203 +       FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
 204 +       FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
 205 +
 206 +       FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
 207 +       FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
 208 +       FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
 209 +       FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
 210 +       FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
 211 +       FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
 212 +       FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
 213 +       FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
 214 +       FACTOR(CLK_TOP_USB_PHY48M, "USB_PHY48M_CK", "univpll", 1, 26),
 215 +       FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
 216 +       FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
 217 +       FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
 218 +       FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
 219 +       FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
 220 +       FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
 221 +       FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
 222 +       FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
 223 +       FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
 224 +       FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
 225 +       FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
 226 +       FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
 227 +
 228 +       FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
 229 +       FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
 230 +       FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
 231 +       FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
 232 +
 233 +       FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
 234 +       FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
 235 +
 236 +       FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
 237 +       FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
 238 +       FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
 239 +
 240 +       FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
 241 +       FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
 242 +       FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
 243 +
 244 +       FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
 245 +       FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
 246 +       FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
 247 +
 248 +       FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
 249 +       FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
 250 +       FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
 251 +
 252 +       FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
 253 +       FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
 254 +       FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
 255 +
 256 +       FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
 257 +
 258 +       FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
 259 +       FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
 260 +       FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
 261 +       FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
 262 +       FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
 263 +
 264 +       FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
 265 +       FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
 266 +       FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
 267 +       FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
 268 +       FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
 269 +       FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
 270 +       FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
 271 +       FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
 272 +};
 273 +
 274 +static const char * const axi_parents[] __initconst = {
 275 +       "clk26m",
 276 +       "syspll1_d2",
 277 +       "syspll_d5",
 278 +       "syspll1_d4",
 279 +       "univpll_d5",
 280 +       "univpll2_d2",
 281 +       "mmpll_d2",
 282 +       "dmpll_d2"
 283 +};
 284 +
 285 +static const char * const mem_parents[] __initconst = {
 286 +       "clk26m",
 287 +       "dmpll_ck"
 288 +};
 289 +
 290 +static const char * const ddrphycfg_parents[] __initconst = {
 291 +       "clk26m",
 292 +       "syspll1_d8"
 293 +};
 294 +
 295 +static const char * const mm_parents[] __initconst = {
 296 +       "clk26m",
 297 +       "vencpll_ck",
 298 +       "syspll1_d2",
 299 +       "syspll1_d4",
 300 +       "univpll_d5",
 301 +       "univpll1_d2",
 302 +       "univpll2_d2",
 303 +       "dmpll_ck"
 304 +};
 305 +
 306 +static const char * const pwm_parents[] __initconst = {
 307 +       "clk26m",
 308 +       "univpll2_d4",
 309 +       "univpll3_d2",
 310 +       "univpll1_d4",
 311 +};
 312 +
 313 +static const char * const vdec_parents[] __initconst = {
 314 +       "clk26m",
 315 +       "vdecpll_ck",
 316 +       "syspll_d5",
 317 +       "syspll1_d4",
 318 +       "univpll_d5",
 319 +       "univpll2_d2",
 320 +       "vencpll_ck",
 321 +       "msdcpll_d2",
 322 +       "mmpll_d2"
 323 +};
 324 +
 325 +static const char * const mfg_parents[] __initconst = {
 326 +       "clk26m",
 327 +       "mmpll_ck",
 328 +       "dmpll_x2_ck",
 329 +       "msdcpll_ck",
 330 +       "clk26m",
 331 +       "syspll_d3",
 332 +       "univpll_d3",
 333 +       "univpll1_d2"
 334 +};
 335 +
 336 +static const char * const camtg_parents[] __initconst = {
 337 +       "clk26m",
 338 +       "univpll_d26",
 339 +       "univpll2_d2",
 340 +       "syspll3_d2",
 341 +       "syspll3_d4",
 342 +       "msdcpll_d2",
 343 +       "mmpll_d2"
 344 +};
 345 +
 346 +static const char * const uart_parents[] __initconst = {
 347 +       "clk26m",
 348 +       "univpll2_d8"
 349 +};
 350 +
 351 +static const char * const spi_parents[] __initconst = {
 352 +       "clk26m",
 353 +       "syspll3_d2",
 354 +       "syspll4_d2",
 355 +       "univpll2_d4",
 356 +       "univpll1_d8"
 357 +};
 358 +
 359 +static const char * const usb20_parents[] __initconst = {
 360 +       "clk26m",
 361 +       "univpll1_d8",
 362 +       "univpll3_d4"
 363 +};
 364 +
 365 +static const char * const msdc30_parents[] __initconst = {
 366 +       "clk26m",
 367 +       "msdcpll_d2",
 368 +       "syspll2_d2",
 369 +       "syspll1_d4",
 370 +       "univpll1_d4",
 371 +       "univpll2_d4"
 372 +};
 373 +
 374 +static const char * const audio_parents[] __initconst = {
 375 +       "clk26m",
 376 +       "syspll1_d16"
 377 +};
 378 +
 379 +static const char * const aud_intbus_parents[] __initconst = {
 380 +       "clk26m",
 381 +       "syspll1_d4",
 382 +       "syspll3_d2",
 383 +       "syspll4_d2",
 384 +       "univpll3_d2",
 385 +       "univpll2_d4"
 386 +};
 387 +
 388 +static const char * const pmicspi_parents[] __initconst = {
 389 +       "clk26m",
 390 +       "syspll1_d8",
 391 +       "syspll2_d4",
 392 +       "syspll4_d2",
 393 +       "syspll3_d4",
 394 +       "syspll2_d8",
 395 +       "syspll1_d16",
 396 +       "univpll3_d4",
 397 +       "univpll_d26",
 398 +       "dmpll_d2",
 399 +       "dmpll_d4"
 400 +};
 401 +
 402 +static const char * const scp_parents[] __initconst = {
 403 +       "clk26m",
 404 +       "syspll1_d8",
 405 +       "dmpll_d2",
 406 +       "dmpll_d4"
 407 +};
 408 +
 409 +static const char * const dpi0_parents[] __initconst = {
 410 +       "clk26m",
 411 +       "mipipll",
 412 +       "mipipll_d2",
 413 +       "mipipll_d4",
 414 +       "clk26m",
 415 +       "tvdpll_ck",
 416 +       "tvdpll_d2",
 417 +       "tvdpll_d4"
 418 +};
 419 +
 420 +static const char * const dpi1_parents[] __initconst = {
 421 +       "clk26m",
 422 +       "tvdpll_ck",
 423 +       "tvdpll_d2",
 424 +       "tvdpll_d4"
 425 +};
 426 +
 427 +static const char * const tve_parents[] __initconst = {
 428 +       "clk26m",
 429 +       "mipipll",
 430 +       "mipipll_d2",
 431 +       "mipipll_d4",
 432 +       "clk26m",
 433 +       "tvdpll_ck",
 434 +       "tvdpll_d2",
 435 +       "tvdpll_d4"
 436 +};
 437 +
 438 +static const char * const hdmi_parents[] __initconst = {
 439 +       "clk26m",
 440 +       "hdmipll_ck",
 441 +       "hdmipll_d2",
 442 +       "hdmipll_d3"
 443 +};
 444 +
 445 +static const char * const apll_parents[] __initconst = {
 446 +       "clk26m",
 447 +       "audpll",
 448 +       "audpll_d4",
 449 +       "audpll_d8",
 450 +       "audpll_d16",
 451 +       "audpll_d24",
 452 +       "clk26m",
 453 +       "clk26m"
 454 +};
 455 +
 456 +static const char * const rtc_parents[] __initconst = {
 457 +       "32k_internal",
 458 +       "32k_external",
 459 +       "clk26m",
 460 +       "univpll3_d8"
 461 +};
 462 +
 463 +static const char * const nfi2x_parents[] __initconst = {
 464 +       "clk26m",
 465 +       "syspll2_d2",
 466 +       "syspll_d7",
 467 +       "univpll3_d2",
 468 +       "syspll2_d4",
 469 +       "univpll3_d4",
 470 +       "syspll4_d4",
 471 +       "clk26m"
 472 +};
 473 +
 474 +static const char * const emmc_hclk_parents[] __initconst = {
 475 +       "clk26m",
 476 +       "syspll1_d2",
 477 +       "syspll1_d4",
 478 +       "syspll2_d2"
 479 +};
 480 +
 481 +static const char * const flash_parents[] __initconst = {
 482 +       "clk26m_d8",
 483 +       "clk26m",
 484 +       "syspll2_d8",
 485 +       "syspll3_d4",
 486 +       "univpll3_d4",
 487 +       "syspll4_d2",
 488 +       "syspll2_d4",
 489 +       "univpll2_d4"
 490 +};
 491 +
 492 +static const char * const di_parents[] __initconst = {
 493 +       "clk26m",
 494 +       "tvd2pll_ck",
 495 +       "tvd2pll_d2",
 496 +       "clk26m"
 497 +};
 498 +
 499 +static const char * const nr_osd_parents[] __initconst = {
 500 +       "clk26m",
 501 +       "vencpll_ck",
 502 +       "syspll1_d2",
 503 +       "syspll1_d4",
 504 +       "univpll_d5",
 505 +       "univpll1_d2",
 506 +       "univpll2_d2",
 507 +       "dmpll_ck"
 508 +};
 509 +
 510 +static const char * const hdmirx_bist_parents[] __initconst = {
 511 +       "clk26m",
 512 +       "syspll_d3",
 513 +       "clk26m",
 514 +       "syspll1_d16",
 515 +       "syspll4_d2",
 516 +       "syspll1_d4",
 517 +       "vencpll_ck",
 518 +       "clk26m"
 519 +};
 520 +
 521 +static const char * const intdir_parents[] __initconst = {
 522 +       "clk26m",
 523 +       "mmpll_ck",
 524 +       "syspll_d2",
 525 +       "univpll_d2"
 526 +};
 527 +
 528 +static const char * const asm_parents[] __initconst = {
 529 +       "clk26m",
 530 +       "univpll2_d4",
 531 +       "univpll2_d2",
 532 +       "syspll_d5"
 533 +};
 534 +
 535 +static const char * const ms_card_parents[] __initconst = {
 536 +       "clk26m",
 537 +       "univpll3_d8",
 538 +       "syspll4_d4"
 539 +};
 540 +
 541 +static const char * const ethif_parents[] __initconst = {
 542 +       "clk26m",
 543 +       "syspll1_d2",
 544 +       "syspll_d5",
 545 +       "syspll1_d4",
 546 +       "univpll_d5",
 547 +       "univpll1_d2",
 548 +       "dmpll_ck",
 549 +       "dmpll_d2"
 550 +};
 551 +
 552 +static const char * const hdmirx_parents[] __initconst = {
 553 +       "clk26m",
 554 +       "univpll_d52"
 555 +};
 556 +
 557 +static const char * const cmsys_parents[] __initconst = {
 558 +       "clk26m",
 559 +       "syspll1_d2",
 560 +       "univpll1_d2",
 561 +       "univpll_d5",
 562 +       "syspll_d5",
 563 +       "syspll2_d2",
 564 +       "syspll1_d4",
 565 +       "syspll3_d2",
 566 +       "syspll2_d4",
 567 +       "syspll1_d8",
 568 +       "clk26m",
 569 +       "clk26m",
 570 +       "clk26m",
 571 +       "clk26m",
 572 +       "clk26m"
 573 +};
 574 +
 575 +static const char * const clk_8bdac_parents[] __initconst = {
 576 +       "clkrtc_int",
 577 +       "8bdac_ck_pre",
 578 +       "clk26m",
 579 +       "clk26m"
 580 +};
 581 +
 582 +static const char * const aud2dvd_parents[] __initconst = {
 583 +       "a1sys_hp_ck",
 584 +       "a2sys_hp_ck"
 585 +};
 586 +
 587 +static const char * const padmclk_parents[] __initconst = {
 588 +       "clk26m",
 589 +       "univpll_d26",
 590 +       "univpll_d52",
 591 +       "univpll_d108",
 592 +       "univpll2_d8",
 593 +       "univpll2_d16",
 594 +       "univpll2_d32"
 595 +};
 596 +
 597 +static const char * const aud_mux_parents[] __initconst = {
 598 +       "clk26m",
 599 +       "aud1pll_98m_ck",
 600 +       "aud2pll_90m_ck",
 601 +       "hadds2pll_98m",
 602 +       "audio_ext1_ck",
 603 +       "audio_ext2_ck"
 604 +};
 605 +
 606 +static const char * const aud_src_parents[] __initconst = {
 607 +       "aud_mux1_sel",
 608 +       "aud_mux2_sel"
 609 +};
 610 +
 611 +static const char * const cpu_parents[] __initconst = {
 612 +       "clk26m",
 613 +       "armpll",
 614 +       "mainpll",
 615 +       "mmpll"
 616 +};
 617 +
 618 +static const struct mtk_composite top_muxes[] __initconst = {
 619 +       MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 620 +               0x0040, 0, 3, INVALID_MUX_GATE_BIT),
 621 +       MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1, 15),
 622 +       MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
 623 +       MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 3, 31),
 624 +
 625 +       MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
 626 +       MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
 627 +       MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23),
 628 +       MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0050, 24, 3, 31),
 629 +       MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7),
 630 +
 631 +       MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents, 0x0060, 8, 3, 15),
 632 +       MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 16, 2, 23),
 633 +       MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0060, 24, 3, 31),
 634 +
 635 +       MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0070, 0, 3, 7),
 636 +       MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0070, 8, 3, 15),
 637 +       MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents, 0x0070, 16, 1, 23),
 638 +       MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0070, 24, 3, 31),
 639 +
 640 +       MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0080, 0, 4, 7),
 641 +       MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15),
 642 +       MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23),
 643 +       MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31),
 644 +
 645 +       MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7),
 646 +       MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x0090, 8, 2, 15),
 647 +       MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23),
 648 +
 649 +       MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00A0, 0, 2, 7),
 650 +       MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00A0, 8, 3, 15),
 651 +       MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents, 0x00A0, 24, 2, 31),
 652 +
 653 +       MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 0x00B0, 0, 3, 7),
 654 +       MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 0x00B0, 8, 2, 15),
 655 +       MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents, 0x00B0, 16, 3, 23),
 656 +       MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents, 0x00B0, 24, 3, 31),
 657 +
 658 +       MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel", hdmirx_bist_parents, 0x00C0, 0, 3, 7),
 659 +       MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 0x00C0, 8, 2, 15),
 660 +       MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents, 0x00C0, 16, 2, 23),
 661 +       MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents, 0x00C0, 24, 3, 31),
 662 +
 663 +       MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents, 0x00D0, 0, 2, 7),
 664 +       MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents, 0x00D0, 16, 2, 23),
 665 +       MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents, 0x00D0, 24, 3, 31),
 666 +
 667 +       MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents, 0x00E0, 0, 1, 7),
 668 +       MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x00E0, 8, 3, 15),
 669 +       MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 0x00E0, 16, 4, 23),
 670 +
 671 +       MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents, 0x00E0, 24, 3, 31),
 672 +       MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents, 0x00F0, 0, 3, 7),
 673 +       MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents, 0x00F0, 8, 2, 15),
 674 +       MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents, 0x00F0, 16, 1, 23),
 675 +
 676 +       MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents, 0x0100, 0, 3),
 677 +
 678 +       MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents, 0x012c, 0, 3),
 679 +       MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents, 0x012c, 3, 3),
 680 +       MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents, 0x012c, 6, 3),
 681 +       MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents, 0x012c, 15, 1, 23),
 682 +       MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents, 0x012c, 16, 1, 24),
 683 +       MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents, 0x012c, 17, 1, 25),
 684 +       MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents, 0x012c, 18, 1, 26),
 685 +       MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents, 0x012c, 19, 1, 27),
 686 +       MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents, 0x012c, 20, 1, 28),
 687 +};
 688 +
 689 +static const struct mtk_clk_divider top_adj_divs[] __initconst = {
 690 +       DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext_ck1", 0x0120, 0, 8),
 691 +       DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext_ck2", 0x0120, 8, 8),
 692 +       DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel", 0x0120, 16, 8),
 693 +       DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel", 0x0120, 24, 8),
 694 +       DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel", 0x0124, 0, 8),
 695 +       DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel", 0x0124, 8, 8),
 696 +       DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel", 0x0124, 16, 8),
 697 +       DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel", 0x0124, 24, 8),
 698 +       DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel", 0x0128, 0, 8),
 699 +       DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel", 0x0128, 8, 8),
 700 +};
 701 +
 702 +static const struct mtk_gate_regs top_aud_cg_regs __initconst = {
 703 +       .sta_ofs = 0x012C,
 704 +};
 705 +
 706 +#define GATE_TOP_AUD(_id, _name, _parent, _shift) {    \
 707 +               .id = _id,                              \
 708 +               .name = _name,                          \
 709 +               .parent_name = _parent,                 \
 710 +               .regs = &top_aud_cg_regs,               \
 711 +               .shift = _shift,                        \
 712 +               .ops = &mtk_clk_gate_ops_no_setclr,     \
 713 +       }
 714 +
 715 +static const struct mtk_gate top_clks[] __initconst = {
 716 +       GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", 21),
 717 +       GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div", 22),
 718 +       GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div", 23),
 719 +       GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div", 24),
 720 +       GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div", 25),
 721 +       GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div", 26),
 722 +       GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div", 27),
 723 +       GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
 724 +};
 725 +
 726 +static void __init mtk_topckgen_init(struct device_node *node)
 727 +{
 728 +       struct clk_onecell_data *clk_data;
 729 +       void __iomem *base;
 730 +       int r;
 731 +
 732 +       base = of_iomap(node, 0);
 733 +       if (!base) {
 734 +               pr_err("%s(): ioremap failed\n", __func__);
 735 +               return;
 736 +       }
 737 +
 738 +       clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
 739 +
 740 +       mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 741 +                                                               clk_data);
 742 +
 743 +       mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
 744 +                                                               clk_data);
 745 +
 746 +       mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
 747 +                               base, &lock, clk_data);
 748 +
 749 +       mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
 750 +                               base, &lock, clk_data);
 751 +
 752 +       mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
 753 +                                               clk_data);
 754 +
 755 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 756 +       if (r)
 757 +               pr_err("%s(): could not register clock provider: %d\n",
 758 +                       __func__, r);
 759 +}
 760 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
 761 +
 762 +static const struct mtk_gate_regs infra_cg_regs __initconst = {
 763 +       .set_ofs = 0x0040,
 764 +       .clr_ofs = 0x0044,
 765 +       .sta_ofs = 0x0048,
 766 +};
 767 +
 768 +#define GATE_ICG(_id, _name, _parent, _shift) {                \
 769 +               .id = _id,                              \
 770 +               .name = _name,                          \
 771 +               .parent_name = _parent,                 \
 772 +               .regs = &infra_cg_regs,                 \
 773 +               .shift = _shift,                        \
 774 +               .ops = &mtk_clk_gate_ops_setclr,        \
 775 +       }
 776 +
 777 +static const struct mtk_gate infra_clks[] __initconst = {
 778 +       GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
 779 +       GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
 780 +       GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
 781 +       GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2_294m_ck", 4),
 782 +       GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk_null", 5),
 783 +       GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
 784 +       GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
 785 +       GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
 786 +       GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
 787 +       GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
 788 +       GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
 789 +       GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
 790 +       GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
 791 +       GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
 792 +       GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
 793 +       GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
 794 +       GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
 795 +       GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
 796 +};
 797 +
 798 +static const struct mtk_fixed_factor infra_fixed_divs[] __initconst = {
 799 +       FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 800 +};
 801 +
 802 +static void __init mtk_infrasys_init(struct device_node *node)
 803 +{
 804 +       struct clk_onecell_data *clk_data;
 805 +       int r;
 806 +
 807 +       clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 808 +
 809 +       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 810 +                                               clk_data);
 811 +       mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 812 +                                               clk_data);
 813 +
 814 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 815 +       if (r)
 816 +               pr_err("%s(): could not register clock provider: %d\n",
 817 +                       __func__, r);
 818 +}
 819 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init);
 820 +
 821 +static const struct mtk_gate_regs peri0_cg_regs __initconst = {
 822 +       .set_ofs = 0x0008,
 823 +       .clr_ofs = 0x0010,
 824 +       .sta_ofs = 0x0018,
 825 +};
 826 +
 827 +static const struct mtk_gate_regs peri1_cg_regs __initconst = {
 828 +       .set_ofs = 0x000c,
 829 +       .clr_ofs = 0x0014,
 830 +       .sta_ofs = 0x001c,
 831 +};
 832 +
 833 +#define GATE_PERI0(_id, _name, _parent, _shift) {      \
 834 +               .id = _id,                              \
 835 +               .name = _name,                          \
 836 +               .parent_name = _parent,                 \
 837 +               .regs = &peri0_cg_regs,                 \
 838 +               .shift = _shift,                        \
 839 +               .ops = &mtk_clk_gate_ops_setclr,        \
 840 +       }
 841 +
 842 +#define GATE_PERI1(_id, _name, _parent, _shift) {      \
 843 +               .id = _id,                              \
 844 +               .name = _name,                          \
 845 +               .parent_name = _parent,                 \
 846 +               .regs = &peri1_cg_regs,                 \
 847 +               .shift = _shift,                        \
 848 +               .ops = &mtk_clk_gate_ops_setclr,        \
 849 +       }
 850 +
 851 +static const struct mtk_gate peri_clks[] __initconst = {
 852 +       GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
 853 +       GATE_PERI1(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
 854 +       GATE_PERI1(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
 855 +       GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
 856 +       GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
 857 +       GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
 858 +       GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
 859 +       GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
 860 +       GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
 861 +       GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
 862 +       GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
 863 +       GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
 864 +       GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
 865 +       GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
 866 +       GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
 867 +       GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
 868 +       GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
 869 +       GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
 870 +       GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
 871 +       GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
 872 +       GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
 873 +       GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
 874 +       GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
 875 +       GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
 876 +       GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
 877 +       GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
 878 +       GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
 879 +       GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
 880 +       GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
 881 +       GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
 882 +       GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
 883 +       GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
 884 +
 885 +       GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card", 11),
 886 +       GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
 887 +       GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
 888 +       GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
 889 +       GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
 890 +       GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
 891 +       GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
 892 +       GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi_sel", 4),
 893 +       GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi_sel", 3),
 894 +       GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
 895 +       GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
 896 +       GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
 897 +};
 898 +
 899 +static const char * const uart_ck_sel_parents[] __initconst = {
 900 +       "clk26m",
 901 +       "uart_sel",
 902 +};
 903 +
 904 +static const struct mtk_composite peri_muxs[] __initconst = {
 905 +       MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
 906 +       MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
 907 +       MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
 908 +       MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 909 +};
 910 +
 911 +static void __init mtk_pericfg_init(struct device_node *node)
 912 +{
 913 +       struct clk_onecell_data *clk_data;
 914 +       void __iomem *base;
 915 +       int r;
 916 +
 917 +       base = of_iomap(node, 0);
 918 +       if (!base) {
 919 +               pr_err("%s(): ioremap failed\n", __func__);
 920 +               return;
 921 +       }
 922 +
 923 +       clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
 924 +
 925 +       mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
 926 +                                               clk_data);
 927 +
 928 +       mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
 929 +                       &lock, clk_data);
 930 +
 931 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 932 +       if (r)
 933 +               pr_err("%s(): could not register clock provider: %d\n",
 934 +                       __func__, r);
 935 +}
 936 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init);
 937 +
 938 +static const struct mtk_gate_regs disp0_cg_regs __initconst = {
 939 +       .set_ofs = 0x0104,
 940 +       .clr_ofs = 0x0108,
 941 +       .sta_ofs = 0x0100,
 942 +};
 943 +
 944 +static const struct mtk_gate_regs disp1_cg_regs __initconst = {
 945 +       .set_ofs = 0x0114,
 946 +       .clr_ofs = 0x0118,
 947 +       .sta_ofs = 0x0110,
 948 +};
 949 +
 950 +#define GATE_DISP0(_id, _name, _parent, _shift) {      \
 951 +               .id = _id,                              \
 952 +               .name = _name,                          \
 953 +               .parent_name = _parent,                 \
 954 +               .regs = &disp0_cg_regs,                 \
 955 +               .shift = _shift,                        \
 956 +               .ops = &mtk_clk_gate_ops_setclr,        \
 957 +       }
 958 +
 959 +#define GATE_DISP1(_id, _name, _parent, _shift) {      \
 960 +               .id = _id,                              \
 961 +               .name = _name,                          \
 962 +               .parent_name = _parent,                 \
 963 +               .regs = &disp1_cg_regs,                 \
 964 +               .shift = _shift,                        \
 965 +               .ops = &mtk_clk_gate_ops_setclr,        \
 966 +       }
 967 +
 968 +static const struct mtk_gate mm_clks[] __initconst = {
 969 +       GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
 970 +       GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
 971 +       GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
 972 +       GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
 973 +       GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
 974 +       GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
 975 +       GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
 976 +       GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
 977 +       GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
 978 +       GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
 979 +       GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
 980 +       GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
 981 +       GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
 982 +       GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
 983 +       GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
 984 +       GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "clk26m", 15),
 985 +       GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
 986 +       GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
 987 +       GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
 988 +       GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
 989 +       GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
 990 +       GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
 991 +       GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsio_lntc_dsiclk", 1),
 992 +       GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
 993 +       GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
 994 +       GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
 995 +       GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
 996 +       GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
 997 +       GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
 998 +       GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
 999 +       GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
1000 +       GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
1001 +       GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
1002 +       GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
1003 +};
1004 +
1005 +static void __init mtk_mmsys_init(struct device_node *node)
1006 +{
1007 +       struct clk_onecell_data *clk_data;
1008 +       int r;
1009 +
1010 +       clk_data = mtk_alloc_clk_data(CLK_MM_NR);
1011 +
1012 +       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
1013 +                                               clk_data);
1014 +
1015 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1016 +       if (r)
1017 +               pr_err("%s(): could not register clock provider: %d\n",
1018 +                       __func__, r);
1019 +}
1020 +CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt2701-mmsys", mtk_mmsys_init);
1021 +
1022 +static const struct mtk_gate_regs img_cg_regs __initconst = {
1023 +       .set_ofs = 0x0004,
1024 +       .clr_ofs = 0x0008,
1025 +       .sta_ofs = 0x0000,
1026 +};
1027 +
1028 +#define GATE_IMG(_id, _name, _parent, _shift) {                \
1029 +               .id = _id,                              \
1030 +               .name = _name,                          \
1031 +               .parent_name = _parent,                 \
1032 +               .regs = &img_cg_regs,                   \
1033 +               .shift = _shift,                        \
1034 +               .ops = &mtk_clk_gate_ops_setclr,        \
1035 +       }
1036 +
1037 +static const struct mtk_gate img_clks[] __initconst = {
1038 +       GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0),
1039 +       GATE_IMG(CLK_IMG_RESZ, "img_resz", "mm_sel", 1),
1040 +       GATE_IMG(CLK_IMG_JPGDEC, "img_jpgdec", "mm_sel", 5),
1041 +       GATE_IMG(CLK_IMG_VENC_LT, "img_venc_lt", "mm_sel", 8),
1042 +       GATE_IMG(CLK_IMG_VENC, "img_venc", "mm_sel", 9),
1043 +};
1044 +
1045 +static void __init mtk_imgsys_init(struct device_node *node)
1046 +{
1047 +       struct clk_onecell_data *clk_data;
1048 +       int r;
1049 +
1050 +       clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
1051 +
1052 +       mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
1053 +                                               clk_data);
1054 +
1055 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1056 +       if (r)
1057 +               pr_err("%s(): could not register clock provider: %d\n",
1058 +                       __func__, r);
1059 +}
1060 +CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt2701-imgsys", mtk_imgsys_init);
1061 +
1062 +static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
1063 +       .set_ofs = 0x0000,
1064 +       .clr_ofs = 0x0004,
1065 +       .sta_ofs = 0x0000,
1066 +};
1067 +
1068 +static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
1069 +       .set_ofs = 0x0008,
1070 +       .clr_ofs = 0x000c,
1071 +       .sta_ofs = 0x0008,
1072 +};
1073 +
1074 +#define GATE_VDEC0(_id, _name, _parent, _shift) {      \
1075 +               .id = _id,                              \
1076 +               .name = _name,                          \
1077 +               .parent_name = _parent,                 \
1078 +               .regs = &vdec0_cg_regs,                 \
1079 +               .shift = _shift,                        \
1080 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
1081 +       }
1082 +
1083 +#define GATE_VDEC1(_id, _name, _parent, _shift) {      \
1084 +               .id = _id,                              \
1085 +               .name = _name,                          \
1086 +               .parent_name = _parent,                 \
1087 +               .regs = &vdec1_cg_regs,                 \
1088 +               .shift = _shift,                        \
1089 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
1090 +       }
1091 +
1092 +static const struct mtk_gate vdec_clks[] __initconst = {
1093 +       GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
1094 +       GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
1095 +};
1096 +
1097 +static void __init mtk_vdecsys_init(struct device_node *node)
1098 +{
1099 +       struct clk_onecell_data *clk_data;
1100 +       int r;
1101 +
1102 +       clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
1103 +
1104 +       mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
1105 +                                               clk_data);
1106 +
1107 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1108 +       if (r)
1109 +               pr_err("%s(): could not register clock provider: %d\n",
1110 +                       __func__, r);
1111 +}
1112 +CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt2701-vdecsys", mtk_vdecsys_init);
1113 +
1114 +static const struct mtk_gate_regs hif_cg_regs __initconst = {
1115 +       .sta_ofs = 0x0008,
1116 +};
1117 +
1118 +#define GATE_HIF(_id, _name, _parent, _shift) {                \
1119 +               .id = _id,                              \
1120 +               .name = _name,                          \
1121 +               .parent_name = _parent,                 \
1122 +               .regs = &hif_cg_regs,                   \
1123 +               .shift = _shift,                        \
1124 +               .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1125 +       }
1126 +
1127 +static const struct mtk_gate hif_clks[] __initconst = {
1128 +       GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
1129 +       GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
1130 +       GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
1131 +       GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
1132 +       GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
1133 +};
1134 +
1135 +static void __init mtk_hifsys_init(struct device_node *node)
1136 +{
1137 +       struct clk_onecell_data *clk_data;
1138 +       int r;
1139 +
1140 +       clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
1141 +
1142 +       mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
1143 +                                               clk_data);
1144 +
1145 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1146 +       if (r)
1147 +               pr_err("%s(): could not register clock provider: %d\n",
1148 +                       __func__, r);
1149 +}
1150 +CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);
1151 +
1152 +static const struct mtk_gate_regs eth_cg_regs __initconst = {
1153 +       .sta_ofs = 0x0030,
1154 +};
1155 +
1156 +#define GATE_eth(_id, _name, _parent, _shift) {                \
1157 +               .id = _id,                              \
1158 +               .name = _name,                          \
1159 +               .parent_name = _parent,                 \
1160 +               .regs = &eth_cg_regs,                   \
1161 +               .shift = _shift,                        \
1162 +               .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1163 +       }
1164 +
1165 +static const struct mtk_gate eth_clks[] __initconst = {
1166 +       GATE_HIF(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
1167 +       GATE_HIF(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
1168 +       GATE_HIF(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
1169 +       GATE_HIF(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
1170 +       GATE_HIF(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
1171 +       GATE_HIF(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
1172 +       GATE_HIF(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
1173 +       GATE_HIF(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
1174 +};
1175 +
1176 +static void __init mtk_ethsys_init(struct device_node *node)
1177 +{
1178 +       struct clk_onecell_data *clk_data;
1179 +       int r;
1180 +
1181 +       clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
1182 +
1183 +       mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
1184 +                                               clk_data);
1185 +
1186 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1187 +       if (r)
1188 +               pr_err("%s(): could not register clock provider: %d\n",
1189 +                       __func__, r);
1190 +}
1191 +CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt2701-ethsys", mtk_ethsys_init);
1192 +
1193 +static const struct mtk_gate_regs bdp0_cg_regs __initconst = {
1194 +       .set_ofs = 0x0104,
1195 +       .clr_ofs = 0x0108,
1196 +       .sta_ofs = 0x0100,
1197 +};
1198 +
1199 +static const struct mtk_gate_regs bdp1_cg_regs __initconst = {
1200 +       .set_ofs = 0x0114,
1201 +       .clr_ofs = 0x0118,
1202 +       .sta_ofs = 0x0110,
1203 +};
1204 +
1205 +#define GATE_BDP0(_id, _name, _parent, _shift) {       \
1206 +               .id = _id,                              \
1207 +               .name = _name,                          \
1208 +               .parent_name = _parent,                 \
1209 +               .regs = &bdp0_cg_regs,                  \
1210 +               .shift = _shift,                        \
1211 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
1212 +       }
1213 +
1214 +#define GATE_BDP1(_id, _name, _parent, _shift) {       \
1215 +               .id = _id,                              \
1216 +               .name = _name,                          \
1217 +               .parent_name = _parent,                 \
1218 +               .regs = &bdp1_cg_regs,                  \
1219 +               .shift = _shift,                        \
1220 +               .ops = &mtk_clk_gate_ops_setclr_inv,    \
1221 +       }
1222 +
1223 +static const struct mtk_gate bdp_clks[] __initconst = {
1224 +       GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
1225 +       GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
1226 +       GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
1227 +       GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
1228 +       GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
1229 +       GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
1230 +       GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
1231 +       GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi_sel", 7),
1232 +       GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
1233 +       GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
1234 +       GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
1235 +       GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
1236 +       GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
1237 +       GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
1238 +       GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
1239 +       GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
1240 +       GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
1241 +       GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
1242 +       GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
1243 +       GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
1244 +       GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
1245 +       GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
1246 +       GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
1247 +       GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
1248 +       GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
1249 +       GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
1250 +       GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
1251 +       GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
1252 +       GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
1253 +       GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
1254 +       GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
1255 +       GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
1256 +       GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
1257 +       GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
1258 +       GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
1259 +       GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
1260 +       GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
1261 +       GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
1262 +       GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
1263 +       GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
1264 +       GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
1265 +       GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
1266 +       GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
1267 +       GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
1268 +       GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
1269 +       GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
1270 +       GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
1271 +       GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
1272 +       GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_mon", 16),
1273 +};
1274 +
1275 +static void __init mtk_bdpsys_init(struct device_node *node)
1276 +{
1277 +       struct clk_onecell_data *clk_data;
1278 +       int r;
1279 +
1280 +       clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
1281 +
1282 +       mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
1283 +                                               clk_data);
1284 +
1285 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1286 +       if (r)
1287 +               pr_err("%s(): could not register clock provider: %d\n",
1288 +                       __func__, r);
1289 +}
1290 +CLK_OF_DECLARE(mtk_bdpsys, "mediatek,mt2701-bdpsys", mtk_bdpsys_init);
1291 +
1292 +#define MT8590_PLL_FMAX                (2000 * MHZ)
1293 +#define CON0_MT8590_RST_BAR    BIT(27)
1294 +
1295 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
1296 +                       _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) {  \
1297 +               .id = _id,                                              \
1298 +               .name = _name,                                          \
1299 +               .reg = _reg,                                            \
1300 +               .pwr_reg = _pwr_reg,                                    \
1301 +               .en_mask = _en_mask,                                    \
1302 +               .flags = _flags,                                        \
1303 +               .rst_bar_mask = CON0_MT8590_RST_BAR,                    \
1304 +               .fmax = MT8590_PLL_FMAX,                                \
1305 +               .pcwbits = _pcwbits,                                    \
1306 +               .pd_reg = _pd_reg,                                      \
1307 +               .pd_shift = _pd_shift,                                  \
1308 +               .tuner_reg = _tuner_reg,                                \
1309 +               .pcw_reg = _pcw_reg,                                    \
1310 +               .pcw_shift = _pcw_shift,                                \
1311 +       }
1312 +
1313 +static const struct mtk_pll_data apmixed_plls[] = {
1314 +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001, 0,
1315 +                               21, 0x204, 24, 0x0, 0x204, 0),
1316 +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
1317 +                 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
1318 +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
1319 +                 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
1320 +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
1321 +                               21, 0x230, 4, 0x0, 0x234, 0),
1322 +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
1323 +                               21, 0x240, 4, 0x0, 0x244, 0),
1324 +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
1325 +                               21, 0x250, 4, 0x0, 0x254, 0),
1326 +       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
1327 +                               31, 0x270, 4, 0x0, 0x274, 0),
1328 +       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
1329 +                               31, 0x280, 4, 0x0, 0x284, 0),
1330 +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
1331 +                               31, 0x290, 4, 0x0, 0x294, 0),
1332 +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
1333 +                               31, 0x2a0, 4, 0x0, 0x2a4, 0),
1334 +       PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
1335 +                               31, 0x2b0, 4, 0x0, 0x2b4, 0),
1336 +       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
1337 +                               31, 0x2c0, 4, 0x0, 0x2c4, 0),
1338 +       PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
1339 +                               21, 0x2d0, 4, 0x0, 0x2d4, 0),
1340 +};
1341 +
1342 +static void __init mtk_apmixedsys_init(struct device_node *node)
1343 +{
1344 +       struct clk_onecell_data *clk_data;
1345 +       int r;
1346 +
1347 +       clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
1348 +       if (!clk_data)
1349 +               return;
1350 +
1351 +       mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
1352 +                                                               clk_data);
1353 +
1354 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1355 +       if (r)
1356 +               pr_err("%s(): could not register clock provider: %d\n",
1357 +                       __func__, r);
1358 +}
1359 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
1360 +                                                       mtk_apmixedsys_init);
1361 diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
1362 index cf08db6..be19a41 100644
1363 --- a/drivers/clk/mediatek/clk-mtk.c
1364 +++ b/drivers/clk/mediatek/clk-mtk.c
1365 @@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
1366                         clk_data->clks[mc->id] = clk;
1367         }
1368  }
1369 +
1370 +void __init mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
1371 +                       int num, void __iomem *base, spinlock_t *lock,
1372 +                               struct clk_onecell_data *clk_data)
1373 +{
1374 +       struct clk *clk;
1375 +       int i;
1376 +
1377 +       for (i = 0; i <  num; i++) {
1378 +               const struct mtk_clk_divider *mcd = &mcds[i];
1379 +
1380 +               clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
1381 +                       mcd->flags, base +  mcd->div_reg, mcd->div_shift,
1382 +                       mcd->div_width, mcd->clk_divider_flags, lock);
1383 +
1384 +               if (IS_ERR(clk)) {
1385 +                       pr_err("Failed to register clk %s: %ld\n",
1386 +                               mcd->name, PTR_ERR(clk));
1387 +                       continue;
1388 +               }
1389 +
1390 +               if (clk_data)
1391 +                       clk_data->clks[mcd->id] = clk;
1392 +       }
1393 +}
1394 diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
1395 index 32d2e45..60701e8 100644
1396 --- a/drivers/clk/mediatek/clk-mtk.h
1397 +++ b/drivers/clk/mediatek/clk-mtk.h
1398 @@ -110,7 +110,8 @@ struct mtk_composite {
1399                 .flags = CLK_SET_RATE_PARENT,                           \
1400         }
1401
1402 -#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) {      \
1403 +#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg,        \
1404 +                                       _div_width, _div_shift) {       \
1405                 .id = _id,                                              \
1406                 .parent = _parent,                                      \
1407                 .name = _name,                                          \
1408 @@ -145,8 +146,36 @@ struct mtk_gate {
1409         const struct clk_ops *ops;
1410  };
1411
1412 -int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
1413 -               int num, struct clk_onecell_data *clk_data);
1414 +int mtk_clk_register_gates(struct device_node *node,
1415 +                       const struct mtk_gate *clks, int num,
1416 +                       struct clk_onecell_data *clk_data);
1417 +
1418 +struct mtk_clk_divider {
1419 +       int id;
1420 +       const char *name;
1421 +       const char *parent_name;
1422 +       unsigned long flags;
1423 +
1424 +       uint32_t div_reg;
1425 +       unsigned char div_shift;
1426 +       unsigned char div_width;
1427 +       unsigned char clk_divider_flags;
1428 +       const struct clk_div_table *clk_div_table;
1429 +};
1430 +
1431 +#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) {   \
1432 +               .id = _id,                                      \
1433 +               .name = _name,                                  \
1434 +               .parent_name = _parent,                         \
1435 +               .flags = CLK_SET_RATE_PARENT,                   \
1436 +               .div_reg = _reg,                                \
1437 +               .div_shift = _shift,                            \
1438 +               .div_width = _width,                            \
1439 +}
1440 +
1441 +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
1442 +                       int num, void __iomem *base, spinlock_t *lock,
1443 +                               struct clk_onecell_data *clk_data);
1444
1445  struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
1446
1447 --
1448 1.7.10.4
1449