target/linux/mediatek/patches-4.4/0002-soc-mediatek-Separate-scpsys-driver-common-code.patch

   1 From 2c93328ed05061a50e3bd4111379dbcf6946d3ac Mon Sep 17 00:00:00 2001
   2 From: James Liao <jamesjj.liao@mediatek.com>
   3 Date: Wed, 30 Dec 2015 14:41:43 +0800
   4 Subject: [PATCH 02/90] soc: mediatek: Separate scpsys driver common code
   5
   6 Separate scpsys driver common code to mtk-scpsys.c, and move MT8173
   7 platform code to mtk-scpsys-mt8173.c.
   8
   9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  10 ---
  11  drivers/soc/mediatek/Kconfig             |   13 +-
  12  drivers/soc/mediatek/Makefile            |    1 +
  13  drivers/soc/mediatek/mtk-scpsys-mt8173.c |  179 ++++++++++++++++++
  14  drivers/soc/mediatek/mtk-scpsys.c        |  301 ++++++++----------------------
  15  drivers/soc/mediatek/mtk-scpsys.h        |   54 ++++++
  16  5 files changed, 320 insertions(+), 228 deletions(-)
  17  create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt8173.c
  18  create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
  19
  20 diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
  21 index 0a4ea80..eca6fb7 100644
  22 --- a/drivers/soc/mediatek/Kconfig
  23 +++ b/drivers/soc/mediatek/Kconfig
  24 @@ -22,11 +22,20 @@ config MTK_PMIC_WRAP
  25
  26  config MTK_SCPSYS
  27         bool "MediaTek SCPSYS Support"
  28 -       depends on ARCH_MEDIATEK || COMPILE_TEST
  29 -       default ARM64 && ARCH_MEDIATEK
  30         select REGMAP
  31         select MTK_INFRACFG
  32         select PM_GENERIC_DOMAINS if PM
  33         help
  34           Say yes here to add support for the MediaTek SCPSYS power domain
  35           driver.
  36 +
  37 +config MTK_SCPSYS_MT8173
  38 +       bool "MediaTek MT8173 SCPSYS Support"
  39 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  40 +       select MTK_SCPSYS
  41 +       default ARCH_MEDIATEK
  42 +       help
  43 +         Say yes here to add support for the MT8173 SCPSYS power domain
  44 +         driver.
  45 +         The System Control Processor System (SCPSYS) has several power
  46 +         management related tasks in the system.
  47 diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
  48 index 12998b0..3b22baa 100644
  49 --- a/drivers/soc/mediatek/Makefile
  50 +++ b/drivers/soc/mediatek/Makefile
  51 @@ -1,3 +1,4 @@
  52  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
  53  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  54  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
  55 +obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
  56 diff --git a/drivers/soc/mediatek/mtk-scpsys-mt8173.c b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
  57 new file mode 100644
  58 index 0000000..3c7b569
  59 --- /dev/null
  60 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
  61 @@ -0,0 +1,179 @@
  62 +/*
  63 + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
  64 + *
  65 + * This program is free software; you can redistribute it and/or modify
  66 + * it under the terms of the GNU General Public License version 2 as
  67 + * published by the Free Software Foundation.
  68 + *
  69 + * This program is distributed in the hope that it will be useful,
  70 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  71 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  72 + * GNU General Public License for more details.
  73 + */
  74 +#include <linux/mfd/syscon.h>
  75 +#include <linux/module.h>
  76 +#include <linux/of_device.h>
  77 +#include <linux/pm_domain.h>
  78 +#include <linux/soc/mediatek/infracfg.h>
  79 +#include <dt-bindings/power/mt8173-power.h>
  80 +
  81 +#include "mtk-scpsys.h"
  82 +
  83 +#define SPM_VDE_PWR_CON                        0x0210
  84 +#define SPM_MFG_PWR_CON                        0x0214
  85 +#define SPM_VEN_PWR_CON                        0x0230
  86 +#define SPM_ISP_PWR_CON                        0x0238
  87 +#define SPM_DIS_PWR_CON                        0x023c
  88 +#define SPM_VEN2_PWR_CON               0x0298
  89 +#define SPM_AUDIO_PWR_CON              0x029c
  90 +#define SPM_MFG_2D_PWR_CON             0x02c0
  91 +#define SPM_MFG_ASYNC_PWR_CON          0x02c4
  92 +#define SPM_USB_PWR_CON                        0x02cc
  93 +
  94 +#define PWR_STATUS_DISP                        BIT(3)
  95 +#define PWR_STATUS_MFG                 BIT(4)
  96 +#define PWR_STATUS_ISP                 BIT(5)
  97 +#define PWR_STATUS_VDEC                        BIT(7)
  98 +#define PWR_STATUS_VENC_LT             BIT(20)
  99 +#define PWR_STATUS_VENC                        BIT(21)
 100 +#define PWR_STATUS_MFG_2D              BIT(22)
 101 +#define PWR_STATUS_MFG_ASYNC           BIT(23)
 102 +#define PWR_STATUS_AUDIO               BIT(24)
 103 +#define PWR_STATUS_USB                 BIT(25)
 104 +
 105 +static const struct scp_domain_data scp_domain_data[] __initconst = {
 106 +       [MT8173_POWER_DOMAIN_VDEC] = {
 107 +               .name = "vdec",
 108 +               .sta_mask = PWR_STATUS_VDEC,
 109 +               .ctl_offs = SPM_VDE_PWR_CON,
 110 +               .sram_pdn_bits = GENMASK(11, 8),
 111 +               .sram_pdn_ack_bits = GENMASK(12, 12),
 112 +               .clk_id = {CLK_MM},
 113 +       },
 114 +       [MT8173_POWER_DOMAIN_VENC] = {
 115 +               .name = "venc",
 116 +               .sta_mask = PWR_STATUS_VENC,
 117 +               .ctl_offs = SPM_VEN_PWR_CON,
 118 +               .sram_pdn_bits = GENMASK(11, 8),
 119 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 120 +               .clk_id = {CLK_MM, CLK_VENC},
 121 +       },
 122 +       [MT8173_POWER_DOMAIN_ISP] = {
 123 +               .name = "isp",
 124 +               .sta_mask = PWR_STATUS_ISP,
 125 +               .ctl_offs = SPM_ISP_PWR_CON,
 126 +               .sram_pdn_bits = GENMASK(11, 8),
 127 +               .sram_pdn_ack_bits = GENMASK(13, 12),
 128 +               .clk_id = {CLK_MM},
 129 +       },
 130 +       [MT8173_POWER_DOMAIN_MM] = {
 131 +               .name = "mm",
 132 +               .sta_mask = PWR_STATUS_DISP,
 133 +               .ctl_offs = SPM_DIS_PWR_CON,
 134 +               .sram_pdn_bits = GENMASK(11, 8),
 135 +               .sram_pdn_ack_bits = GENMASK(12, 12),
 136 +               .clk_id = {CLK_MM},
 137 +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
 138 +                       MT8173_TOP_AXI_PROT_EN_MM_M1,
 139 +       },
 140 +       [MT8173_POWER_DOMAIN_VENC_LT] = {
 141 +               .name = "venc_lt",
 142 +               .sta_mask = PWR_STATUS_VENC_LT,
 143 +               .ctl_offs = SPM_VEN2_PWR_CON,
 144 +               .sram_pdn_bits = GENMASK(11, 8),
 145 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 146 +               .clk_id = {CLK_MM, CLK_VENC_LT},
 147 +       },
 148 +       [MT8173_POWER_DOMAIN_AUDIO] = {
 149 +               .name = "audio",
 150 +               .sta_mask = PWR_STATUS_AUDIO,
 151 +               .ctl_offs = SPM_AUDIO_PWR_CON,
 152 +               .sram_pdn_bits = GENMASK(11, 8),
 153 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 154 +               .clk_id = {CLK_NONE},
 155 +       },
 156 +       [MT8173_POWER_DOMAIN_USB] = {
 157 +               .name = "usb",
 158 +               .sta_mask = PWR_STATUS_USB,
 159 +               .ctl_offs = SPM_USB_PWR_CON,
 160 +               .sram_pdn_bits = GENMASK(11, 8),
 161 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 162 +               .clk_id = {CLK_NONE},
 163 +               .active_wakeup = true,
 164 +       },
 165 +       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
 166 +               .name = "mfg_async",
 167 +               .sta_mask = PWR_STATUS_MFG_ASYNC,
 168 +               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
 169 +               .sram_pdn_bits = GENMASK(11, 8),
 170 +               .sram_pdn_ack_bits = 0,
 171 +               .clk_id = {CLK_MFG},
 172 +       },
 173 +       [MT8173_POWER_DOMAIN_MFG_2D] = {
 174 +               .name = "mfg_2d",
 175 +               .sta_mask = PWR_STATUS_MFG_2D,
 176 +               .ctl_offs = SPM_MFG_2D_PWR_CON,
 177 +               .sram_pdn_bits = GENMASK(11, 8),
 178 +               .sram_pdn_ack_bits = GENMASK(13, 12),
 179 +               .clk_id = {CLK_NONE},
 180 +       },
 181 +       [MT8173_POWER_DOMAIN_MFG] = {
 182 +               .name = "mfg",
 183 +               .sta_mask = PWR_STATUS_MFG,
 184 +               .ctl_offs = SPM_MFG_PWR_CON,
 185 +               .sram_pdn_bits = GENMASK(13, 8),
 186 +               .sram_pdn_ack_bits = GENMASK(21, 16),
 187 +               .clk_id = {CLK_NONE},
 188 +               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
 189 +                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
 190 +                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
 191 +                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
 192 +       },
 193 +};
 194 +
 195 +#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
 196 +
 197 +static int __init scpsys_probe(struct platform_device *pdev)
 198 +{
 199 +       struct scp *scp;
 200 +       struct genpd_onecell_data *pd_data;
 201 +       int ret;
 202 +
 203 +       scp = init_scp(pdev, scp_domain_data, NUM_DOMAINS);
 204 +       if (IS_ERR(scp))
 205 +               return PTR_ERR(scp);
 206 +
 207 +       mtk_register_power_domains(pdev, scp, NUM_DOMAINS);
 208 +
 209 +       pd_data = &scp->pd_data;
 210 +
 211 +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
 212 +               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
 213 +       if (ret && IS_ENABLED(CONFIG_PM))
 214 +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
 215 +
 216 +       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
 217 +               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
 218 +       if (ret && IS_ENABLED(CONFIG_PM))
 219 +               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
 220 +
 221 +       return 0;
 222 +}
 223 +
 224 +static const struct of_device_id of_scpsys_match_tbl[] = {
 225 +       {
 226 +               .compatible = "mediatek,mt8173-scpsys",
 227 +       }, {
 228 +               /* sentinel */
 229 +       }
 230 +};
 231 +
 232 +static struct platform_driver scpsys_drv = {
 233 +       .driver = {
 234 +               .name = "mtk-scpsys-mt8173",
 235 +               .owner = THIS_MODULE,
 236 +               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
 237 +       },
 238 +};
 239 +
 240 +module_platform_driver_probe(scpsys_drv, scpsys_probe);
 241 diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
 242 index 4d4203c..a0943c5 100644
 243 --- a/drivers/soc/mediatek/mtk-scpsys.c
 244 +++ b/drivers/soc/mediatek/mtk-scpsys.c
 245 @@ -11,28 +11,14 @@
 246   * GNU General Public License for more details.
 247   */
 248  #include <linux/clk.h>
 249 -#include <linux/delay.h>
 250  #include <linux/io.h>
 251 -#include <linux/kernel.h>
 252  #include <linux/mfd/syscon.h>
 253 -#include <linux/module.h>
 254 -#include <linux/of_device.h>
 255  #include <linux/platform_device.h>
 256  #include <linux/pm_domain.h>
 257 -#include <linux/regmap.h>
 258  #include <linux/soc/mediatek/infracfg.h>
 259 -#include <dt-bindings/power/mt8173-power.h>
 260 -
 261 -#define SPM_VDE_PWR_CON                        0x0210
 262 -#define SPM_MFG_PWR_CON                        0x0214
 263 -#define SPM_VEN_PWR_CON                        0x0230
 264 -#define SPM_ISP_PWR_CON                        0x0238
 265 -#define SPM_DIS_PWR_CON                        0x023c
 266 -#define SPM_VEN2_PWR_CON               0x0298
 267 -#define SPM_AUDIO_PWR_CON              0x029c
 268 -#define SPM_MFG_2D_PWR_CON             0x02c0
 269 -#define SPM_MFG_ASYNC_PWR_CON          0x02c4
 270 -#define SPM_USB_PWR_CON                        0x02cc
 271 +
 272 +#include "mtk-scpsys.h"
 273 +
 274  #define SPM_PWR_STATUS                 0x060c
 275  #define SPM_PWR_STATUS_2ND             0x0610
 276
 277 @@ -42,153 +28,6 @@
 278  #define PWR_ON_2ND_BIT                 BIT(3)
 279  #define PWR_CLK_DIS_BIT                        BIT(4)
 280
 281 -#define PWR_STATUS_DISP                        BIT(3)
 282 -#define PWR_STATUS_MFG                 BIT(4)
 283 -#define PWR_STATUS_ISP                 BIT(5)
 284 -#define PWR_STATUS_VDEC                        BIT(7)
 285 -#define PWR_STATUS_VENC_LT             BIT(20)
 286 -#define PWR_STATUS_VENC                        BIT(21)
 287 -#define PWR_STATUS_MFG_2D              BIT(22)
 288 -#define PWR_STATUS_MFG_ASYNC           BIT(23)
 289 -#define PWR_STATUS_AUDIO               BIT(24)
 290 -#define PWR_STATUS_USB                 BIT(25)
 291 -
 292 -enum clk_id {
 293 -       MT8173_CLK_NONE,
 294 -       MT8173_CLK_MM,
 295 -       MT8173_CLK_MFG,
 296 -       MT8173_CLK_VENC,
 297 -       MT8173_CLK_VENC_LT,
 298 -       MT8173_CLK_MAX,
 299 -};
 300 -
 301 -#define MAX_CLKS       2
 302 -
 303 -struct scp_domain_data {
 304 -       const char *name;
 305 -       u32 sta_mask;
 306 -       int ctl_offs;
 307 -       u32 sram_pdn_bits;
 308 -       u32 sram_pdn_ack_bits;
 309 -       u32 bus_prot_mask;
 310 -       enum clk_id clk_id[MAX_CLKS];
 311 -       bool active_wakeup;
 312 -};
 313 -
 314 -static const struct scp_domain_data scp_domain_data[] __initconst = {
 315 -       [MT8173_POWER_DOMAIN_VDEC] = {
 316 -               .name = "vdec",
 317 -               .sta_mask = PWR_STATUS_VDEC,
 318 -               .ctl_offs = SPM_VDE_PWR_CON,
 319 -               .sram_pdn_bits = GENMASK(11, 8),
 320 -               .sram_pdn_ack_bits = GENMASK(12, 12),
 321 -               .clk_id = {MT8173_CLK_MM},
 322 -       },
 323 -       [MT8173_POWER_DOMAIN_VENC] = {
 324 -               .name = "venc",
 325 -               .sta_mask = PWR_STATUS_VENC,
 326 -               .ctl_offs = SPM_VEN_PWR_CON,
 327 -               .sram_pdn_bits = GENMASK(11, 8),
 328 -               .sram_pdn_ack_bits = GENMASK(15, 12),
 329 -               .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
 330 -       },
 331 -       [MT8173_POWER_DOMAIN_ISP] = {
 332 -               .name = "isp",
 333 -               .sta_mask = PWR_STATUS_ISP,
 334 -               .ctl_offs = SPM_ISP_PWR_CON,
 335 -               .sram_pdn_bits = GENMASK(11, 8),
 336 -               .sram_pdn_ack_bits = GENMASK(13, 12),
 337 -               .clk_id = {MT8173_CLK_MM},
 338 -       },
 339 -       [MT8173_POWER_DOMAIN_MM] = {
 340 -               .name = "mm",
 341 -               .sta_mask = PWR_STATUS_DISP,
 342 -               .ctl_offs = SPM_DIS_PWR_CON,
 343 -               .sram_pdn_bits = GENMASK(11, 8),
 344 -               .sram_pdn_ack_bits = GENMASK(12, 12),
 345 -               .clk_id = {MT8173_CLK_MM},
 346 -               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
 347 -                       MT8173_TOP_AXI_PROT_EN_MM_M1,
 348 -       },
 349 -       [MT8173_POWER_DOMAIN_VENC_LT] = {
 350 -               .name = "venc_lt",
 351 -               .sta_mask = PWR_STATUS_VENC_LT,
 352 -               .ctl_offs = SPM_VEN2_PWR_CON,
 353 -               .sram_pdn_bits = GENMASK(11, 8),
 354 -               .sram_pdn_ack_bits = GENMASK(15, 12),
 355 -               .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
 356 -       },
 357 -       [MT8173_POWER_DOMAIN_AUDIO] = {
 358 -               .name = "audio",
 359 -               .sta_mask = PWR_STATUS_AUDIO,
 360 -               .ctl_offs = SPM_AUDIO_PWR_CON,
 361 -               .sram_pdn_bits = GENMASK(11, 8),
 362 -               .sram_pdn_ack_bits = GENMASK(15, 12),
 363 -               .clk_id = {MT8173_CLK_NONE},
 364 -       },
 365 -       [MT8173_POWER_DOMAIN_USB] = {
 366 -               .name = "usb",
 367 -               .sta_mask = PWR_STATUS_USB,
 368 -               .ctl_offs = SPM_USB_PWR_CON,
 369 -               .sram_pdn_bits = GENMASK(11, 8),
 370 -               .sram_pdn_ack_bits = GENMASK(15, 12),
 371 -               .clk_id = {MT8173_CLK_NONE},
 372 -               .active_wakeup = true,
 373 -       },
 374 -       [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
 375 -               .name = "mfg_async",
 376 -               .sta_mask = PWR_STATUS_MFG_ASYNC,
 377 -               .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
 378 -               .sram_pdn_bits = GENMASK(11, 8),
 379 -               .sram_pdn_ack_bits = 0,
 380 -               .clk_id = {MT8173_CLK_MFG},
 381 -       },
 382 -       [MT8173_POWER_DOMAIN_MFG_2D] = {
 383 -               .name = "mfg_2d",
 384 -               .sta_mask = PWR_STATUS_MFG_2D,
 385 -               .ctl_offs = SPM_MFG_2D_PWR_CON,
 386 -               .sram_pdn_bits = GENMASK(11, 8),
 387 -               .sram_pdn_ack_bits = GENMASK(13, 12),
 388 -               .clk_id = {MT8173_CLK_NONE},
 389 -       },
 390 -       [MT8173_POWER_DOMAIN_MFG] = {
 391 -               .name = "mfg",
 392 -               .sta_mask = PWR_STATUS_MFG,
 393 -               .ctl_offs = SPM_MFG_PWR_CON,
 394 -               .sram_pdn_bits = GENMASK(13, 8),
 395 -               .sram_pdn_ack_bits = GENMASK(21, 16),
 396 -               .clk_id = {MT8173_CLK_NONE},
 397 -               .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
 398 -                       MT8173_TOP_AXI_PROT_EN_MFG_M0 |
 399 -                       MT8173_TOP_AXI_PROT_EN_MFG_M1 |
 400 -                       MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
 401 -       },
 402 -};
 403 -
 404 -#define NUM_DOMAINS    ARRAY_SIZE(scp_domain_data)
 405 -
 406 -struct scp;
 407 -
 408 -struct scp_domain {
 409 -       struct generic_pm_domain genpd;
 410 -       struct scp *scp;
 411 -       struct clk *clk[MAX_CLKS];
 412 -       u32 sta_mask;
 413 -       void __iomem *ctl_addr;
 414 -       u32 sram_pdn_bits;
 415 -       u32 sram_pdn_ack_bits;
 416 -       u32 bus_prot_mask;
 417 -       bool active_wakeup;
 418 -};
 419 -
 420 -struct scp {
 421 -       struct scp_domain domains[NUM_DOMAINS];
 422 -       struct genpd_onecell_data pd_data;
 423 -       struct device *dev;
 424 -       void __iomem *base;
 425 -       struct regmap *infracfg;
 426 -};
 427 -
 428  static int scpsys_domain_is_on(struct scp_domain *scpd)
 429  {
 430         struct scp *scp = scpd->scp;
 431 @@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct device *dev)
 432         return scpd->active_wakeup;
 433  }
 434
 435 -static int __init scpsys_probe(struct platform_device *pdev)
 436 +static void init_clks(struct platform_device *pdev, struct clk *clk[CLK_MAX])
 437 +{
 438 +       enum clk_id clk_ids[] = {
 439 +               CLK_MM,
 440 +               CLK_MFG,
 441 +               CLK_VENC,
 442 +               CLK_VENC_LT
 443 +       };
 444 +
 445 +       static const char * const clk_names[] = {
 446 +               "mm",
 447 +               "mfg",
 448 +               "venc",
 449 +               "venc_lt",
 450 +       };
 451 +
 452 +       int i;
 453 +
 454 +       for (i = 0; i < ARRAY_SIZE(clk_ids); i++)
 455 +               clk[clk_ids[i]] = devm_clk_get(&pdev->dev, clk_names[i]);
 456 +}
 457 +
 458 +struct scp *init_scp(struct platform_device *pdev,
 459 +                       const struct scp_domain_data *scp_domain_data, int num)
 460  {
 461         struct genpd_onecell_data *pd_data;
 462         struct resource *res;
 463 -       int i, j, ret;
 464 +       int i, j;
 465         struct scp *scp;
 466 -       struct clk *clk[MT8173_CLK_MAX];
 467 +       struct clk *clk[CLK_MAX];
 468
 469         scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
 470         if (!scp)
 471 -               return -ENOMEM;
 472 +               return ERR_PTR(-ENOMEM);
 473
 474         scp->dev = &pdev->dev;
 475
 476         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 477         scp->base = devm_ioremap_resource(&pdev->dev, res);
 478         if (IS_ERR(scp->base))
 479 -               return PTR_ERR(scp->base);
 480 -
 481 -       pd_data = &scp->pd_data;
 482 -
 483 -       pd_data->domains = devm_kzalloc(&pdev->dev,
 484 -                       sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
 485 -       if (!pd_data->domains)
 486 -               return -ENOMEM;
 487 -
 488 -       clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
 489 -       if (IS_ERR(clk[MT8173_CLK_MM]))
 490 -               return PTR_ERR(clk[MT8173_CLK_MM]);
 491 -
 492 -       clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
 493 -       if (IS_ERR(clk[MT8173_CLK_MFG]))
 494 -               return PTR_ERR(clk[MT8173_CLK_MFG]);
 495 -
 496 -       clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
 497 -       if (IS_ERR(clk[MT8173_CLK_VENC]))
 498 -               return PTR_ERR(clk[MT8173_CLK_VENC]);
 499 -
 500 -       clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
 501 -       if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
 502 -               return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
 503 +               return ERR_CAST(scp->base);
 504
 505         scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 506                         "infracfg");
 507         if (IS_ERR(scp->infracfg)) {
 508                 dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
 509                                 PTR_ERR(scp->infracfg));
 510 -               return PTR_ERR(scp->infracfg);
 511 +               return ERR_CAST(scp->infracfg);
 512         }
 513
 514 -       pd_data->num_domains = NUM_DOMAINS;
 515 +       scp->domains = devm_kzalloc(&pdev->dev,
 516 +                               sizeof(*scp->domains) * num, GFP_KERNEL);
 517 +       if (!scp->domains)
 518 +               return ERR_PTR(-ENOMEM);
 519 +
 520 +       pd_data = &scp->pd_data;
 521 +
 522 +       pd_data->domains = devm_kzalloc(&pdev->dev,
 523 +                       sizeof(*pd_data->domains) * num, GFP_KERNEL);
 524 +       if (!pd_data->domains)
 525 +               return ERR_PTR(-ENOMEM);
 526
 527 -       for (i = 0; i < NUM_DOMAINS; i++) {
 528 +       pd_data->num_domains = num;
 529 +
 530 +       init_clks(pdev, clk);
 531 +
 532 +       for (i = 0; i < num; i++) {
 533                 struct scp_domain *scpd = &scp->domains[i];
 534                 struct generic_pm_domain *genpd = &scpd->genpd;
 535                 const struct scp_domain_data *data = &scp_domain_data[i];
 536
 537 +               for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
 538 +                       struct clk *c = clk[data->clk_id[j]];
 539 +
 540 +                       if (IS_ERR(c)) {
 541 +                               dev_err(&pdev->dev, "%s: clk unavailable\n",
 542 +                                       data->name);
 543 +                               return ERR_CAST(c);
 544 +                       }
 545 +
 546 +                       scpd->clk[j] = c;
 547 +               }
 548 +
 549                 pd_data->domains[i] = genpd;
 550                 scpd->scp = scp;
 551
 552 @@ -464,13 +329,25 @@ static int __init scpsys_probe(struct platform_device *pdev)
 553                 scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
 554                 scpd->bus_prot_mask = data->bus_prot_mask;
 555                 scpd->active_wakeup = data->active_wakeup;
 556 -               for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
 557 -                       scpd->clk[j] = clk[data->clk_id[j]];
 558
 559                 genpd->name = data->name;
 560                 genpd->power_off = scpsys_power_off;
 561                 genpd->power_on = scpsys_power_on;
 562                 genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
 563 +       }
 564 +
 565 +       return scp;
 566 +}
 567 +
 568 +void mtk_register_power_domains(struct platform_device *pdev,
 569 +                               struct scp *scp, int num)
 570 +{
 571 +       struct genpd_onecell_data *pd_data;
 572 +       int i, ret;
 573 +
 574 +       for (i = 0; i < num; i++) {
 575 +               struct scp_domain *scpd = &scp->domains[i];
 576 +               struct generic_pm_domain *genpd = &scpd->genpd;
 577
 578                 /*
 579                  * Initially turn on all domains to make the domains usable
 580 @@ -489,37 +366,9 @@ static int __init scpsys_probe(struct platform_device *pdev)
 581          * valid.
 582          */
 583
 584 -       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
 585 -               pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
 586 -       if (ret && IS_ENABLED(CONFIG_PM))
 587 -               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
 588 -
 589 -       ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
 590 -               pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
 591 -       if (ret && IS_ENABLED(CONFIG_PM))
 592 -               dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
 593 +       pd_data = &scp->pd_data;
 594
 595         ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
 596         if (ret)
 597                 dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
 598 -
 599 -       return 0;
 600  }
 601 -
 602 -static const struct of_device_id of_scpsys_match_tbl[] = {
 603 -       {
 604 -               .compatible = "mediatek,mt8173-scpsys",
 605 -       }, {
 606 -               /* sentinel */
 607 -       }
 608 -};
 609 -
 610 -static struct platform_driver scpsys_drv = {
 611 -       .driver = {
 612 -               .name = "mtk-scpsys",
 613 -               .owner = THIS_MODULE,
 614 -               .of_match_table = of_match_ptr(of_scpsys_match_tbl),
 615 -       },
 616 -};
 617 -
 618 -module_platform_driver_probe(scpsys_drv, scpsys_probe);
 619 diff --git a/drivers/soc/mediatek/mtk-scpsys.h b/drivers/soc/mediatek/mtk-scpsys.h
 620 new file mode 100644
 621 index 0000000..466728d
 622 --- /dev/null
 623 +++ b/drivers/soc/mediatek/mtk-scpsys.h
 624 @@ -0,0 +1,54 @@
 625 +#ifndef __DRV_SOC_MTK_H
 626 +#define __DRV_SOC_MTK_H
 627 +
 628 +enum clk_id {
 629 +       CLK_NONE,
 630 +       CLK_MM,
 631 +       CLK_MFG,
 632 +       CLK_VENC,
 633 +       CLK_VENC_LT,
 634 +       CLK_MAX,
 635 +};
 636 +
 637 +#define MAX_CLKS       2
 638 +
 639 +struct scp_domain_data {
 640 +       const char *name;
 641 +       u32 sta_mask;
 642 +       int ctl_offs;
 643 +       u32 sram_pdn_bits;
 644 +       u32 sram_pdn_ack_bits;
 645 +       u32 bus_prot_mask;
 646 +       enum clk_id clk_id[MAX_CLKS];
 647 +       bool active_wakeup;
 648 +};
 649 +
 650 +struct scp;
 651 +
 652 +struct scp_domain {
 653 +       struct generic_pm_domain genpd;
 654 +       struct scp *scp;
 655 +       struct clk *clk[MAX_CLKS];
 656 +       u32 sta_mask;
 657 +       void __iomem *ctl_addr;
 658 +       u32 sram_pdn_bits;
 659 +       u32 sram_pdn_ack_bits;
 660 +       u32 bus_prot_mask;
 661 +       bool active_wakeup;
 662 +};
 663 +
 664 +struct scp {
 665 +       struct scp_domain *domains;
 666 +       struct genpd_onecell_data pd_data;
 667 +       struct device *dev;
 668 +       void __iomem *base;
 669 +       struct regmap *infracfg;
 670 +};
 671 +
 672 +struct scp *init_scp(struct platform_device *pdev,
 673 +                       const struct scp_domain_data *scp_domain_data, int num);
 674 +
 675 +void mtk_register_power_domains(struct platform_device *pdev,
 676 +                               struct scp *scp, int num);
 677 +
 678 +#endif /* __DRV_SOC_MTK_H */
 679 --
 680 1.7.10.4
 681