target/linux/lantiq/patches-4.4/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch

   1 From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 7 Aug 2014 18:15:36 +0200
   4 Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/phy/Kconfig  |    5 +
   9  drivers/net/phy/Makefile |    1 +
  10  drivers/net/phy/lantiq.c |  231 ++++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 237 insertions(+)
  12  create mode 100644 drivers/net/phy/lantiq.c
  13
  14 --- a/drivers/net/phy/Kconfig
  15 +++ b/drivers/net/phy/Kconfig
  16 @@ -202,6 +202,11 @@ config RTL8306_PHY
  17         tristate "Driver for Realtek RTL8306S switches"
  18         select SWCONFIG
  19
  20 +config LANTIQ_PHY
  21 +       tristate "Driver for Lantiq PHYs"
  22 +       ---help---
  23 +         Supports the 11G and 22E PHYs.
  24 +
  25  config FIXED_PHY
  26         tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
  27         depends on PHYLIB
  28 --- a/drivers/net/phy/Makefile
  29 +++ b/drivers/net/phy/Makefile
  30 @@ -46,6 +46,7 @@ obj-$(CONFIG_DP83848_PHY)     += dp83848.o
  31  obj-$(CONFIG_DP83867_PHY)      += dp83867.o
  32  obj-$(CONFIG_STE10XP)          += ste10Xp.o
  33  obj-$(CONFIG_MICREL_PHY)       += micrel.o
  34 +obj-$(CONFIG_LANTIQ_PHY)        += lantiq.o
  35  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  36  obj-$(CONFIG_MICREL_KS8995MA)  += spi_ks8995.o
  37  obj-$(CONFIG_AT803X_PHY)       += at803x.o
  38 --- /dev/null
  39 +++ b/drivers/net/phy/lantiq.c
  40 @@ -0,0 +1,278 @@
  41 +/*
  42 + *   This program is free software; you can redistribute it and/or modify
  43 + *   it under the terms of the GNU General Public License as published by
  44 + *   the Free Software Foundation; either version 2 of the License, or
  45 + *   (at your option) any later version.
  46 + *
  47 + *   This program is distributed in the hope that it will be useful,
  48 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  49 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  50 + *   GNU General Public License for more details.
  51 + *
  52 + *   You should have received a copy of the GNU General Public License
  53 + *   along with this program; if not, write to the Free Software
  54 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  55 + *
  56 + *   Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  57 + */
  58 +
  59 +#include <linux/module.h>
  60 +#include <linux/phy.h>
  61 +#include <linux/of.h>
  62 +
  63 +#define MII_MMDCTRL            0x0d
  64 +#define MII_MMDDATA            0x0e
  65 +
  66 +#define MII_VR9_11G_IMASK      0x19    /* interrupt mask */
  67 +#define MII_VR9_11G_ISTAT      0x1a    /* interrupt status */
  68 +
  69 +#define INT_VR9_11G_WOL                BIT(15) /* Wake-On-LAN */
  70 +#define INT_VR9_11G_ANE                BIT(11) /* Auto-Neg error */
  71 +#define INT_VR9_11G_ANC                BIT(10) /* Auto-Neg complete */
  72 +#define INT_VR9_11G_ADSC       BIT(5)  /* Link auto-downspeed detect */
  73 +#define INT_VR9_11G_DXMC       BIT(2)  /* Duplex mode change */
  74 +#define INT_VR9_11G_LSPC       BIT(1)  /* Link speed change */
  75 +#define INT_VR9_11G_LSTC       BIT(0)  /* Link state change */
  76 +#define INT_VR9_11G_MASK       (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
  77 +
  78 +#define ADVERTISED_MPD         BIT(10) /* Multi-port device */
  79 +
  80 +#define MMD_DEVAD              0x1f
  81 +#define MMD_ACTYPE_SHIFT       14
  82 +#define MMD_ACTYPE_ADDRESS     (0 << MMD_ACTYPE_SHIFT)
  83 +#define MMD_ACTYPE_DATA                (1 << MMD_ACTYPE_SHIFT)
  84 +#define MMD_ACTYPE_DATA_PI     (2 << MMD_ACTYPE_SHIFT)
  85 +#define MMD_ACTYPE_DATA_PIWR   (3 << MMD_ACTYPE_SHIFT)
  86 +
  87 +static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
  88 +                                               u16 regnum)
  89 +{
  90 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
  91 +       phy_write(phydev, MII_MMDDATA, regnum);
  92 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
  93 +
  94 +       return phy_read(phydev, MII_MMDDATA);
  95 +}
  96 +
  97 +static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
  98 +                                               u16 regnum, u16 val)
  99 +{
 100 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
 101 +       phy_write(phydev, MII_MMDDATA, regnum);
 102 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
 103 +       phy_write(phydev, MII_MMDDATA, val);
 104 +
 105 +       return 0;
 106 +}
 107 +
 108 +#if IS_ENABLED(CONFIG_OF_MDIO)
 109 +static int vr9_gphy_of_reg_init(struct phy_device *phydev)
 110 +{
 111 +       u32 tmp;
 112 +
 113 +       /* store the led values if one was passed by the devicetree */
 114 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledch", &tmp))
 115 +               vr9_gphy_mmd_write(phydev, 0x1e0, tmp);
 116 +
 117 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledcl", &tmp))
 118 +               vr9_gphy_mmd_write(phydev, 0x1e1, tmp);
 119 +
 120 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0h", &tmp))
 121 +               vr9_gphy_mmd_write(phydev, 0x1e2, tmp);
 122 +
 123 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0l", &tmp))
 124 +               vr9_gphy_mmd_write(phydev, 0x1e3, tmp);
 125 +
 126 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1h", &tmp))
 127 +               vr9_gphy_mmd_write(phydev, 0x1e4, tmp);
 128 +
 129 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1l", &tmp))
 130 +               vr9_gphy_mmd_write(phydev, 0x1e5, tmp);
 131 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2h", &tmp))
 132 +               vr9_gphy_mmd_write(phydev, 0x1e6, tmp);
 133 +
 134 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2l", &tmp))
 135 +               vr9_gphy_mmd_write(phydev, 0x1e7, tmp);
 136 +
 137 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3h", &tmp))
 138 +               vr9_gphy_mmd_write(phydev, 0x1e8, tmp);
 139 +
 140 +       if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3l", &tmp))
 141 +               vr9_gphy_mmd_write(phydev, 0x1e9, tmp);
 142 +
 143 +       return 0;
 144 +}
 145 +#else
 146 +static int vr9_gphy_of_reg_init(struct phy_device *phydev)
 147 +{
 148 +       return 0;
 149 +}
 150 +#endif /* CONFIG_OF_MDIO */
 151 +
 152 +static int vr9_gphy_config_init(struct phy_device *phydev)
 153 +{
 154 +       int err;
 155 +
 156 +       dev_dbg(&phydev->dev, "%s\n", __func__);
 157 +
 158 +       /* Mask all interrupts */
 159 +       err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 160 +       if (err)
 161 +               return err;
 162 +
 163 +       /* Clear all pending interrupts */
 164 +       phy_read(phydev, MII_VR9_11G_ISTAT);
 165 +
 166 +       vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5);
 167 +       vr9_gphy_mmd_write(phydev, 0x1e1, 0x67);
 168 +       vr9_gphy_mmd_write(phydev, 0x1e2, 0x42);
 169 +       vr9_gphy_mmd_write(phydev, 0x1e3, 0x10);
 170 +       vr9_gphy_mmd_write(phydev, 0x1e4, 0x70);
 171 +       vr9_gphy_mmd_write(phydev, 0x1e5, 0x03);
 172 +       vr9_gphy_mmd_write(phydev, 0x1e6, 0x20);
 173 +       vr9_gphy_mmd_write(phydev, 0x1e7, 0x00);
 174 +       vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
 175 +       vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
 176 +
 177 +       vr9_gphy_of_reg_init(phydev);
 178 +
 179 +       return 0;
 180 +}
 181 +
 182 +static int vr9_gphy_config_aneg(struct phy_device *phydev)
 183 +{
 184 +       int reg, err;
 185 +
 186 +       /* Advertise as multi-port device */
 187 +       reg = phy_read(phydev, MII_CTRL1000);
 188 +       reg |= ADVERTISED_MPD;
 189 +       err = phy_write(phydev, MII_CTRL1000, reg);
 190 +       if (err)
 191 +               return err;
 192 +
 193 +       return genphy_config_aneg(phydev);
 194 +}
 195 +
 196 +static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
 197 +{
 198 +       int reg;
 199 +
 200 +       /*
 201 +        * Possible IRQ numbers:
 202 +        * - IM3_IRL18 for GPHY0
 203 +        * - IM3_IRL17 for GPHY1
 204 +        *
 205 +        * Due to a silicon bug IRQ lines are not really independent from
 206 +        * each other. Sometimes the two lines are driven at the same time
 207 +        * if only one GPHY core raises the interrupt.
 208 +        */
 209 +
 210 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 211 +
 212 +       return (reg < 0) ? reg : 0;
 213 +}
 214 +
 215 +static int vr9_gphy_did_interrupt(struct phy_device *phydev)
 216 +{
 217 +       int reg;
 218 +
 219 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 220 +
 221 +       return reg > 0;
 222 +}
 223 +
 224 +static int vr9_gphy_config_intr(struct phy_device *phydev)
 225 +{
 226 +       int err;
 227 +
 228 +       if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 229 +               err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
 230 +       else
 231 +               err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 232 +
 233 +       return err;
 234 +}
 235 +
 236 +static struct phy_driver lantiq_phy[] = {
 237 +       {
 238 +               .phy_id         = 0xd565a400,
 239 +               .phy_id_mask    = 0xfffffff8,
 240 +               .name           = "Lantiq XWAY PEF7071",
 241 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 242 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 243 +               .config_init    = vr9_gphy_config_init,
 244 +               .config_aneg    = vr9_gphy_config_aneg,
 245 +               .read_status    = genphy_read_status,
 246 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 247 +               .did_interrupt  = vr9_gphy_did_interrupt,
 248 +               .config_intr    = vr9_gphy_config_intr,
 249 +               .driver         = { .owner = THIS_MODULE },
 250 +       }, {
 251 +               .phy_id         = 0x030260D0,
 252 +               .phy_id_mask    = 0xfffffff0,
 253 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.3",
 254 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 255 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 256 +               .config_init    = vr9_gphy_config_init,
 257 +               .config_aneg    = vr9_gphy_config_aneg,
 258 +               .read_status    = genphy_read_status,
 259 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 260 +               .did_interrupt  = vr9_gphy_did_interrupt,
 261 +               .config_intr    = vr9_gphy_config_intr,
 262 +               .driver         = { .owner = THIS_MODULE },
 263 +       }, {
 264 +               .phy_id         = 0xd565a408,
 265 +               .phy_id_mask    = 0xfffffff8,
 266 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.4",
 267 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 268 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 269 +               .config_init    = vr9_gphy_config_init,
 270 +               .config_aneg    = vr9_gphy_config_aneg,
 271 +               .read_status    = genphy_read_status,
 272 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 273 +               .did_interrupt  = vr9_gphy_did_interrupt,
 274 +               .config_intr    = vr9_gphy_config_intr,
 275 +               .driver         = { .owner = THIS_MODULE },
 276 +       }, {
 277 +               .phy_id         = 0xd565a418,
 278 +               .phy_id_mask    = 0xfffffff8,
 279 +               .name           = "Lantiq XWAY XRX PHY22F v1.4",
 280 +               .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 281 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 282 +               .config_init    = vr9_gphy_config_init,
 283 +               .config_aneg    = vr9_gphy_config_aneg,
 284 +               .read_status    = genphy_read_status,
 285 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 286 +               .did_interrupt  = vr9_gphy_did_interrupt,
 287 +               .config_intr    = vr9_gphy_config_intr,
 288 +               .driver         = { .owner = THIS_MODULE },
 289 +       },
 290 +};
 291 +
 292 +static int __init ltq_phy_init(void)
 293 +{
 294 +       int i;
 295 +
 296 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
 297 +               int err = phy_driver_register(&lantiq_phy[i]);
 298 +               if (err)
 299 +                       pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
 300 +       }
 301 +
 302 +       return 0;
 303 +}
 304 +
 305 +static void __exit ltq_phy_exit(void)
 306 +{
 307 +       int i;
 308 +
 309 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
 310 +               phy_driver_unregister(&lantiq_phy[i]);
 311 +}
 312 +
 313 +module_init(ltq_phy_init);
 314 +module_exit(ltq_phy_exit);
 315 +
 316 +MODULE_DESCRIPTION("Lantiq PHY drivers");
 317 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
 318 +MODULE_LICENSE("GPL");
 319 --- /dev/null
 320 +++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
 321 @@ -0,0 +1,216 @@
 322 +Lanitq PHY binding
 323 +============================================
 324 +
 325 +This devicetree binding controls the lantiq ethernet phys led functionality.
 326 +
 327 +Example:
 328 +       mdio@0 {
 329 +               #address-cells = <1>;
 330 +               #size-cells = <0>;
 331 +               compatible = "lantiq,xrx200-mdio";
 332 +                       phy5: ethernet-phy@5 {
 333 +                       reg = <0x1>;
 334 +                       compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 335 +               };
 336 +               phy11: ethernet-phy@11 {
 337 +                       reg = <0x11>;
 338 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
 339 +                       lantiq,led2h = <0x00>;
 340 +                       lantiq,led2l = <0x03>;
 341 +               };
 342 +               phy12: ethernet-phy@12 {
 343 +                       reg = <0x12>;
 344 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
 345 +                       lantiq,led1h = <0x00>;
 346 +                       lantiq,led1l = <0x03>;
 347 +               };
 348 +               phy13: ethernet-phy@13 {
 349 +                       reg = <0x13>;
 350 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
 351 +                       lantiq,led2h = <0x00>;
 352 +                       lantiq,led2l = <0x03>;
 353 +               };
 354 +               phy14: ethernet-phy@14 {
 355 +                       reg = <0x14>;
 356 +                       compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
 357 +                       lantiq,led1h = <0x00>;
 358 +                       lantiq,led1l = <0x03>;
 359 +               };
 360 +       };
 361 +
 362 +Register Description
 363 +============================================
 364 +
 365 +LEDCH:
 366 +
 367 +Name   Hardware Reset Value
 368 +LEDCH  0x00C5
 369 +
 370 +| 15 |    |    |    |    |    |    |  8 |
 371 +=========================================
 372 +|              RES                     |
 373 +=========================================
 374 +
 375 +|  7 |    |    |    |    |    |    |  0 |
 376 +=========================================
 377 +|   FBF   |   SBF   |RES |     NACS     |
 378 +=========================================
 379 +
 380 +Field  Bits    Type    Description
 381 +FBC    7:6     RW      Fast Blink Frequency
 382 +                       ---
 383 +                       0x0 (00b) F02HZ 2 Hz blinking frequency
 384 +                       0x1 (01b) F04HZ 4 Hz blinking frequency
 385 +                       0x2 (10b) F08HZ 8 Hz blinking frequency
 386 +                       0x3 (11b) F16HZ 16 Hz blinking frequency
 387 +
 388 +SBF    5:4     RW      Slow Blink Frequency
 389 +                       ---
 390 +                       0x0 (00b) F02HZ 2 Hz blinking frequency
 391 +                       0x1 (01b) F04HZ 4 Hz blinking frequency
 392 +                       0x2 (10b) F08HZ 8 Hz blinking frequency
 393 +                       0x3 (11b) F16HZ 16 Hz blinking frequency
 394 +
 395 +NACS   2:0     RW      Inverse of Scan Function
 396 +                       ---
 397 +                       0x0 (000b) NONE No Function
 398 +                       0x1 (001b) LINK Complex function enabled when link is up
 399 +                       0x2 (010b) PDOWN Complex function enabled when device is powered-down
 400 +                       0x3 (011b) EEE Complex function enabled when device is in EEE mode
 401 +                       0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
 402 +                       0x5 (101b) ABIST Complex function enabled when analog self-test is running
 403 +                       0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
 404 +                       0x7 (111b) TEST Complex function enabled when test mode is running
 405 +
 406 +LEDCL:
 407 +
 408 +Name   Hardware Reset Value
 409 +LEDCL  0x0067
 410 +
 411 +| 15 |    |    |    |    |    |    |  8 |
 412 +=========================================
 413 +|              RES                     |
 414 +=========================================
 415 +
 416 +|  7 |    |    |    |    |    |    |  0 |
 417 +=========================================
 418 +|RES |     SCAN     |RES |    CBLINK    |
 419 +=========================================
 420 +
 421 +Field  Bits    Type    Description
 422 +SCAN   6:4     RW      Complex Scan Configuration
 423 +                       ---
 424 +                       000 B NONE No Function
 425 +                       001 B LINK Complex function enabled when link is up
 426 +                       010 B PDOWN Complex function enabled when device is powered-down
 427 +                       011 B EEE Complex function enabled when device is in EEE mode
 428 +                       100 B ANEG Complex function enabled when auto-negotiation is running
 429 +                       101 B ABIST Complex function enabled when analog self-test is running
 430 +                       110 B CDIAG Complex function enabled when cable diagnostics are running
 431 +                       111 B TEST Complex function enabled when test mode is running
 432 +
 433 +CBLINK 2:0     RW      Complex Blinking Configuration
 434 +                       ---
 435 +                       000 B NONE No Function
 436 +                       001 B LINK Complex function enabled when link is up
 437 +                       010 B PDOWN Complex function enabled when device is powered-down
 438 +                       011 B EEE Complex function enabled when device is in EEE mode
 439 +                       100 B ANEG Complex function enabled when auto-negotiation is running
 440 +                       101 B ABIST Complex function enabled when analog self-test is running
 441 +                       110 B CDIAG Complex function enabled when cable diagnostics are running
 442 +                       111 B TEST Complex function enabled when test mode is running
 443 +
 444 +LEDxH:
 445 +
 446 +Name   Hardware Reset Value
 447 +LED0H  0x0070
 448 +LED1H  0x0020
 449 +LED2H  0x0040
 450 +LED3H  0x0040
 451 +
 452 +| 15 |    |    |    |    |    |    |  8 |
 453 +=========================================
 454 +|              RES                     |
 455 +=========================================
 456 +
 457 +|  7 |    |    |    |    |    |    |  0 |
 458 +=========================================
 459 +|        CON        |       BLINKF      |
 460 +=========================================
 461 +
 462 +Field  Bits    Type    Description
 463 +CON    7:4     RW      Constant On Configuration
 464 +                       ---
 465 +                       0x0 (0000b) NONE LED does not light up constantly
 466 +                       0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
 467 +                       0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
 468 +                       0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
 469 +                       0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
 470 +                       0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
 471 +                       0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
 472 +                       0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
 473 +                       0x8 (1000b) PDOWN LED is on when device is powered-down
 474 +                       0x9 (1001b) EEE LED is on when device is in EEE mode
 475 +                       0xA (1010b) ANEG LED is on when auto-negotiation is running
 476 +                       0xB (1011b) ABIST LED is on when analog self-test is running
 477 +                       0xC (1100b) CDIAG LED is on when cable diagnostics are running
 478 +
 479 +BLINKF 3:0     RW      Fast Blinking Configuration
 480 +                       ---
 481 +                       0x0 (0000b) NONE No Blinking
 482 +                       0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
 483 +                       0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
 484 +                       0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
 485 +                       0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
 486 +                       0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
 487 +                       0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
 488 +                       0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
 489 +                       0x8 (1000b) PDOWN Blink when device is powered-down
 490 +                       0x9 (1001b) EEE Blink when device is in EEE mode
 491 +                       0xA (1010b) ANEG Blink when auto-negotiation is running
 492 +                       0xB (1011b) ABIST Blink when analog self-test is running
 493 +                       0xC (1100b) CDIAG Blink when cable diagnostics are running
 494 +
 495 +LEDxL:
 496 +
 497 +Name   Hardware Reset Value
 498 +LED0L  0x0003
 499 +LED1L  0x0000
 500 +LED2L  0x0000
 501 +LED3L  0x0020
 502 +
 503 +| 15 |    |    |    |    |    |    |  8 |
 504 +=========================================
 505 +|              RES                     |
 506 +=========================================
 507 +
 508 +|  7 |    |    |    |    |    |    |  0 |
 509 +=========================================
 510 +|      BLINKS       |       PULSE       |
 511 +=========================================
 512 +
 513 +Field  Bits    Type    Description
 514 +BLINKS 7:4     RW      Slow Blinkin Configuration
 515 +                       ---
 516 +                       0x0 (0000b) NONE No Blinking
 517 +                       0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
 518 +                       0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
 519 +                       0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
 520 +                       0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
 521 +                       0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
 522 +                       0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
 523 +                       0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
 524 +                       0x8 (1000b) PDOWN Blink when device is powered-down
 525 +                       0x9 (1001b) EEE Blink when device is in EEE mode
 526 +                       0xA (1010b) ANEG Blink when auto-negotiation is running
 527 +                       0xB (1011b) ABIST Blink when analog self-test is running
 528 +                       0xC (1100b) CDIAG Blink when cable diagnostics are runningning
 529 +
 530 +PULSE  3:0     RW      Pulsing Configuration
 531 +                       The pulse field is a mask field by which certain events can be combined
 532 +                       ---
 533 +                       0x0 (0000b) NONE No pulsing
 534 +                       0x1 (0001b) TXACT Transmit activity
 535 +                       0x2 (0010b) RXACT Receive activity
 536 +                       0x4 (0100b) COL Collision
 537 +                       0x8 (1000b) RES Reserved