target/linux/lantiq/patches-3.9/0010-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch

   1 From fd69e82feee0966fd61374ea76d6ff36ce42e51c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 29 Jun 2013 19:42:16 +0200
   4 Subject: [PATCH 10/22] NET: MIPS: lantiq: update etop driver for devicetree
   5
   6 ---
   7  drivers/net/ethernet/lantiq_etop.c |  500 +++++++++++++++++++++++++-----------
   8  1 file changed, 354 insertions(+), 146 deletions(-)
   9
  10 --- a/drivers/net/ethernet/lantiq_etop.c
  11 +++ b/drivers/net/ethernet/lantiq_etop.c
  12 @@ -12,7 +12,7 @@
  13   *   along with this program; if not, write to the Free Software
  14   *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15   *
  16 - *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  17 + *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
  18   */
  19
  20  #include <linux/kernel.h>
  21 @@ -36,6 +36,10 @@
  22  #include <linux/io.h>
  23  #include <linux/dma-mapping.h>
  24  #include <linux/module.h>
  25 +#include <linux/clk.h>
  26 +#include <linux/of_net.h>
  27 +#include <linux/of_irq.h>
  28 +#include <linux/of_platform.h>
  29
  30  #include <asm/checksum.h>
  31
  32 @@ -71,25 +75,61 @@
  33  #define ETOP_MII_REVERSE       0xe
  34  #define ETOP_PLEN_UNDER                0x40
  35  #define ETOP_CGEN              0x800
  36 +#define ETOP_CFG_MII0          0x01
  37
  38 -/* use 2 static channels for TX/RX */
  39 -#define LTQ_ETOP_TX_CHANNEL    1
  40 -#define LTQ_ETOP_RX_CHANNEL    6
  41 -#define IS_TX(x)               (x == LTQ_ETOP_TX_CHANNEL)
  42 -#define IS_RX(x)               (x == LTQ_ETOP_RX_CHANNEL)
  43 +#define LTQ_GBIT_MDIO_CTL      0xCC
  44 +#define LTQ_GBIT_MDIO_DATA     0xd0
  45 +#define LTQ_GBIT_GCTL0         0x68
  46 +#define LTQ_GBIT_PMAC_HD_CTL   0x8c
  47 +#define LTQ_GBIT_P0_CTL                0x4
  48 +#define LTQ_GBIT_PMAC_RX_IPG   0xa8
  49 +#define LTQ_GBIT_RGMII_CTL     0x78
  50 +
  51 +#define PMAC_HD_CTL_AS         (1 << 19)
  52 +#define PMAC_HD_CTL_RXSH       (1 << 22)
  53 +
  54 +/* Switch Enable (0=disable, 1=enable) */
  55 +#define GCTL0_SE               0x80000000
  56 +/* Disable MDIO auto polling (0=disable, 1=enable) */
  57 +#define PX_CTL_DMDIO           0x00400000
  58 +
  59 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
  60 +#define MDC_CLOCK_MASK         0xff000000
  61 +#define MDC_CLOCK_OFFSET       24
  62 +
  63 +/* register information for the gbit's MDIO bus */
  64 +#define MDIO_XR9_REQUEST       0x00008000
  65 +#define MDIO_XR9_READ          0x00000800
  66 +#define MDIO_XR9_WRITE         0x00000400
  67 +#define MDIO_XR9_REG_MASK      0x1f
  68 +#define MDIO_XR9_ADDR_MASK     0x1f
  69 +#define MDIO_XR9_RD_MASK       0xffff
  70 +#define MDIO_XR9_REG_OFFSET    0
  71 +#define MDIO_XR9_ADDR_OFFSET   5
  72 +#define MDIO_XR9_WR_OFFSET     16
  73
  74 +#define LTQ_DMA_ETOP   ((of_machine_is_compatible("lantiq,ase")) ? \
  75 +                       (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
  76 +
  77 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
  78  #define ltq_etop_r32(x)                ltq_r32(ltq_etop_membase + (x))
  79  #define ltq_etop_w32(x, y)     ltq_w32(x, ltq_etop_membase + (y))
  80  #define ltq_etop_w32_mask(x, y, z)     \
  81                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
  82
  83 -#define DRV_VERSION    "1.0"
  84 +#define ltq_gbit_r32(x)                ltq_r32(ltq_gbit_membase + (x))
  85 +#define ltq_gbit_w32(x, y)     ltq_w32(x, ltq_gbit_membase + (y))
  86 +#define ltq_gbit_w32_mask(x, y, z)     \
  87 +               ltq_w32_mask(x, y, ltq_gbit_membase + (z))
  88 +
  89 +#define DRV_VERSION    "1.2"
  90
  91  static void __iomem *ltq_etop_membase;
  92 +static void __iomem *ltq_gbit_membase;
  93
  94  struct ltq_etop_chan {
  95 -       int idx;
  96         int tx_free;
  97 +       int irq;
  98         struct net_device *netdev;
  99         struct napi_struct napi;
 100         struct ltq_dma_channel dma;
 101 @@ -99,22 +139,35 @@ struct ltq_etop_chan {
 102  struct ltq_etop_priv {
 103         struct net_device *netdev;
 104         struct platform_device *pdev;
 105 -       struct ltq_eth_data *pldata;
 106         struct resource *res;
 107
 108         struct mii_bus *mii_bus;
 109         struct phy_device *phydev;
 110
 111 -       struct ltq_etop_chan ch[MAX_DMA_CHAN];
 112 -       int tx_free[MAX_DMA_CHAN >> 1];
 113 +       struct ltq_etop_chan txch;
 114 +       struct ltq_etop_chan rxch;
 115 +
 116 +       int tx_irq;
 117 +       int rx_irq;
 118 +
 119 +       const void *mac;
 120 +       int mii_mode;
 121
 122         spinlock_t lock;
 123 +
 124 +       struct clk *clk_ppe;
 125 +       struct clk *clk_switch;
 126 +       struct clk *clk_ephy;
 127 +       struct clk *clk_ephycgu;
 128  };
 129
 130 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
 131 +                               int phy_reg, u16 phy_data);
 132 +
 133  static int
 134  ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 135  {
 136 -       ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 137 +       ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
 138         if (!ch->skb[ch->dma.desc])
 139                 return -ENOMEM;
 140         ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
 141 @@ -149,8 +202,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
 142         spin_unlock_irqrestore(&priv->lock, flags);
 143
 144         skb_put(skb, len);
 145 +       skb->dev = ch->netdev;
 146         skb->protocol = eth_type_trans(skb, ch->netdev);
 147         netif_receive_skb(skb);
 148 +       ch->netdev->stats.rx_packets++;
 149 +       ch->netdev->stats.rx_bytes += len;
 150  }
 151
 152  static int
 153 @@ -158,8 +214,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
 154  {
 155         struct ltq_etop_chan *ch = container_of(napi,
 156                                 struct ltq_etop_chan, napi);
 157 +       struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 158         int rx = 0;
 159         int complete = 0;
 160 +       unsigned long flags;
 161
 162         while ((rx < budget) && !complete) {
 163                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 164 @@ -173,7 +231,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
 165         }
 166         if (complete || !rx) {
 167                 napi_complete(&ch->napi);
 168 +               spin_lock_irqsave(&priv->lock, flags);
 169                 ltq_dma_ack_irq(&ch->dma);
 170 +               spin_unlock_irqrestore(&priv->lock, flags);
 171         }
 172         return rx;
 173  }
 174 @@ -185,12 +245,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
 175                 container_of(napi, struct ltq_etop_chan, napi);
 176         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 177         struct netdev_queue *txq =
 178 -               netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 179 +               netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&priv->lock, flags);
 183         while ((ch->dma.desc_base[ch->tx_free].ctl &
 184                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 185 +               ch->netdev->stats.tx_packets++;
 186 +               ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
 187                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 188                 ch->skb[ch->tx_free] = NULL;
 189                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 190 @@ -203,7 +265,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
 191         if (netif_tx_queue_stopped(txq))
 192                 netif_tx_start_queue(txq);
 193         napi_complete(&ch->napi);
 194 +       spin_lock_irqsave(&priv->lock, flags);
 195         ltq_dma_ack_irq(&ch->dma);
 196 +       spin_unlock_irqrestore(&priv->lock, flags);
 197         return 1;
 198  }
 199
 200 @@ -211,9 +275,10 @@ static irqreturn_t
 201  ltq_etop_dma_irq(int irq, void *_priv)
 202  {
 203         struct ltq_etop_priv *priv = _priv;
 204 -       int ch = irq - LTQ_DMA_CH0_INT;
 205 -
 206 -       napi_schedule(&priv->ch[ch].napi);
 207 +       if (irq == priv->txch.dma.irq)
 208 +               napi_schedule(&priv->txch.napi);
 209 +       else
 210 +               napi_schedule(&priv->rxch.napi);
 211         return IRQ_HANDLED;
 212  }
 213
 214 @@ -225,7 +290,7 @@ ltq_etop_free_channel(struct net_device
 215         ltq_dma_free(&ch->dma);
 216         if (ch->dma.irq)
 217                 free_irq(ch->dma.irq, priv);
 218 -       if (IS_RX(ch->idx)) {
 219 +       if (ch == &priv->txch) {
 220                 int desc;
 221                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 222                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 223 @@ -236,23 +301,59 @@ static void
 224  ltq_etop_hw_exit(struct net_device *dev)
 225  {
 226         struct ltq_etop_priv *priv = netdev_priv(dev);
 227 -       int i;
 228
 229 -       ltq_pmu_disable(PMU_PPE);
 230 -       for (i = 0; i < MAX_DMA_CHAN; i++)
 231 -               if (IS_TX(i) || IS_RX(i))
 232 -                       ltq_etop_free_channel(dev, &priv->ch[i]);
 233 +       clk_disable(priv->clk_ppe);
 234 +
 235 +       if (of_machine_is_compatible("lantiq,ar9"))
 236 +               clk_disable(priv->clk_switch);
 237 +
 238 +       if (of_machine_is_compatible("lantiq,ase")) {
 239 +               clk_disable(priv->clk_ephy);
 240 +               clk_disable(priv->clk_ephycgu);
 241 +       }
 242 +
 243 +       ltq_etop_free_channel(dev, &priv->txch);
 244 +       ltq_etop_free_channel(dev, &priv->rxch);
 245 +}
 246 +
 247 +static void
 248 +ltq_etop_gbit_init(struct net_device *dev)
 249 +{
 250 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 251 +
 252 +       clk_enable(priv->clk_switch);
 253 +
 254 +       ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 255 +       /** Disable MDIO auto polling mode */
 256 +       ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
 257 +       /* set 1522 packet size */
 258 +       ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
 259 +       /* disable pmac & dmac headers */
 260 +       ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
 261 +               LTQ_GBIT_PMAC_HD_CTL);
 262 +       /* Due to traffic halt when burst length 8,
 263 +               replace default IPG value with 0x3B */
 264 +       ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
 265 +       /* set mdc clock to 2.5 MHz */
 266 +       ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
 267 +               LTQ_GBIT_RGMII_CTL);
 268  }
 269
 270  static int
 271  ltq_etop_hw_init(struct net_device *dev)
 272  {
 273         struct ltq_etop_priv *priv = netdev_priv(dev);
 274 -       int i;
 275 +       int mii_mode = priv->mii_mode;
 276 +
 277 +       clk_enable(priv->clk_ppe);
 278
 279 -       ltq_pmu_enable(PMU_PPE);
 280 +       if (of_machine_is_compatible("lantiq,ar9")) {
 281 +               ltq_etop_gbit_init(dev);
 282 +               /* force the etops link to the gbit to MII */
 283 +               mii_mode = PHY_INTERFACE_MODE_MII;
 284 +       }
 285
 286 -       switch (priv->pldata->mii_mode) {
 287 +       switch (mii_mode) {
 288         case PHY_INTERFACE_MODE_RMII:
 289                 ltq_etop_w32_mask(ETOP_MII_MASK,
 290                         ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 291 @@ -264,39 +365,68 @@ ltq_etop_hw_init(struct net_device *dev)
 292                 break;
 293
 294         default:
 295 +               if (of_machine_is_compatible("lantiq,ase")) {
 296 +                       clk_enable(priv->clk_ephy);
 297 +                       /* disable external MII */
 298 +                       ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 299 +                       /* enable clock for internal PHY */
 300 +                       clk_enable(priv->clk_ephycgu);
 301 +                       /* we need to write this magic to the internal phy to
 302 +                          make it work */
 303 +                       ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
 304 +                       pr_info("Selected EPHY mode\n");
 305 +                       break;
 306 +               }
 307                 netdev_err(dev, "unknown mii mode %d\n",
 308 -                       priv->pldata->mii_mode);
 309 +                       mii_mode);
 310                 return -ENOTSUPP;
 311         }
 312
 313         /* enable crc generation */
 314         ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 315
 316 +       return 0;
 317 +}
 318 +
 319 +static int
 320 +ltq_etop_dma_init(struct net_device *dev)
 321 +{
 322 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 323 +       int tx = priv->tx_irq - LTQ_DMA_ETOP;
 324 +       int rx = priv->rx_irq - LTQ_DMA_ETOP;
 325 +       int err;
 326 +
 327         ltq_dma_init_port(DMA_PORT_ETOP);
 328
 329 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 330 -               int irq = LTQ_DMA_CH0_INT + i;
 331 -               struct ltq_etop_chan *ch = &priv->ch[i];
 332 -
 333 -               ch->idx = ch->dma.nr = i;
 334 -
 335 -               if (IS_TX(i)) {
 336 -                       ltq_dma_alloc_tx(&ch->dma);
 337 -                       request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
 338 -                               "etop_tx", priv);
 339 -               } else if (IS_RX(i)) {
 340 -                       ltq_dma_alloc_rx(&ch->dma);
 341 -                       for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 342 -                                       ch->dma.desc++)
 343 -                               if (ltq_etop_alloc_skb(ch))
 344 -                                       return -ENOMEM;
 345 -                       ch->dma.desc = 0;
 346 -                       request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
 347 -                               "etop_rx", priv);
 348 +       priv->txch.dma.nr = tx;
 349 +       ltq_dma_alloc_tx(&priv->txch.dma);
 350 +       err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
 351 +               "eth_tx", priv);
 352 +       if (err) {
 353 +               netdev_err(dev, "failed to allocate tx irq\n");
 354 +               goto err_out;
 355 +       }
 356 +       priv->txch.dma.irq = priv->tx_irq;
 357 +
 358 +       priv->rxch.dma.nr = rx;
 359 +       ltq_dma_alloc_rx(&priv->rxch.dma);
 360 +       for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
 361 +                       priv->rxch.dma.desc++) {
 362 +               if (ltq_etop_alloc_skb(&priv->rxch)) {
 363 +                       netdev_err(dev, "failed to allocate skbs\n");
 364 +                       err = -ENOMEM;
 365 +                       goto err_out;
 366                 }
 367 -               ch->dma.irq = irq;
 368         }
 369 -       return 0;
 370 +       priv->rxch.dma.desc = 0;
 371 +       err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
 372 +               "eth_rx", priv);
 373 +       if (err)
 374 +               netdev_err(dev, "failed to allocate rx irq\n");
 375 +       else
 376 +               priv->rxch.dma.irq = priv->rx_irq;
 377 +err_out:
 378 +       return err;
 379  }
 380
 381  static void
 382 @@ -312,7 +442,10 @@ ltq_etop_get_settings(struct net_device
 383  {
 384         struct ltq_etop_priv *priv = netdev_priv(dev);
 385
 386 -       return phy_ethtool_gset(priv->phydev, cmd);
 387 +       if (priv->phydev)
 388 +               return phy_ethtool_gset(priv->phydev, cmd);
 389 +       else
 390 +               return 0;
 391  }
 392
 393  static int
 394 @@ -320,7 +453,10 @@ ltq_etop_set_settings(struct net_device
 395  {
 396         struct ltq_etop_priv *priv = netdev_priv(dev);
 397
 398 -       return phy_ethtool_sset(priv->phydev, cmd);
 399 +       if (priv->phydev)
 400 +               return phy_ethtool_sset(priv->phydev, cmd);
 401 +       else
 402 +               return 0;
 403  }
 404
 405  static int
 406 @@ -328,7 +464,10 @@ ltq_etop_nway_reset(struct net_device *d
 407  {
 408         struct ltq_etop_priv *priv = netdev_priv(dev);
 409
 410 -       return phy_start_aneg(priv->phydev);
 411 +       if (priv->phydev)
 412 +               return phy_start_aneg(priv->phydev);
 413 +       else
 414 +               return 0;
 415  }
 416
 417  static const struct ethtool_ops ltq_etop_ethtool_ops = {
 418 @@ -339,6 +478,39 @@ static const struct ethtool_ops ltq_etop
 419  };
 420
 421  static int
 422 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
 423 +               int phy_reg, u16 phy_data)
 424 +{
 425 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
 426 +               (phy_data << MDIO_XR9_WR_OFFSET) |
 427 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 428 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 429 +
 430 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 431 +               ;
 432 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 433 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 434 +               ;
 435 +       return 0;
 436 +}
 437 +
 438 +static int
 439 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
 440 +{
 441 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
 442 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 443 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 444 +
 445 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 446 +               ;
 447 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 448 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 449 +               ;
 450 +       val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
 451 +       return val;
 452 +}
 453 +
 454 +static int
 455  ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 456  {
 457         u32 val = MDIO_REQUEST |
 458 @@ -379,14 +551,18 @@ ltq_etop_mdio_probe(struct net_device *d
 459  {
 460         struct ltq_etop_priv *priv = netdev_priv(dev);
 461         struct phy_device *phydev = NULL;
 462 -       int phy_addr;
 463 +       u32 phy_supported =  (SUPPORTED_10baseT_Half
 464 +                       | SUPPORTED_10baseT_Full
 465 +                       | SUPPORTED_100baseT_Half
 466 +                       | SUPPORTED_100baseT_Full
 467 +                       | SUPPORTED_Autoneg
 468 +                       | SUPPORTED_MII
 469 +                       | SUPPORTED_TP);
 470
 471 -       for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 472 -               if (priv->mii_bus->phy_map[phy_addr]) {
 473 -                       phydev = priv->mii_bus->phy_map[phy_addr];
 474 -                       break;
 475 -               }
 476 -       }
 477 +       if (of_machine_is_compatible("lantiq,ase"))
 478 +               phydev = priv->mii_bus->phy_map[8];
 479 +       else
 480 +               phydev = priv->mii_bus->phy_map[0];
 481
 482         if (!phydev) {
 483                 netdev_err(dev, "no PHY found\n");
 484 @@ -394,21 +570,18 @@ ltq_etop_mdio_probe(struct net_device *d
 485         }
 486
 487         phydev = phy_connect(dev, dev_name(&phydev->dev),
 488 -                            &ltq_etop_mdio_link, priv->pldata->mii_mode);
 489 +                       &ltq_etop_mdio_link, priv->mii_mode);
 490
 491         if (IS_ERR(phydev)) {
 492                 netdev_err(dev, "Could not attach to PHY\n");
 493                 return PTR_ERR(phydev);
 494         }
 495
 496 -       phydev->supported &= (SUPPORTED_10baseT_Half
 497 -                             | SUPPORTED_10baseT_Full
 498 -                             | SUPPORTED_100baseT_Half
 499 -                             | SUPPORTED_100baseT_Full
 500 -                             | SUPPORTED_Autoneg
 501 -                             | SUPPORTED_MII
 502 -                             | SUPPORTED_TP);
 503 +       if (of_machine_is_compatible("lantiq,ar9"))
 504 +               phy_supported |= SUPPORTED_1000baseT_Half
 505 +                       | SUPPORTED_1000baseT_Full;
 506
 507 +       phydev->supported &= phy_supported;
 508         phydev->advertising = phydev->supported;
 509         priv->phydev = phydev;
 510         pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
 511 @@ -433,8 +606,13 @@ ltq_etop_mdio_init(struct net_device *de
 512         }
 513
 514         priv->mii_bus->priv = dev;
 515 -       priv->mii_bus->read = ltq_etop_mdio_rd;
 516 -       priv->mii_bus->write = ltq_etop_mdio_wr;
 517 +       if (of_machine_is_compatible("lantiq,ar9")) {
 518 +               priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
 519 +               priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
 520 +       } else {
 521 +               priv->mii_bus->read = ltq_etop_mdio_rd;
 522 +               priv->mii_bus->write = ltq_etop_mdio_wr;
 523 +       }
 524         priv->mii_bus->name = "ltq_mii";
 525         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 526                 priv->pdev->name, priv->pdev->id);
 527 @@ -483,17 +661,19 @@ static int
 528  ltq_etop_open(struct net_device *dev)
 529  {
 530         struct ltq_etop_priv *priv = netdev_priv(dev);
 531 -       int i;
 532 +       unsigned long flags;
 533
 534 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 535 -               struct ltq_etop_chan *ch = &priv->ch[i];
 536 +       napi_enable(&priv->txch.napi);
 537 +       napi_enable(&priv->rxch.napi);
 538 +
 539 +       spin_lock_irqsave(&priv->lock, flags);
 540 +       ltq_dma_open(&priv->txch.dma);
 541 +       ltq_dma_open(&priv->rxch.dma);
 542 +       spin_unlock_irqrestore(&priv->lock, flags);
 543 +
 544 +       if (priv->phydev)
 545 +               phy_start(priv->phydev);
 546
 547 -               if (!IS_TX(i) && (!IS_RX(i)))
 548 -                       continue;
 549 -               ltq_dma_open(&ch->dma);
 550 -               napi_enable(&ch->napi);
 551 -       }
 552 -       phy_start(priv->phydev);
 553         netif_tx_start_all_queues(dev);
 554         return 0;
 555  }
 556 @@ -502,18 +682,19 @@ static int
 557  ltq_etop_stop(struct net_device *dev)
 558  {
 559         struct ltq_etop_priv *priv = netdev_priv(dev);
 560 -       int i;
 561 +       unsigned long flags;
 562
 563         netif_tx_stop_all_queues(dev);
 564 -       phy_stop(priv->phydev);
 565 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 566 -               struct ltq_etop_chan *ch = &priv->ch[i];
 567 -
 568 -               if (!IS_RX(i) && !IS_TX(i))
 569 -                       continue;
 570 -               napi_disable(&ch->napi);
 571 -               ltq_dma_close(&ch->dma);
 572 -       }
 573 +       if (priv->phydev)
 574 +               phy_stop(priv->phydev);
 575 +       napi_disable(&priv->txch.napi);
 576 +       napi_disable(&priv->rxch.napi);
 577 +
 578 +       spin_lock_irqsave(&priv->lock, flags);
 579 +       ltq_dma_close(&priv->txch.dma);
 580 +       ltq_dma_close(&priv->rxch.dma);
 581 +       spin_unlock_irqrestore(&priv->lock, flags);
 582 +
 583         return 0;
 584  }
 585
 586 @@ -523,16 +704,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
 587         int queue = skb_get_queue_mapping(skb);
 588         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 589         struct ltq_etop_priv *priv = netdev_priv(dev);
 590 -       struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 591 -       struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 592 -       int len;
 593 +       struct ltq_dma_desc *desc =
 594 +               &priv->txch.dma.desc_base[priv->txch.dma.desc];
 595         unsigned long flags;
 596         u32 byte_offset;
 597 +       int len;
 598
 599         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 600
 601 -       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 602 -               dev_kfree_skb_any(skb);
 603 +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
 604 +                       priv->txch.skb[priv->txch.dma.desc]) {
 605                 netdev_err(dev, "tx ring full\n");
 606                 netif_tx_stop_queue(txq);
 607                 return NETDEV_TX_BUSY;
 608 @@ -540,7 +721,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
 609
 610         /* dma needs to start on a 16 byte aligned address */
 611         byte_offset = CPHYSADDR(skb->data) % 16;
 612 -       ch->skb[ch->dma.desc] = skb;
 613 +       priv->txch.skb[priv->txch.dma.desc] = skb;
 614
 615         dev->trans_start = jiffies;
 616
 617 @@ -550,11 +731,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
 618         wmb();
 619         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 620                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 621 -       ch->dma.desc++;
 622 -       ch->dma.desc %= LTQ_DESC_NUM;
 623 +       priv->txch.dma.desc++;
 624 +       priv->txch.dma.desc %= LTQ_DESC_NUM;
 625         spin_unlock_irqrestore(&priv->lock, flags);
 626
 627 -       if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 628 +       if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
 629                 netif_tx_stop_queue(txq);
 630
 631         return NETDEV_TX_OK;
 632 @@ -633,34 +814,33 @@ ltq_etop_init(struct net_device *dev)
 633         struct ltq_etop_priv *priv = netdev_priv(dev);
 634         struct sockaddr mac;
 635         int err;
 636 -       bool random_mac = false;
 637
 638         ether_setup(dev);
 639         dev->watchdog_timeo = 10 * HZ;
 640         err = ltq_etop_hw_init(dev);
 641         if (err)
 642                 goto err_hw;
 643 +       err = ltq_etop_dma_init(dev);
 644 +       if (err)
 645 +               goto err_hw;
 646 +
 647         ltq_etop_change_mtu(dev, 1500);
 648
 649 -       memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 650 +       if (priv->mac)
 651 +               memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
 652         if (!is_valid_ether_addr(mac.sa_data)) {
 653                 pr_warn("etop: invalid MAC, using random\n");
 654 -               eth_random_addr(mac.sa_data);
 655 -               random_mac = true;
 656 +               random_ether_addr(mac.sa_data);
 657         }
 658
 659         err = ltq_etop_set_mac_address(dev, &mac);
 660         if (err)
 661                 goto err_netdev;
 662 -
 663 -       /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
 664 -       if (random_mac)
 665 -               dev->addr_assign_type = NET_ADDR_RANDOM;
 666 -
 667         ltq_etop_set_multicast_list(dev);
 668 -       err = ltq_etop_mdio_init(dev);
 669 -       if (err)
 670 -               goto err_netdev;
 671 +       if (!ltq_etop_mdio_init(dev))
 672 +               dev->ethtool_ops = &ltq_etop_ethtool_ops;
 673 +       else
 674 +               pr_warn("etop: mdio probe failed\n");;
 675         return 0;
 676
 677  err_netdev:
 678 @@ -680,6 +860,9 @@ ltq_etop_tx_timeout(struct net_device *d
 679         err = ltq_etop_hw_init(dev);
 680         if (err)
 681                 goto err_hw;
 682 +       err = ltq_etop_dma_init(dev);
 683 +       if (err)
 684 +               goto err_hw;
 685         dev->trans_start = jiffies;
 686         netif_wake_queue(dev);
 687         return;
 688 @@ -703,14 +886,18 @@ static const struct net_device_ops ltq_e
 689         .ndo_tx_timeout = ltq_etop_tx_timeout,
 690  };
 691
 692 -static int __init
 693 -ltq_etop_probe(struct platform_device *pdev)
 694 +static int ltq_etop_probe(struct platform_device *pdev)
 695  {
 696         struct net_device *dev;
 697         struct ltq_etop_priv *priv;
 698 -       struct resource *res;
 699 +       struct resource *res, *gbit_res, irqres[2];
 700         int err;
 701 -       int i;
 702 +
 703 +       err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
 704 +       if (err != 2) {
 705 +               dev_err(&pdev->dev, "failed to get etop irqs\n");
 706 +               return -EINVAL;
 707 +       }
 708
 709         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 710         if (!res) {
 711 @@ -736,30 +923,60 @@ ltq_etop_probe(struct platform_device *p
 712                 goto err_out;
 713         }
 714
 715 -       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 716 -       if (!dev) {
 717 -               err = -ENOMEM;
 718 -               goto err_out;
 719 +       if (of_machine_is_compatible("lantiq,ar9")) {
 720 +               gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 721 +               if (!gbit_res) {
 722 +                       dev_err(&pdev->dev, "failed to get gbit resource\n");
 723 +                       err = -ENOENT;
 724 +                       goto err_out;
 725 +               }
 726 +               ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
 727 +                       gbit_res->start, resource_size(gbit_res));
 728 +               if (!ltq_gbit_membase) {
 729 +                       dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
 730 +                               pdev->id);
 731 +                       err = -ENOMEM;
 732 +                       goto err_out;
 733 +               }
 734         }
 735 +
 736 +       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 737         strcpy(dev->name, "eth%d");
 738         dev->netdev_ops = &ltq_eth_netdev_ops;
 739 -       dev->ethtool_ops = &ltq_etop_ethtool_ops;
 740         priv = netdev_priv(dev);
 741         priv->res = res;
 742         priv->pdev = pdev;
 743 -       priv->pldata = dev_get_platdata(&pdev->dev);
 744         priv->netdev = dev;
 745 +       priv->tx_irq = irqres[0].start;
 746 +       priv->rx_irq = irqres[1].start;
 747 +       priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
 748 +       priv->mac = ltq_get_eth_mac();
 749 +       if (!priv->mac)
 750 +               priv->mac = of_get_mac_address(pdev->dev.of_node);
 751 +
 752 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 753 +       if (IS_ERR(priv->clk_ppe))
 754 +               return PTR_ERR(priv->clk_ppe);
 755 +       if (of_machine_is_compatible("lantiq,ar9")) {
 756 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 757 +               if (IS_ERR(priv->clk_switch))
 758 +                       return PTR_ERR(priv->clk_switch);
 759 +       }
 760 +       if (of_machine_is_compatible("lantiq,ase")) {
 761 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 762 +               if (IS_ERR(priv->clk_ephy))
 763 +                       return PTR_ERR(priv->clk_ephy);
 764 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 765 +               if (IS_ERR(priv->clk_ephycgu))
 766 +                       return PTR_ERR(priv->clk_ephycgu);
 767 +       }
 768 +
 769         spin_lock_init(&priv->lock);
 770
 771 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 772 -               if (IS_TX(i))
 773 -                       netif_napi_add(dev, &priv->ch[i].napi,
 774 -                               ltq_etop_poll_tx, 8);
 775 -               else if (IS_RX(i))
 776 -                       netif_napi_add(dev, &priv->ch[i].napi,
 777 -                               ltq_etop_poll_rx, 32);
 778 -               priv->ch[i].netdev = dev;
 779 -       }
 780 +       netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
 781 +       netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
 782 +       priv->txch.netdev = dev;
 783 +       priv->rxch.netdev = dev;
 784
 785         err = register_netdev(dev);
 786         if (err)
 787 @@ -788,32 +1005,23 @@ ltq_etop_remove(struct platform_device *
 788         return 0;
 789  }
 790
 791 +static const struct of_device_id ltq_etop_match[] = {
 792 +       { .compatible = "lantiq,etop-xway" },
 793 +       {},
 794 +};
 795 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
 796 +
 797  static struct platform_driver ltq_mii_driver = {
 798 +       .probe = ltq_etop_probe,
 799         .remove = ltq_etop_remove,
 800         .driver = {
 801                 .name = "ltq_etop",
 802                 .owner = THIS_MODULE,
 803 +               .of_match_table = ltq_etop_match,
 804         },
 805  };
 806
 807 -int __init
 808 -init_ltq_etop(void)
 809 -{
 810 -       int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 811 -
 812 -       if (ret)
 813 -               pr_err("ltq_etop: Error registering platform driver!");
 814 -       return ret;
 815 -}
 816 -
 817 -static void __exit
 818 -exit_ltq_etop(void)
 819 -{
 820 -       platform_driver_unregister(&ltq_mii_driver);
 821 -}
 822 -
 823 -module_init(init_ltq_etop);
 824 -module_exit(exit_ltq_etop);
 825 +module_platform_driver(ltq_mii_driver);
 826
 827  MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 828  MODULE_DESCRIPTION("Lantiq SoC ETOP");