target/linux/lantiq/patches-3.7/0301-gptu.patch

   1 --- /dev/null
   2 +++ b/arch/mips/lantiq/xway/timer.c
   3 @@ -0,0 +1,845 @@
   4 +#ifndef CONFIG_SOC_AMAZON_SE
   5 +
   6 +#include <linux/kernel.h>
   7 +#include <linux/module.h>
   8 +#include <linux/version.h>
   9 +#include <linux/types.h>
  10 +#include <linux/fs.h>
  11 +#include <linux/miscdevice.h>
  12 +#include <linux/init.h>
  13 +#include <linux/uaccess.h>
  14 +#include <linux/unistd.h>
  15 +#include <linux/errno.h>
  16 +#include <linux/interrupt.h>
  17 +#include <linux/sched.h>
  18 +
  19 +#include <asm/irq.h>
  20 +#include <asm/div64.h>
  21 +#include "../clk.h"
  22 +
  23 +#include <lantiq_soc.h>
  24 +#include <lantiq_irq.h>
  25 +#include <lantiq_timer.h>
  26 +
  27 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
  28 +
  29 +#ifdef TIMER1A
  30 +#define FIRST_TIMER                    TIMER1A
  31 +#else
  32 +#define FIRST_TIMER                    2
  33 +#endif
  34 +
  35 +/*
  36 + *  GPTC divider is set or not.
  37 + */
  38 +#define GPTU_CLC_RMC_IS_SET            0
  39 +
  40 +/*
  41 + *  Timer Interrupt (IRQ)
  42 + */
  43 +/*  Must be adjusted when ICU driver is available */
  44 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
  45 +
  46 +/*
  47 + *  Bits Operation
  48 + */
  49 +#define GET_BITS(x, msb, lsb)          \
  50 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  51 +#define SET_BITS(x, msb, lsb, value)   \
  52 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
  53 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  54 +
  55 +/*
  56 + *  GPTU Register Mapping
  57 + */
  58 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
  59 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
  60 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
  61 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  62 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  63 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  64 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  65 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
  66 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
  67 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
  68 +
  69 +/*
  70 + *  Clock Control Register
  71 + */
  72 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
  73 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
  74 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
  75 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
  76 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
  77 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
  78 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
  79 +
  80 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
  81 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
  82 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
  83 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
  84 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
  85 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
  86 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
  87 +
  88 +/*
  89 + *  ID Register
  90 + */
  91 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
  92 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
  93 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
  94 +
  95 +/*
  96 + *  Control Register of Timer/Counter nX
  97 + *    n is the index of block (1 based index)
  98 + *    X is either A or B
  99 + */
 100 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 101 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 102 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 103 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 104 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 105 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 106 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 107 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 108 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 109 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 110 +
 111 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 112 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 113 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 114 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 115 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 116 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 117 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 118 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 119 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 120 +
 121 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 122 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 123 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 124 +
 125 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 126 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 127 +
 128 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 129 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 130 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 131 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 132 +#define TIMER_FLAG_NONE_EDGE           0x0000
 133 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 134 +#define TIMER_FLAG_REAL                        0x0000
 135 +#define TIMER_FLAG_INVERT              0x0040
 136 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 137 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 138 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 139 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 140 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 141 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 142 +
 143 +struct timer_dev_timer {
 144 +       unsigned int f_irq_on;
 145 +       unsigned int irq;
 146 +       unsigned int flag;
 147 +       unsigned long arg1;
 148 +       unsigned long arg2;
 149 +};
 150 +
 151 +struct timer_dev {
 152 +       struct mutex gptu_mutex;
 153 +       unsigned int number_of_timers;
 154 +       unsigned int occupation;
 155 +       unsigned int f_gptu_on;
 156 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 157 +};
 158 +
 159 +
 160 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 161 +       struct clk *clk = clk_get_fpi();
 162 +       return clk_get_rate(clk);
 163 +}
 164 +
 165 +
 166 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 167 +static int gptu_open(struct inode *, struct file *);
 168 +static int gptu_release(struct inode *, struct file *);
 169 +
 170 +static struct file_operations gptu_fops = {
 171 +       .owner = THIS_MODULE,
 172 +       .unlocked_ioctl = gptu_ioctl,
 173 +       .open = gptu_open,
 174 +       .release = gptu_release
 175 +};
 176 +
 177 +static struct miscdevice gptu_miscdev = {
 178 +       .minor = MISC_DYNAMIC_MINOR,
 179 +       .name = "gptu",
 180 +       .fops = &gptu_fops,
 181 +};
 182 +
 183 +static struct timer_dev timer_dev;
 184 +
 185 +static irqreturn_t timer_irq_handler(int irq, void *p)
 186 +{
 187 +       unsigned int timer;
 188 +       unsigned int flag;
 189 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 190 +
 191 +       timer = irq - TIMER_INTERRUPT;
 192 +       if (timer < timer_dev.number_of_timers
 193 +               && dev_timer == &timer_dev.timer[timer]) {
 194 +               /*  Clear interrupt.    */
 195 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 196 +
 197 +               /*  Call user hanler or signal. */
 198 +               flag = dev_timer->flag;
 199 +               if (!(timer & 0x01)
 200 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 201 +                       /* 16-bit timer or timer A of 32-bit timer  */
 202 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 203 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 204 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 205 +                               if (dev_timer->arg1)
 206 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 207 +                               break;
 208 +                       case TIMER_FLAG_SIGNAL:
 209 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 210 +                               break;
 211 +                       }
 212 +               }
 213 +       }
 214 +       return IRQ_HANDLED;
 215 +}
 216 +
 217 +static inline void lq_enable_gptu(void)
 218 +{
 219 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 220 +       clk_enable(clk);
 221 +
 222 +       //ltq_pmu_enable(PMU_GPT);
 223 +
 224 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 225 +       *LQ_GPTU_CLC =
 226 +               GPTU_CLC_SMC_SET(0x00) |
 227 +               GPTU_CLC_RMC_SET(0x01) |
 228 +               GPTU_CLC_FSOE_SET(0) |
 229 +               GPTU_CLC_SBWE_SET(1) |
 230 +               GPTU_CLC_EDIS_SET(0) |
 231 +               GPTU_CLC_SPEN_SET(0) |
 232 +               GPTU_CLC_DISR_SET(0);
 233 +}
 234 +
 235 +static inline void lq_disable_gptu(void)
 236 +{
 237 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 238 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 239 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 240 +
 241 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 242 +       *LQ_GPTU_CLC =
 243 +               GPTU_CLC_SMC_SET(0x00) |
 244 +               GPTU_CLC_RMC_SET(0x00) |
 245 +               GPTU_CLC_FSOE_SET(0) |
 246 +               GPTU_CLC_SBWE_SET(0) |
 247 +               GPTU_CLC_EDIS_SET(0) |
 248 +               GPTU_CLC_SPEN_SET(0) |
 249 +               GPTU_CLC_DISR_SET(1);
 250 +
 251 +       clk_enable(clk);
 252 +}
 253 +
 254 +int lq_request_timer(unsigned int timer, unsigned int flag,
 255 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 256 +{
 257 +       int ret = 0;
 258 +       unsigned int con_reg, irnen_reg;
 259 +       int n, X;
 260 +
 261 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 262 +               return -EINVAL;
 263 +
 264 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 265 +               timer, flag, value);
 266 +
 267 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 268 +               value &= 0xFFFF;
 269 +       else
 270 +               timer &= ~0x01;
 271 +
 272 +       mutex_lock(&timer_dev.gptu_mutex);
 273 +
 274 +       /*
 275 +        *  Allocate timer.
 276 +        */
 277 +       if (timer < FIRST_TIMER) {
 278 +               unsigned int mask;
 279 +               unsigned int shift;
 280 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 281 +               unsigned int offset = TIMER2A;
 282 +
 283 +               /*
 284 +                *  Pick up a free timer.
 285 +                */
 286 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 287 +                       mask = 1 << offset;
 288 +                       shift = 1;
 289 +               } else {
 290 +                       mask = 3 << offset;
 291 +                       shift = 2;
 292 +               }
 293 +               for (timer = offset;
 294 +                    timer < offset + timer_dev.number_of_timers;
 295 +                    timer += shift, mask <<= shift)
 296 +                       if (!(timer_dev.occupation & mask)) {
 297 +                               timer_dev.occupation |= mask;
 298 +                               break;
 299 +                       }
 300 +               if (timer >= offset + timer_dev.number_of_timers) {
 301 +                       printk("failed![%d]\n", __LINE__);
 302 +                       mutex_unlock(&timer_dev.gptu_mutex);
 303 +                       return -EINVAL;
 304 +               } else
 305 +                       ret = timer;
 306 +       } else {
 307 +               register unsigned int mask;
 308 +
 309 +               /*
 310 +                *  Check if the requested timer is free.
 311 +                */
 312 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 313 +               if ((timer_dev.occupation & mask)) {
 314 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 315 +                               __LINE__, mask, timer_dev.occupation);
 316 +                       mutex_unlock(&timer_dev.gptu_mutex);
 317 +                       return -EBUSY;
 318 +               } else {
 319 +                       timer_dev.occupation |= mask;
 320 +                       ret = 0;
 321 +               }
 322 +       }
 323 +
 324 +       /*
 325 +        *  Prepare control register value.
 326 +        */
 327 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 328 +       default:
 329 +       case TIMER_FLAG_NONE_EDGE:
 330 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 331 +               break;
 332 +       case TIMER_FLAG_RISE_EDGE:
 333 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 334 +               break;
 335 +       case TIMER_FLAG_FALL_EDGE:
 336 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 337 +               break;
 338 +       case TIMER_FLAG_ANY_EDGE:
 339 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 340 +               break;
 341 +       }
 342 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 343 +               con_reg |=
 344 +                       TIMER_FLAG_MASK_SRC(flag) ==
 345 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 346 +                       GPTU_CON_SRC_EXT_SET(0);
 347 +       else
 348 +               con_reg |=
 349 +                       TIMER_FLAG_MASK_SRC(flag) ==
 350 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 351 +                       GPTU_CON_SRC_EG_SET(0);
 352 +       con_reg |=
 353 +               TIMER_FLAG_MASK_SYNC(flag) ==
 354 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 355 +               GPTU_CON_SYNC_SET(1);
 356 +       con_reg |=
 357 +               TIMER_FLAG_MASK_INVERT(flag) ==
 358 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 359 +       con_reg |=
 360 +               TIMER_FLAG_MASK_SIZE(flag) ==
 361 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 362 +               GPTU_CON_EXT_SET(1);
 363 +       con_reg |=
 364 +               TIMER_FLAG_MASK_STOP(flag) ==
 365 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 366 +       con_reg |=
 367 +               TIMER_FLAG_MASK_TYPE(flag) ==
 368 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 369 +               GPTU_CON_CNT_SET(1);
 370 +       con_reg |=
 371 +               TIMER_FLAG_MASK_DIR(flag) ==
 372 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 373 +
 374 +       /*
 375 +        *  Fill up running data.
 376 +        */
 377 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 378 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 379 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 380 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 381 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 382 +
 383 +       /*
 384 +        *  Enable GPTU module.
 385 +        */
 386 +       if (!timer_dev.f_gptu_on) {
 387 +               lq_enable_gptu();
 388 +               timer_dev.f_gptu_on = 1;
 389 +       }
 390 +
 391 +       /*
 392 +        *  Enable IRQ.
 393 +        */
 394 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 395 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 396 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 397 +                               (unsigned long) find_task_by_vpid((int) arg1);
 398 +
 399 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 400 +
 401 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 402 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 403 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 404 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 405 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 406 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 407 +               }
 408 +       } else
 409 +               irnen_reg = 0;
 410 +
 411 +       /*
 412 +        *  Write config register, reload value and enable interrupt.
 413 +        */
 414 +       n = timer >> 1;
 415 +       X = timer & 0x01;
 416 +       *LQ_GPTU_CON(n, X) = con_reg;
 417 +       *LQ_GPTU_RELOAD(n, X) = value;
 418 +       /* printk("reload value = %d\n", (u32)value); */
 419 +       *LQ_GPTU_IRNEN |= irnen_reg;
 420 +
 421 +       mutex_unlock(&timer_dev.gptu_mutex);
 422 +       printk("successful!\n");
 423 +       return ret;
 424 +}
 425 +EXPORT_SYMBOL(lq_request_timer);
 426 +
 427 +int lq_free_timer(unsigned int timer)
 428 +{
 429 +       unsigned int flag;
 430 +       unsigned int mask;
 431 +       int n, X;
 432 +
 433 +       if (!timer_dev.f_gptu_on)
 434 +               return -EINVAL;
 435 +
 436 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 437 +               return -EINVAL;
 438 +
 439 +       mutex_lock(&timer_dev.gptu_mutex);
 440 +
 441 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 442 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 443 +               timer &= ~0x01;
 444 +
 445 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 446 +       if (((timer_dev.occupation & mask) ^ mask)) {
 447 +               mutex_unlock(&timer_dev.gptu_mutex);
 448 +               return -EINVAL;
 449 +       }
 450 +
 451 +       n = timer >> 1;
 452 +       X = timer & 0x01;
 453 +
 454 +       if (GPTU_CON_EN(n, X))
 455 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 456 +
 457 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 458 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 459 +
 460 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 461 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 462 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 463 +       }
 464 +
 465 +       timer_dev.occupation &= ~mask;
 466 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 467 +               lq_disable_gptu();
 468 +               timer_dev.f_gptu_on = 0;
 469 +       }
 470 +
 471 +       mutex_unlock(&timer_dev.gptu_mutex);
 472 +
 473 +       return 0;
 474 +}
 475 +EXPORT_SYMBOL(lq_free_timer);
 476 +
 477 +int lq_start_timer(unsigned int timer, int is_resume)
 478 +{
 479 +       unsigned int flag;
 480 +       unsigned int mask;
 481 +       int n, X;
 482 +
 483 +       if (!timer_dev.f_gptu_on)
 484 +               return -EINVAL;
 485 +
 486 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 487 +               return -EINVAL;
 488 +
 489 +       mutex_lock(&timer_dev.gptu_mutex);
 490 +
 491 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 492 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 493 +               timer &= ~0x01;
 494 +
 495 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 496 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 497 +       if (((timer_dev.occupation & mask) ^ mask)) {
 498 +               mutex_unlock(&timer_dev.gptu_mutex);
 499 +               return -EINVAL;
 500 +       }
 501 +
 502 +       n = timer >> 1;
 503 +       X = timer & 0x01;
 504 +
 505 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 506 +
 507 +
 508 +       mutex_unlock(&timer_dev.gptu_mutex);
 509 +
 510 +       return 0;
 511 +}
 512 +EXPORT_SYMBOL(lq_start_timer);
 513 +
 514 +int lq_stop_timer(unsigned int timer)
 515 +{
 516 +       unsigned int flag;
 517 +       unsigned int mask;
 518 +       int n, X;
 519 +
 520 +       if (!timer_dev.f_gptu_on)
 521 +               return -EINVAL;
 522 +
 523 +       if (timer < FIRST_TIMER
 524 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 525 +               return -EINVAL;
 526 +
 527 +       mutex_lock(&timer_dev.gptu_mutex);
 528 +
 529 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 530 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 531 +               timer &= ~0x01;
 532 +
 533 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 534 +       if (((timer_dev.occupation & mask) ^ mask)) {
 535 +               mutex_unlock(&timer_dev.gptu_mutex);
 536 +               return -EINVAL;
 537 +       }
 538 +
 539 +       n = timer >> 1;
 540 +       X = timer & 0x01;
 541 +
 542 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 543 +
 544 +       mutex_unlock(&timer_dev.gptu_mutex);
 545 +
 546 +       return 0;
 547 +}
 548 +EXPORT_SYMBOL(lq_stop_timer);
 549 +
 550 +int lq_reset_counter_flags(u32 timer, u32 flags)
 551 +{
 552 +       unsigned int oflag;
 553 +       unsigned int mask, con_reg;
 554 +       int n, X;
 555 +
 556 +       if (!timer_dev.f_gptu_on)
 557 +               return -EINVAL;
 558 +
 559 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 560 +               return -EINVAL;
 561 +
 562 +       mutex_lock(&timer_dev.gptu_mutex);
 563 +
 564 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 565 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 566 +               timer &= ~0x01;
 567 +
 568 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 569 +       if (((timer_dev.occupation & mask) ^ mask)) {
 570 +               mutex_unlock(&timer_dev.gptu_mutex);
 571 +               return -EINVAL;
 572 +       }
 573 +
 574 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 575 +       default:
 576 +       case TIMER_FLAG_NONE_EDGE:
 577 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 578 +               break;
 579 +       case TIMER_FLAG_RISE_EDGE:
 580 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 581 +               break;
 582 +       case TIMER_FLAG_FALL_EDGE:
 583 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 584 +               break;
 585 +       case TIMER_FLAG_ANY_EDGE:
 586 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 587 +               break;
 588 +       }
 589 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 590 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 591 +       else
 592 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 593 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 594 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 595 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 596 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 597 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 598 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 599 +
 600 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 601 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 602 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 603 +
 604 +       n = timer >> 1;
 605 +       X = timer & 0x01;
 606 +
 607 +       *LQ_GPTU_CON(n, X) = con_reg;
 608 +       smp_wmb();
 609 +       mutex_unlock(&timer_dev.gptu_mutex);
 610 +       return 0;
 611 +}
 612 +EXPORT_SYMBOL(lq_reset_counter_flags);
 613 +
 614 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 615 +{
 616 +       unsigned int flag;
 617 +       unsigned int mask;
 618 +       int n, X;
 619 +
 620 +       if (!timer_dev.f_gptu_on)
 621 +               return -EINVAL;
 622 +
 623 +       if (timer < FIRST_TIMER
 624 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 625 +               return -EINVAL;
 626 +
 627 +       mutex_lock(&timer_dev.gptu_mutex);
 628 +
 629 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 630 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 631 +               timer &= ~0x01;
 632 +
 633 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 634 +       if (((timer_dev.occupation & mask) ^ mask)) {
 635 +               mutex_unlock(&timer_dev.gptu_mutex);
 636 +               return -EINVAL;
 637 +       }
 638 +
 639 +       n = timer >> 1;
 640 +       X = timer & 0x01;
 641 +
 642 +       *value = *LQ_GPTU_COUNT(n, X);
 643 +
 644 +
 645 +       mutex_unlock(&timer_dev.gptu_mutex);
 646 +
 647 +       return 0;
 648 +}
 649 +EXPORT_SYMBOL(lq_get_count_value);
 650 +
 651 +u32 lq_cal_divider(unsigned long freq)
 652 +{
 653 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 654 +       u32 clock_divider = 1;
 655 +       module_freq = fpi * 1000;
 656 +       do_div(module_freq, clock_divider * freq);
 657 +       return module_freq;
 658 +}
 659 +EXPORT_SYMBOL(lq_cal_divider);
 660 +
 661 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 662 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 663 +       unsigned long arg2)
 664 +{
 665 +       unsigned long divider;
 666 +       unsigned int flag;
 667 +
 668 +       divider = lq_cal_divider(freq);
 669 +       if (divider == 0)
 670 +               return -EINVAL;
 671 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 672 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 673 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 674 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 675 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 676 +
 677 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 678 +               timer, freq, divider);
 679 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 680 +}
 681 +EXPORT_SYMBOL(lq_set_timer);
 682 +
 683 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 684 +       unsigned long arg1, unsigned long arg2)
 685 +{
 686 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 687 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 688 +}
 689 +EXPORT_SYMBOL(lq_set_counter);
 690 +
 691 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 692 +       unsigned long arg)
 693 +{
 694 +       int ret;
 695 +       struct gptu_ioctl_param param;
 696 +
 697 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 698 +               return -EFAULT;
 699 +       copy_from_user(&param, (void *) arg, sizeof(param));
 700 +
 701 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 702 +              || GPTU_SET_COUNTER) && param.timer < 2)
 703 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 704 +           && !access_ok(VERIFY_WRITE, arg,
 705 +                          sizeof(struct gptu_ioctl_param)))
 706 +               return -EFAULT;
 707 +
 708 +       switch (cmd) {
 709 +       case GPTU_REQUEST_TIMER:
 710 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 711 +                                    (unsigned long) param.pid,
 712 +                                    (unsigned long) param.sig);
 713 +               if (ret > 0) {
 714 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 715 +                                     timer, &ret, sizeof(&ret));
 716 +                       ret = 0;
 717 +               }
 718 +               break;
 719 +       case GPTU_FREE_TIMER:
 720 +               ret = lq_free_timer(param.timer);
 721 +               break;
 722 +       case GPTU_START_TIMER:
 723 +               ret = lq_start_timer(param.timer, param.flag);
 724 +               break;
 725 +       case GPTU_STOP_TIMER:
 726 +               ret = lq_stop_timer(param.timer);
 727 +               break;
 728 +       case GPTU_GET_COUNT_VALUE:
 729 +               ret = lq_get_count_value(param.timer, &param.value);
 730 +               if (!ret)
 731 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 732 +                                     value, &param.value,
 733 +                                     sizeof(param.value));
 734 +               break;
 735 +       case GPTU_CALCULATE_DIVIDER:
 736 +               param.value = lq_cal_divider(param.value);
 737 +               if (param.value == 0)
 738 +                       ret = -EINVAL;
 739 +               else {
 740 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 741 +                                     value, &param.value,
 742 +                                     sizeof(param.value));
 743 +                       ret = 0;
 744 +               }
 745 +               break;
 746 +       case GPTU_SET_TIMER:
 747 +               ret = lq_set_timer(param.timer, param.value,
 748 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 749 +                                TIMER_FLAG_ONCE ? 1 : 0,
 750 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 751 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 752 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 753 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 754 +                                TIMER_FLAG_NO_HANDLE,
 755 +                                (unsigned long) param.pid,
 756 +                                (unsigned long) param.sig);
 757 +               if (ret > 0) {
 758 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 759 +                                     timer, &ret, sizeof(&ret));
 760 +                       ret = 0;
 761 +               }
 762 +               break;
 763 +       case GPTU_SET_COUNTER:
 764 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 765 +               if (ret > 0) {
 766 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 767 +                                     timer, &ret, sizeof(&ret));
 768 +                       ret = 0;
 769 +               }
 770 +               break;
 771 +       default:
 772 +               ret = -ENOTTY;
 773 +       }
 774 +
 775 +       return ret;
 776 +}
 777 +
 778 +static int gptu_open(struct inode *inode, struct file *file)
 779 +{
 780 +       return 0;
 781 +}
 782 +
 783 +static int gptu_release(struct inode *inode, struct file *file)
 784 +{
 785 +       return 0;
 786 +}
 787 +
 788 +int __init lq_gptu_init(void)
 789 +{
 790 +       int ret;
 791 +       unsigned int i;
 792 +
 793 +       ltq_w32(0, LQ_GPTU_IRNEN);
 794 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 795 +
 796 +       memset(&timer_dev, 0, sizeof(timer_dev));
 797 +       mutex_init(&timer_dev.gptu_mutex);
 798 +
 799 +       lq_enable_gptu();
 800 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 801 +       lq_disable_gptu();
 802 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 803 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 804 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 805 +
 806 +       ret = misc_register(&gptu_miscdev);
 807 +       if (ret) {
 808 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 809 +               return ret;
 810 +       } else {
 811 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
 812 +       }
 813 +
 814 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 815 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
 816 +               if (ret) {
 817 +                       for (; i >= 0; i--)
 818 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
 819 +                       misc_deregister(&gptu_miscdev);
 820 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
 821 +                       return ret;
 822 +               } else {
 823 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
 824 +                       disable_irq(timer_dev.timer[i].irq);
 825 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
 826 +               }
 827 +       }
 828 +
 829 +       return 0;
 830 +}
 831 +
 832 +void __exit lq_gptu_exit(void)
 833 +{
 834 +       unsigned int i;
 835 +
 836 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 837 +               if (timer_dev.timer[i].f_irq_on)
 838 +                       disable_irq(timer_dev.timer[i].irq);
 839 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
 840 +       }
 841 +       lq_disable_gptu();
 842 +       misc_deregister(&gptu_miscdev);
 843 +}
 844 +
 845 +module_init(lq_gptu_init);
 846 +module_exit(lq_gptu_exit);
 847 +
 848 +#endif
 849 --- /dev/null
 850 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
 851 @@ -0,0 +1,155 @@
 852 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 853 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 854 +
 855 +
 856 +/******************************************************************************
 857 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
 858 +
 859 +                               No Warranty
 860 +   Because the program is licensed free of charge, there is no warranty for
 861 +   the program, to the extent permitted by applicable law.  Except when
 862 +   otherwise stated in writing the copyright holders and/or other parties
 863 +   provide the program "as is" without warranty of any kind, either
 864 +   expressed or implied, including, but not limited to, the implied
 865 +   warranties of merchantability and fitness for a particular purpose. The
 866 +   entire risk as to the quality and performance of the program is with
 867 +   you.  should the program prove defective, you assume the cost of all
 868 +   necessary servicing, repair or correction.
 869 +
 870 +   In no event unless required by applicable law or agreed to in writing
 871 +   will any copyright holder, or any other party who may modify and/or
 872 +   redistribute the program as permitted above, be liable to you for
 873 +   damages, including any general, special, incidental or consequential
 874 +   damages arising out of the use or inability to use the program
 875 +   (including but not limited to loss of data or data being rendered
 876 +   inaccurate or losses sustained by you or third parties or a failure of
 877 +   the program to operate with any other programs), even if such holder or
 878 +   other party has been advised of the possibility of such damages.
 879 +******************************************************************************/
 880 +
 881 +
 882 +/*
 883 + * ####################################
 884 + *              Definition
 885 + * ####################################
 886 + */
 887 +
 888 +/*
 889 + *  Available Timer/Counter Index
 890 + */
 891 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
 892 +#define TIMER_ANY                       0x00
 893 +#define TIMER1A                         TIMER(1, 0)
 894 +#define TIMER1B                         TIMER(1, 1)
 895 +#define TIMER2A                         TIMER(2, 0)
 896 +#define TIMER2B                         TIMER(2, 1)
 897 +#define TIMER3A                         TIMER(3, 0)
 898 +#define TIMER3B                         TIMER(3, 1)
 899 +
 900 +/*
 901 + *  Flag of Timer/Counter
 902 + *  These flags specify the way in which timer is configured.
 903 + */
 904 +/*  Bit size of timer/counter.                      */
 905 +#define TIMER_FLAG_16BIT                0x0000
 906 +#define TIMER_FLAG_32BIT                0x0001
 907 +/*  Switch between timer and counter.               */
 908 +#define TIMER_FLAG_TIMER                0x0000
 909 +#define TIMER_FLAG_COUNTER              0x0002
 910 +/*  Stop or continue when overflowing/underflowing. */
 911 +#define TIMER_FLAG_ONCE                 0x0000
 912 +#define TIMER_FLAG_CYCLIC               0x0004
 913 +/*  Count up or counter down.                       */
 914 +#define TIMER_FLAG_UP                   0x0000
 915 +#define TIMER_FLAG_DOWN                 0x0008
 916 +/*  Count on specific level or edge.                */
 917 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
 918 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
 919 +#define TIMER_FLAG_RISE_EDGE            0x0010
 920 +#define TIMER_FLAG_FALL_EDGE            0x0020
 921 +#define TIMER_FLAG_ANY_EDGE             0x0030
 922 +/*  Signal is syncronous to module clock or not.    */
 923 +#define TIMER_FLAG_UNSYNC               0x0000
 924 +#define TIMER_FLAG_SYNC                 0x0080
 925 +/*  Different interrupt handle type.                */
 926 +#define TIMER_FLAG_NO_HANDLE            0x0000
 927 +#if defined(__KERNEL__)
 928 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
 929 +#endif  //  defined(__KERNEL__)
 930 +#define TIMER_FLAG_SIGNAL               0x0300
 931 +/*  Internal clock source or external clock source  */
 932 +#define TIMER_FLAG_INT_SRC              0x0000
 933 +#define TIMER_FLAG_EXT_SRC              0x1000
 934 +
 935 +
 936 +/*
 937 + *  ioctl Command
 938 + */
 939 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 940 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 941 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 942 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 943 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 944 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 945 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 946 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 947 +
 948 +/*
 949 + *  Data Type Used to Call ioctl
 950 + */
 951 +struct gptu_ioctl_param {
 952 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 953 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 954 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 955 +                                                 *  be dynamically allocated and ID would be stored in  *
 956 +                                                 *  this field.                                         *
 957 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 958 +                                                 *  ignored.                                            *
 959 +                                                 *  In other command, this field is ID of timer/counter *
 960 +                                                 *  allocated.                                          */
 961 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 962 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 963 +                                                 *  specify how to configure timer/counter.             *
 964 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 965 +                                                 *  and non-zero indicate resume timer/counter.         *
 966 +                                                 *  In other command, this field is ignored.            */
 967 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 968 +                                                 *  init/reload value.                                  *
 969 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 970 +                                                 *  frequency (0.001Hz) of timer.                       *
 971 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 972 +                                                 *  value would be stored in this field.                *
 973 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 974 +                                                 *  contains frequency wanted, and after calculation,   *
 975 +                                                 *  divider would be stored in this field to overwrite  *
 976 +                                                 *  the frequency.                                      *
 977 +                                                 *  In other command, this field is ignored.            */
 978 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 979 +                                                 *  if signal is required, this field contains process  *
 980 +                                                 *  ID to which signal would be sent.                   *
 981 +                                                 *  In other command, this field is ignored.            */
 982 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 983 +                                                 *  if signal is required, this field contains signal   *
 984 +                                                 *  number which would be sent.                         *
 985 +                                                 *  In other command, this field is ignored.            */
 986 +};
 987 +
 988 +/*
 989 + * ####################################
 990 + *              Data Type
 991 + * ####################################
 992 + */
 993 +typedef void (*timer_callback)(unsigned long arg);
 994 +
 995 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 996 +extern int lq_free_timer(unsigned int);
 997 +extern int lq_start_timer(unsigned int, int);
 998 +extern int lq_stop_timer(unsigned int);
 999 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
1000 +extern int lq_get_count_value(unsigned int, unsigned long *);
1001 +extern u32 lq_cal_divider(unsigned long);
1002 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
1003 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
1004 +       u32 reload, unsigned long arg1, unsigned long arg2);
1005 +
1006 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
1007 --- a/arch/mips/lantiq/xway/Makefile
1008 +++ b/arch/mips/lantiq/xway/Makefile
1009 @@ -1,3 +1,3 @@
1010 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
1011 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o
1012
1013  obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o