target/linux/lantiq/patches-3.0/420-spi3.patch

   1 From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
   2 Date: Thu, 3 Mar 2011 20:42:26 +0000 (+0100)
   3 Subject: MIPS: lantiq: Add device register helper for SPI controller and devices
   4 X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=b35b07062b718ece9b9cb7b23b12d83a087eafb0;hp=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90
   5
   6 MIPS: lantiq: Add device register helper for SPI controller and devices
   7
   8 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
   9 ---
  10
  11 --- a/arch/mips/lantiq/xway/devices.h
  12 +++ b/arch/mips/lantiq/xway/devices.h
  13 @@ -11,10 +11,13 @@
  14
  15  #include "../devices.h"
  16  #include <linux/phy.h>
  17 +#include <linux/spi/spi.h>
  18
  19  extern void ltq_register_gpio(void);
  20  extern void ltq_register_gpio_stp(void);
  21  extern void ltq_register_ase_asc(void);
  22  extern void ltq_register_etop(struct ltq_eth_data *eth);
  23 +extern void ltq_register_spi(struct ltq_spi_platform_data *pdata,
  24 +       struct spi_board_info const *info, unsigned n);
  25
  26  #endif
  27 --- a/arch/mips/lantiq/xway/devices.c
  28 +++ b/arch/mips/lantiq/xway/devices.c
  29 @@ -21,6 +21,7 @@
  30  #include <linux/io.h>
  31  #include <linux/gpio.h>
  32  #include <linux/leds.h>
  33 +#include <linux/spi/spi.h>
  34
  35  #include <asm/bootinfo.h>
  36  #include <asm/irq.h>
  37 @@ -119,3 +120,41 @@ ltq_register_etop(struct ltq_eth_data *e
  38                 platform_device_register(&ltq_etop);
  39         }
  40  }
  41 +
  42 +static struct resource ltq_spi_resources[] = {
  43 +       {
  44 +               .start  = LTQ_SSC_BASE_ADDR,
  45 +               .end    = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
  46 +               .flags  = IORESOURCE_MEM,
  47 +       },
  48 +       IRQ_RES(spi_tx, LTQ_SSC_TIR),
  49 +       IRQ_RES(spi_rx, LTQ_SSC_RIR),
  50 +       IRQ_RES(spi_err, LTQ_SSC_EIR),
  51 +};
  52 +
  53 +static struct resource ltq_spi_resources_ar9[] = {
  54 +       {
  55 +               .start  = LTQ_SSC_BASE_ADDR,
  56 +               .end    = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
  57 +               .flags  = IORESOURCE_MEM,
  58 +       },
  59 +       IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9),
  60 +       IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9),
  61 +       IRQ_RES(spi_err, LTQ_SSC_EIR),
  62 +};
  63 +
  64 +static struct platform_device ltq_spi = {
  65 +       .name           = "ltq-spi",
  66 +       .resource       = ltq_spi_resources,
  67 +       .num_resources  = ARRAY_SIZE(ltq_spi_resources),
  68 +};
  69 +
  70 +void __init ltq_register_spi(struct ltq_spi_platform_data *pdata,
  71 +               struct spi_board_info const *info, unsigned n)
  72 +{
  73 +       if(ltq_is_ar9())
  74 +               ltq_spi.resource = ltq_spi_resources_ar9;
  75 +       spi_register_board_info(info, n);
  76 +       ltq_spi.dev.platform_data = pdata;
  77 +       platform_device_register(&ltq_spi);
  78 +}
  79 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
  80 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
  81 @@ -27,6 +27,8 @@
  82
  83  #define LTQ_SSC_TIR            (INT_NUM_IM0_IRL0 + 15)
  84  #define LTQ_SSC_RIR            (INT_NUM_IM0_IRL0 + 14)
  85 +#define LTQ_SSC_TIR_AR9                (INT_NUM_IM0_IRL0 + 14)
  86 +#define LTQ_SSC_RIR_AR9                (INT_NUM_IM0_IRL0 + 15)
  87  #define LTQ_SSC_EIR            (INT_NUM_IM0_IRL0 + 16)
  88
  89  #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)