1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
4 * $Date: 2009-04-17 06:15:34 $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include <linux/kernel.h>
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/init.h>
55 #include <linux/gpio.h>
57 #include <linux/device.h>
58 #include <linux/platform_device.h>
60 #include <linux/errno.h>
61 #include <linux/types.h>
62 #include <linux/stat.h> /* permission constants */
63 #include <linux/irq.h>
66 #include "dwc_otg_plat.h"
67 #include "dwc_otg_attr.h"
68 #include "dwc_otg_driver.h"
69 #include "dwc_otg_cil.h"
70 #include "dwc_otg_cil_ifx.h"
72 // #include "dwc_otg_pcd.h" // device
73 #include "dwc_otg_hcd.h" // host
75 #include "dwc_otg_ifx.h" // for Infineon platform specific.
77 #define DWC_DRIVER_VERSION "2.60a 22-NOV-2006"
78 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
80 const char dwc_driver_name[] = "dwc_otg";
82 static unsigned long dwc_iomem_base = IFX_USB_IOMEM_BASE;
83 int dwc_irq = LTQ_USB_INT;
85 //int dwc_irq = IFXMIPS_USB_OC_INT;
87 extern int ifx_usb_hc_init(unsigned long base_addr, int irq);
88 extern void ifx_usb_hc_remove(void);
90 /*-------------------------------------------------------------------------*/
91 /* Encapsulate the module parameter settings */
93 static dwc_otg_core_params_t dwc_otg_module_params = {
99 .host_support_fs_ls_low_power = -1,
100 .host_ls_low_power_phy_clk = -1,
101 .enable_dynamic_fifo = -1,
102 .data_fifo_size = -1,
103 .dev_rx_fifo_size = -1,
104 .dev_nperio_tx_fifo_size = -1,
105 .dev_perio_tx_fifo_size = /* dev_perio_tx_fifo_size_1 */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 15 */
106 .host_rx_fifo_size = -1,
107 .host_nperio_tx_fifo_size = -1,
108 .host_perio_tx_fifo_size = -1,
109 .max_transfer_size = -1,
110 .max_packet_count = -1,
114 .phy_utmi_width = -1,
116 .phy_ulpi_ext_vbus = -1,
120 .en_multiple_tx_fifo = -1,
121 .dev_tx_fifo_size = { /* dev_tx_fifo_size */
122 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
130 * This function shows the Driver Version.
132 static ssize_t version_show(struct device_driver *dev, char *buf)
134 return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n",
137 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
140 * Global Debug Level Mask.
142 uint32_t g_dbg_lvl = 0xff; /* OFF */
145 * This function shows the driver Debug Level.
147 static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf)
149 return sprintf(_buf, "0x%0x\n", g_dbg_lvl);
152 * This function stores the driver Debug Level.
154 static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf,
157 g_dbg_lvl = simple_strtoul(_buf, NULL, 16);
160 static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
163 * This function is called during module intialization to verify that
164 * the module parameters are in a valid state.
166 static int check_parameters(dwc_otg_core_if_t *core_if)
171 /* Checks if the parameter is outside of its valid range of values */
172 #define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \
173 ((dwc_otg_module_params._param_ < (_low_)) || \
174 (dwc_otg_module_params._param_ > (_high_)))
176 /* If the parameter has been set by the user, check that the parameter value is
177 * within the value range of values. If not, report a module error. */
178 #define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \
180 if (dwc_otg_module_params._param_ != -1) { \
181 if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \
182 DWC_ERROR("`%d' invalid for parameter `%s'\n", \
183 dwc_otg_module_params._param_, _string_); \
184 dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
190 DWC_OTG_PARAM_ERR(opt,0,1,"opt");
191 DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
192 DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
193 DWC_OTG_PARAM_ERR(speed,0,1,"speed");
194 DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
195 DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
196 DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
197 DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
198 DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
199 DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
200 DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
201 DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
202 DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
203 DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
204 DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
205 DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
206 DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
207 DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
208 DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
209 DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
210 DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
211 DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
212 DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
214 if (dwc_otg_module_params.dma_burst_size != -1) {
215 if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
216 DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
217 DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
218 DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
219 DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
220 DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
221 DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
222 DWC_OTG_PARAM_TEST(dma_burst_size,256,256))
224 DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
225 dwc_otg_module_params.dma_burst_size);
226 dwc_otg_module_params.dma_burst_size = 32;
231 if (dwc_otg_module_params.phy_utmi_width != -1) {
232 if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) &&
233 DWC_OTG_PARAM_TEST(phy_utmi_width,16,16))
235 DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
236 dwc_otg_module_params.phy_utmi_width);
237 //dwc_otg_module_params.phy_utmi_width = 16;
238 dwc_otg_module_params.phy_utmi_width = 8;
243 for (i=0; i<15; i++) {
244 /** @todo should be like above */
245 //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size");
246 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
247 if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768)) {
248 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
249 dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
250 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
256 DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
257 for (i = 0; i < 15; i++) {
258 /** @todo should be like above */
259 //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size");
260 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
261 if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
262 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
263 dwc_otg_module_params.dev_tx_fifo_size[i],
264 "dev_tx_fifo_size", i);
265 dwc_otg_module_params.dev_tx_fifo_size[i] =
266 dwc_param_dev_tx_fifo_size_default;
271 DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
272 DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
273 DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
275 /* At this point, all module parameters that have been set by the user
276 * are valid, and those that have not are left unset. Now set their
277 * default values and/or check the parameters against the hardware
278 * configurations of the OTG core. */
282 /* This sets the parameter to the default value if it has not been set by the
284 #define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
287 if (dwc_otg_module_params._param_ == -1) { \
289 dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
294 /* This checks the macro agains the hardware configuration to see if it is
295 * valid. It is possible that the default value could be invalid. In this
296 * case, it will report a module error if the user touched the parameter.
297 * Otherwise it will adjust the value without any error. */
298 #define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \
300 int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
302 if (!(_is_valid_)) { \
304 DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \
307 dwc_otg_module_params._param_ = (_set_valid_); \
313 retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap",
317 switch (dwc_otg_module_params.otg_cap) {
318 case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
319 if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0;
321 case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
322 if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
323 (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
324 (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
325 (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST))
330 case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
336 (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
337 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
338 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
339 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
340 DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
341 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
343 retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable",
344 ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
347 retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt",
351 DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
353 retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
354 "host_support_fs_ls_low_power",
357 retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
358 "enable_dynamic_fifo",
359 ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
360 (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
363 retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
365 (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
366 core_if->hwcfg3.b.dfifo_depth);
368 retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
370 (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
371 dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
373 retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
374 "dev_nperio_tx_fifo_size",
375 (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
376 (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
378 retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
380 (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
381 dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
384 retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
385 "host_nperio_tx_fifo_size",
386 (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
387 (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
389 retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
390 "host_perio_tx_fifo_size",
391 (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
392 ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
394 retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
396 (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
397 ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
399 retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
401 (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
402 ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
404 retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
406 (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
407 (core_if->hwcfg2.b.num_host_chan + 1));
409 retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
411 (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
412 core_if->hwcfg2.b.num_dev_ep);
415 * Define the following to disable the FS PHY Hardware checking. This is for
416 * internal testing only.
418 * #define NO_FS_PHY_HW_CHECKS
421 #ifdef NO_FS_PHY_HW_CHECKS
422 retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
425 retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
429 if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
430 ((core_if->hwcfg2.b.hs_phy_type == 1) ||
431 (core_if->hwcfg2.b.hs_phy_type == 3)))
435 else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
436 ((core_if->hwcfg2.b.hs_phy_type == 2) ||
437 (core_if->hwcfg2.b.hs_phy_type == 3)))
441 else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
442 (core_if->hwcfg2.b.fs_phy_type == 1))
449 int set = DWC_PHY_TYPE_PARAM_FS;
450 if (core_if->hwcfg2.b.hs_phy_type) {
451 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
452 (core_if->hwcfg2.b.hs_phy_type == 1)) {
453 set = DWC_PHY_TYPE_PARAM_UTMI;
456 set = DWC_PHY_TYPE_PARAM_ULPI;
463 retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed",
464 (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
465 dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
467 retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
468 "host_ls_low_power_phy_clk",
469 ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
470 ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
472 DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
473 DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
474 DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
475 DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
476 DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
478 #ifdef NO_FS_PHY_HW_CHECKS
479 retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
482 retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
484 (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
488 for (i=0; i<16; i++) {
493 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
495 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
497 if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
499 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i);
502 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
507 retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,
508 "en_multiple_tx_fifo",
509 ((dwc_otg_module_params.en_multiple_tx_fifo == 1) &&
510 (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0);
512 for (i = 0; i < 16; i++) {
515 if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
517 dwc_otg_module_params.dev_tx_fifo_size[i] =
518 dwc_param_dev_tx_fifo_size_default;
520 if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <=
521 (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
523 DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'."
524 "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i);
527 dwc_otg_module_params.dev_tx_fifo_size[i] =
528 dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
532 DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
533 DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
534 DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
536 } // check_parameters
540 * This function is the top level interrupt handler for the Common
541 * (Device and host modes) interrupts.
543 static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev)
545 dwc_otg_device_t *otg_dev = _dev;
546 int32_t retval = IRQ_NONE;
548 retval = dwc_otg_handle_common_intr( otg_dev->core_if );
550 mask_and_ack_ifx_irq (_irq);
552 return IRQ_RETVAL(retval);
557 * This function is called when a DWC_OTG device is unregistered with the
558 * dwc_otg_driver. This happens, for example, when the rmmod command is
559 * executed. The device may or may not be electrically present. If it is
560 * present, the driver stops device processing. Any resources used on behalf
561 * of this device are freed.
566 dwc_otg_driver_remove(struct platform_device *_dev)
568 //dwc_otg_device_t *otg_dev = dev_get_drvdata(&_dev->dev);
569 dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
571 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
573 if (otg_dev == NULL) {
574 /* Memory allocation for the dwc_otg_device failed. */
581 if (otg_dev->common_irq_installed) {
582 free_irq( otg_dev->irq, otg_dev );
585 #ifndef DWC_DEVICE_ONLY
586 if (otg_dev->hcd != NULL) {
587 dwc_otg_hcd_remove(&_dev->dev);
590 printk("after removehcd\n");
592 // Note: Integrate HOST and DEVICE(Gadget) is not planned yet.
593 #ifndef DWC_HOST_ONLY
594 if (otg_dev->pcd != NULL) {
595 dwc_otg_pcd_remove(otg_dev);
598 if (otg_dev->core_if != NULL) {
599 dwc_otg_cil_remove( otg_dev->core_if );
601 printk("after removecil\n");
604 * Remove the device attributes
606 dwc_otg_attr_remove(&_dev->dev);
607 printk("after removeattr\n");
612 if (otg_dev->base != NULL) {
613 iounmap(otg_dev->base);
615 if (otg_dev->phys_addr != 0) {
616 release_mem_region(otg_dev->phys_addr, otg_dev->base_len);
621 * Clear the drvdata pointer.
623 //dev_set_drvdata(&_dev->dev, 0);
624 platform_set_drvdata(_dev, 0);
629 * This function is called when an DWC_OTG device is bound to a
630 * dwc_otg_driver. It creates the driver components required to
631 * control the device (CIL, HCD, and PCD) and it initializes the
632 * device. The driver components are stored in a dwc_otg_device
633 * structure. A reference to the dwc_otg_device is saved in the
634 * lm_device. This allows the driver to access the dwc_otg_device
635 * structure on subsequent calls to driver methods for this device.
640 dwc_otg_driver_probe(struct platform_device *_dev)
643 dwc_otg_device_t *dwc_otg_device;
644 int pin = (int)_dev->dev.platform_data;
646 struct resource *res;
647 gusbcfg_data_t usbcfg = {.d32 = 0};
652 gpio_request(pin, "usb_power");
653 gpio_direction_output(pin, 1);
654 gpio_set_value(pin, 1);
657 dev_dbg(&_dev->dev, "dwc_otg_driver_probe (%p)\n", _dev);
659 dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
660 if (dwc_otg_device == 0) {
661 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
665 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
666 dwc_otg_device->reg_offset = 0xFFFFFFFF;
669 * Retrieve the memory and IRQ resources.
671 dwc_otg_device->irq = platform_get_irq(_dev, 0);
672 if (dwc_otg_device->irq == 0) {
673 dev_err(&_dev->dev, "no device irq\n");
677 dev_dbg(&_dev->dev, "OTG - device irq: %d\n", dwc_otg_device->irq);
678 res = platform_get_resource(_dev, IORESOURCE_MEM, 0);
680 dev_err(&_dev->dev, "no CSR address\n");
684 dev_dbg(&_dev->dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n",
685 (unsigned)res->start, (unsigned)res->end);
686 dwc_otg_device->phys_addr = res->start;
687 dwc_otg_device->base_len = res->end - res->start + 1;
688 if (request_mem_region(dwc_otg_device->phys_addr, dwc_otg_device->base_len,
689 dwc_driver_name) == NULL) {
690 dev_err(&_dev->dev, "request_mem_region failed\n");
696 * Map the DWC_otg Core memory into virtual address space.
698 dwc_otg_device->base = ioremap_nocache(dwc_otg_device->phys_addr, dwc_otg_device->base_len);
699 if (dwc_otg_device->base == NULL) {
700 dev_err(&_dev->dev, "ioremap() failed\n");
704 dev_dbg(&_dev->dev, "mapped base=0x%08x\n", (unsigned)dwc_otg_device->base);
707 * Attempt to ensure this device is really a DWC_otg Controller.
708 * Read and verify the SNPSID register contents. The value should be
709 * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
711 snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
712 if ((snpsid & 0xFFFFF000) != 0x4F542000) {
713 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
719 * Initialize driver data to point to the global DWC_otg
722 platform_set_drvdata(_dev, dwc_otg_device);
723 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
724 dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params);
725 if (dwc_otg_device->core_if == 0) {
726 dev_err(&_dev->dev, "CIL initialization failed!\n");
732 * Validate parameter values.
734 if (check_parameters(dwc_otg_device->core_if) != 0) {
739 /* Added for PLB DMA phys virt mapping */
740 //dwc_otg_device->core_if->phys_addr = dwc_otg_device->phys_addr;
742 * Create Device Attributes in sysfs
744 dwc_otg_attr_create (&_dev->dev);
747 * Disable the global interrupt until all the interrupt
748 * handlers are installed.
750 dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
752 * Install the interrupt handler for the common interrupts before
753 * enabling common interrupts in core_init below.
755 DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n", dwc_otg_device->irq);
757 retval = request_irq((unsigned int)dwc_otg_device->irq, dwc_otg_common_irq,
758 //SA_INTERRUPT|SA_SHIRQ, "dwc_otg", (void *)dwc_otg_device );
759 IRQF_SHARED, "dwc_otg", (void *)dwc_otg_device );
760 //IRQF_DISABLED, "dwc_otg", (void *)dwc_otg_device );
762 DWC_ERROR("request of irq%d failed retval: %d\n", dwc_otg_device->irq, retval);
766 dwc_otg_device->common_irq_installed = 1;
770 * Initialize the DWC_otg core.
772 dwc_otg_core_init( dwc_otg_device->core_if );
775 #ifndef DWC_HOST_ONLY // otg device mode. (gadget.)
779 retval = dwc_otg_pcd_init(dwc_otg_device);
781 DWC_ERROR("dwc_otg_pcd_init failed\n");
782 dwc_otg_device->pcd = NULL;
785 #endif // DWC_HOST_ONLY
787 #ifndef DWC_DEVICE_ONLY // otg host mode. (HCD)
792 /* force_host_mode */
793 usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
794 usbcfg.b.force_host_mode = 1;
795 dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
797 retval = dwc_otg_hcd_init(&_dev->dev, dwc_otg_device);
799 DWC_ERROR("dwc_otg_hcd_init failed\n");
800 dwc_otg_device->hcd = NULL;
803 #endif // DWC_DEVICE_ONLY
806 * Enable the global interrupt after all the interrupt
807 * handlers are installed.
809 dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
811 usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
812 usbcfg.b.force_host_mode = 0;
813 dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
820 dwc_otg_driver_remove(_dev);
825 * This structure defines the methods to be called by a bus driver
826 * during the lifecycle of a device on that bus. Both drivers and
827 * devices are registered with a bus driver. The bus driver matches
828 * devices to drivers based on information in the device and driver
831 * The probe function is called when the bus driver matches a device
832 * to this driver. The remove function is called when a device is
833 * unregistered with the bus driver.
835 struct platform_driver dwc_otg_driver = {
836 .probe = dwc_otg_driver_probe,
837 .remove = dwc_otg_driver_remove,
838 // .suspend = dwc_otg_driver_suspend,
839 // .resume = dwc_otg_driver_resume,
841 .name = dwc_driver_name,
842 .owner = THIS_MODULE,
845 EXPORT_SYMBOL(dwc_otg_driver);
848 * This function is called when the dwc_otg_driver is installed with the
849 * insmod command. It registers the dwc_otg_driver structure with the
850 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
851 * to be called. In addition, the bus driver will automatically expose
852 * attributes defined for the device and driver in the special sysfs file
857 static int __init dwc_otg_init(void)
861 printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
864 dwc_irq = LTQ_USB_ASE_INT;
867 retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
870 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
873 dwc_otg_power_on(); // ifx only!!
876 retval = platform_driver_register(&dwc_otg_driver);
879 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
883 retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
886 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
889 retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
892 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
899 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
901 driver_unregister(&dwc_otg_driver.driver);
906 module_init(dwc_otg_init);
909 * This function is called when the driver is removed from the kernel
910 * with the rmmod command. The driver unregisters itself with its bus
914 static void __exit dwc_otg_cleanup(void)
916 printk(KERN_DEBUG "dwc_otg_cleanup()\n");
918 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
919 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
921 platform_driver_unregister(&dwc_otg_driver);
924 printk(KERN_INFO "%s module removed\n", dwc_driver_name);
926 module_exit(dwc_otg_cleanup);
928 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
929 MODULE_AUTHOR("Synopsys Inc.");
930 MODULE_LICENSE("GPL");
932 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
933 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
934 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
935 MODULE_PARM_DESC(opt, "OPT Mode");
936 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
937 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
938 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
939 MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
940 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
941 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
942 module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
943 MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
944 module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
945 MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
946 module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
947 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
948 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
949 MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
950 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
951 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
952 module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
953 MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
954 module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
955 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
956 module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
957 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
958 module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
959 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
960 module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
961 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
962 module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
963 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
964 module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
965 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
966 module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
967 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
968 module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
969 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
970 module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
971 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
972 module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
973 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
974 module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
975 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
976 module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
977 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
978 module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
979 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
980 module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
981 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
982 module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
983 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
984 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
985 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
986 module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
987 MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
988 module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
989 MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
990 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
991 /** @todo Set the max to 512K, modify checks */
992 MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
993 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
994 MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
995 module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
996 MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
997 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
998 MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
999 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1000 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1001 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
1002 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1003 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1004 MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
1005 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
1006 MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
1007 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1008 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1009 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1010 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1011 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1012 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1013 module_param_named(debug, g_dbg_lvl, int, 0444);
1014 MODULE_PARM_DESC(debug, "0");
1015 module_param_named(en_multiple_tx_fifo,
1016 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1017 MODULE_PARM_DESC(en_multiple_tx_fifo,
1018 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1019 module_param_named(dev_tx_fifo_size_1,
1020 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1021 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1022 module_param_named(dev_tx_fifo_size_2,
1023 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1024 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1025 module_param_named(dev_tx_fifo_size_3,
1026 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1027 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1028 module_param_named(dev_tx_fifo_size_4,
1029 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1030 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1031 module_param_named(dev_tx_fifo_size_5,
1032 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1033 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1034 module_param_named(dev_tx_fifo_size_6,
1035 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1036 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1037 module_param_named(dev_tx_fifo_size_7,
1038 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1039 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1040 module_param_named(dev_tx_fifo_size_8,
1041 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1042 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1043 module_param_named(dev_tx_fifo_size_9,
1044 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1045 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1046 module_param_named(dev_tx_fifo_size_10,
1047 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1048 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1049 module_param_named(dev_tx_fifo_size_11,
1050 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1051 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1052 module_param_named(dev_tx_fifo_size_12,
1053 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1054 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1055 module_param_named(dev_tx_fifo_size_13,
1056 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1057 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1058 module_param_named(dev_tx_fifo_size_14,
1059 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1060 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1061 module_param_named(dev_tx_fifo_size_15,
1062 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1063 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1064 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1065 MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit"
1066 "0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1067 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
1068 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1069 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
1070 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1071 module_param_named (iomem_base, dwc_iomem_base, ulong, 0444);
1072 MODULE_PARM_DESC (dwc_iomem_base, "The base address of the DWC_OTG register.");
1073 module_param_named (irq, dwc_irq, int, 0444);
1074 MODULE_PARM_DESC (dwc_irq, "The interrupt number");
1076 /** @page "Module Parameters"
1078 * The following parameters may be specified when starting the module.
1079 * These parameters define how the DWC_otg controller should be
1080 * configured. Parameter values are passed to the CIL initialization
1081 * function dwc_otg_cil_init
1083 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1087 <tr><td>Parameter Name</td><td>Meaning</td></tr>
1091 <td>Specifies the OTG capabilities. The driver will automatically detect the
1092 value for this parameter if none is specified.
1093 - 0: HNP and SRP capable (default, if available)
1094 - 1: SRP Only capable
1095 - 2: No HNP/SRP capable
1100 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1101 The driver will automatically detect the value for this parameter if none is
1104 - 1: DMA (default, if available)
1108 <td>dma_burst_size</td>
1109 <td>The DMA Burst size (applicable only for External DMA Mode).
1110 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1115 <td>Specifies the maximum speed of operation in host and device mode. The
1116 actual speed depends on the speed of the attached device and the value of
1118 - 0: High Speed (default)
1123 <td>host_support_fs_ls_low_power</td>
1124 <td>Specifies whether low power mode is supported when attached to a Full
1125 Speed or Low Speed device in host mode.
1126 - 0: Don't support low power mode (default)
1127 - 1: Support low power mode
1131 <td>host_ls_low_power_phy_clk</td>
1132 <td>Specifies the PHY clock rate in low power mode when connected to a Low
1133 Speed device in host mode. This parameter is applicable only if
1134 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1135 - 0: 48 MHz (default)
1140 <td>enable_dynamic_fifo</td>
1141 <td> Specifies whether FIFOs may be resized by the driver software.
1142 - 0: Use cC FIFO size parameters
1143 - 1: Allow dynamic FIFO sizing (default)
1147 <td>data_fifo_size</td>
1148 <td>Total number of 4-byte words in the data FIFO memory. This memory
1149 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1150 - Values: 32 to 32768 (default 8192)
1152 Note: The total FIFO memory depth in the FPGA configuration is 8192.
1156 <td>dev_rx_fifo_size</td>
1157 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1158 FIFO sizing is enabled.
1159 - Values: 16 to 32768 (default 1064)
1163 <td>dev_nperio_tx_fifo_size</td>
1164 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1165 dynamic FIFO sizing is enabled.
1166 - Values: 16 to 32768 (default 1024)
1170 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
1171 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
1172 when dynamic FIFO sizing is enabled.
1173 - Values: 4 to 768 (default 256)
1177 <td>host_rx_fifo_size</td>
1178 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
1180 - Values: 16 to 32768 (default 1024)
1184 <td>host_nperio_tx_fifo_size</td>
1185 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
1186 dynamic FIFO sizing is enabled in the core.
1187 - Values: 16 to 32768 (default 1024)
1191 <td>host_perio_tx_fifo_size</td>
1192 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
1194 - Values: 16 to 32768 (default 1024)
1198 <td>max_transfer_size</td>
1199 <td>The maximum transfer size supported in bytes.
1200 - Values: 2047 to 65,535 (default 65,535)
1204 <td>max_packet_count</td>
1205 <td>The maximum number of packets in a transfer.
1206 - Values: 15 to 511 (default 511)
1210 <td>host_channels</td>
1211 <td>The number of host channel registers to use.
1212 - Values: 1 to 16 (default 12)
1214 Note: The FPGA configuration supports a maximum of 12 host channels.
1218 <td>dev_endpoints</td>
1219 <td>The number of endpoints in addition to EP0 available for device mode
1221 - Values: 1 to 15 (default 6 IN and OUT)
1223 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
1229 <td>Specifies the type of PHY interface to use. By default, the driver will
1230 automatically detect the phy_type.
1232 - 1: UTMI+ (default, if available)
1237 <td>phy_utmi_width</td>
1238 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
1239 phy_type of UTMI+. Also, this parameter is applicable only if the
1240 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
1241 core has been configured to work at either data path width.
1242 - Values: 8 or 16 bits (default 16)
1246 <td>phy_ulpi_ddr</td>
1247 <td>Specifies whether the ULPI operates at double or single data rate. This
1248 parameter is only applicable if phy_type is ULPI.
1249 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
1250 - 1: double data rate ULPI interface with 4 bit wide data bus
1255 <td>Specifies whether to use the I2C interface for full speed PHY. This
1256 parameter is only applicable if PHY_TYPE is FS.
1257 - 0: Disabled (default)
1262 <td>otg_en_multiple_tx_fifo</td>
1263 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
1264 The driver will automatically detect the value for this parameter if none is
1267 - 1: Enabled (default, if available)
1271 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
1272 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
1273 when dynamic FIFO sizing is enabled.
1274 - Values: 4 to 768 (default 256)