2 * Lantiq SoC SPI controller
4 * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/workqueue.h>
14 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/completion.h>
20 #include <linux/spinlock.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_bitbang.h>
27 #include <lantiq_soc.h>
28 #include <lantiq_platform.h>
30 #define LTQ_SPI_CLC 0x00 /* Clock control */
31 #define LTQ_SPI_PISEL 0x04 /* Port input select */
32 #define LTQ_SPI_ID 0x08 /* Identification */
33 #define LTQ_SPI_CON 0x10 /* Control */
34 #define LTQ_SPI_STAT 0x14 /* Status */
35 #define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */
36 #define LTQ_SPI_TB 0x20 /* Transmit buffer */
37 #define LTQ_SPI_RB 0x24 /* Receive buffer */
38 #define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */
39 #define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */
40 #define LTQ_SPI_FSTAT 0x38 /* FIFO status */
41 #define LTQ_SPI_BRT 0x40 /* Baudrate timer */
42 #define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */
43 #define LTQ_SPI_SFCON 0x60 /* Serial frame control */
44 #define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */
45 #define LTQ_SPI_GPOCON 0x70 /* General purpose output control */
46 #define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */
47 #define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */
48 #define LTQ_SPI_RXREQ 0x80 /* Receive request */
49 #define LTQ_SPI_RXCNT 0x84 /* Receive count */
50 #define LTQ_SPI_DMACON 0xEC /* DMA control */
51 #define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */
52 #define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */
53 #define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */
55 #define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */
56 #define LTQ_SPI_CLC_SMC_MASK 0xFF
57 #define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */
58 #define LTQ_SPI_CLC_RMC_MASK 0xFF
59 #define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
60 #define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
62 #define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */
63 #define LTQ_SPI_ID_TXFS_MASK 0x3F
64 #define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */
65 #define LTQ_SPI_ID_RXFS_MASK 0x3F
66 #define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */
67 #define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */
69 #define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */
70 #define LTQ_SPI_CON_BM_MASK 0x1F
71 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
72 #define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
73 #define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
74 #define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
75 #define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
76 #define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
77 #define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
78 #define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
79 #define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
80 #define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
81 #define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
82 #define LTQ_SPI_CON_HB BIT(4) /* Heading control */
83 #define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
84 #define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
86 #define LTQ_SPI_STAT_RXBV_MASK 0x7
87 #define LTQ_SPI_STAT_RXBV_SHIFT 28
88 #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
89 #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
90 #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
91 #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
92 #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
93 #define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
94 #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
95 #define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
97 #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
98 #define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
99 #define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
100 #define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
101 #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
102 #define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
103 #define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
104 #define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
105 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
106 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
107 #define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
108 #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
109 #define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
110 #define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
111 #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
112 #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
113 #define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
115 #define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */
116 #define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F
117 #define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
118 #define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
120 #define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */
121 #define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F
122 #define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
123 #define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
125 #define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
126 #define LTQ_SPI_FSTAT_RXFFL_SHIFT 0
127 #define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f
128 #define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
130 #define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8
131 #define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0
133 #define LTQ_SPI_FGPO_SETOUTN_SHIFT 8
134 #define LTQ_SPI_FGPO_CLROUTN_SHIFT 0
136 #define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */
137 #define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */
139 #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
140 #define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
141 #define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */
142 #define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */
143 #define LTQ_SPI_IRNEN_ALL 0xF
145 /* Hard-wired GPIOs used by SPI controller */
146 #define LTQ_SPI_GPIO_DI (ltq_is_ase()? 8 : 16)
147 #define LTQ_SPI_GPIO_DO (ltq_is_ase()? 9 : 17)
148 #define LTQ_SPI_GPIO_CLK (ltq_is_ase()? 10 : 18)
151 struct spi_bitbang bitbang;
152 struct completion done;
168 struct spi_transfer *curr_transfer;
170 u32 (*get_tx) (struct ltq_spi *);
174 unsigned dma_support:1;
179 struct ltq_spi_controller_state {
180 void (*cs_activate) (struct spi_device *);
181 void (*cs_deactivate) (struct spi_device *);
184 struct ltq_spi_irq_map {
186 irq_handler_t handler;
189 struct ltq_spi_cs_gpio_map {
194 static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
196 return spi_master_get_devdata(spi->master);
199 static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
201 return ioread32be(hw->base + reg);
204 static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
206 iowrite32be(val, hw->base + reg);
209 static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
213 val = ltq_spi_reg_read(hw, reg);
215 ltq_spi_reg_write(hw, val, reg);
218 static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
222 val = ltq_spi_reg_read(hw, reg);
224 ltq_spi_reg_write(hw, val, reg);
227 static void ltq_spi_hw_enable(struct ltq_spi *hw)
232 clk_enable(hw->spiclk);
235 * Set clock divider for run mode to 1 to
236 * run at same frequency as FPI bus
238 clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
239 ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
242 static void ltq_spi_hw_disable(struct ltq_spi *hw)
244 /* Set clock divider to 0 and set module disable bit */
245 ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
247 /* Power-down mdule */
248 clk_disable(hw->spiclk);
251 static void ltq_spi_reset_fifos(struct ltq_spi *hw)
256 * Enable and flush FIFOs. Set interrupt trigger level to
257 * half of FIFO count implemented in hardware.
260 val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
261 val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
262 ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
266 val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
267 val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
268 ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
272 static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
275 unsigned long timeout;
277 timeout = jiffies + msecs_to_jiffies(200);
280 stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
281 if (!(stat & LTQ_SPI_STAT_BSY))
285 } while (!time_after_eq(jiffies, timeout));
287 dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat);
292 static void ltq_spi_config_mode_set(struct ltq_spi *hw)
298 * Putting the SPI module in config mode is only safe if no
299 * transfer is in progress as indicated by busy flag STATE.BSY.
301 if (ltq_spi_wait_ready(hw)) {
302 ltq_spi_reset_fifos(hw);
303 hw->status = -ETIMEDOUT;
305 ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
310 static void ltq_spi_run_mode_set(struct ltq_spi *hw)
315 ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
320 static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
322 const u8 *tx = hw->tx;
331 static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
333 const u16 *tx = (u16 *) hw->tx;
342 static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
344 const u32 *tx = (u32 *) hw->tx;
353 static void ltq_spi_bits_per_word_set(struct spi_device *spi)
355 struct ltq_spi *hw = ltq_spi_to_hw(spi);
357 u8 bits_per_word = spi->bits_per_word;
360 * Use either default value of SPI device or value
361 * from current transfer.
363 if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
364 bits_per_word = hw->curr_transfer->bits_per_word;
366 if (bits_per_word <= 8)
367 hw->get_tx = ltq_spi_tx_word_u8;
368 else if (bits_per_word <= 16)
369 hw->get_tx = ltq_spi_tx_word_u16;
370 else if (bits_per_word <= 32)
371 hw->get_tx = ltq_spi_tx_word_u32;
373 /* CON.BM value = bits_per_word - 1 */
374 bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
376 ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
377 LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
378 ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
381 static void ltq_spi_speed_set(struct spi_device *spi)
383 struct ltq_spi *hw = ltq_spi_to_hw(spi);
384 u32 br, max_speed_hz, spi_clk;
385 u32 speed_hz = spi->max_speed_hz;
388 * Use either default value of SPI device or value
389 * from current transfer.
391 if (hw->curr_transfer && hw->curr_transfer->speed_hz)
392 speed_hz = hw->curr_transfer->speed_hz;
395 * SPI module clock is derived from FPI bus clock dependent on
396 * divider value in CLC.RMS which is always set to 1.
398 spi_clk = clk_get_rate(hw->fpiclk);
401 * Maximum SPI clock frequency in master mode is half of
402 * SPI module clock frequency. Maximum reload value of
403 * baudrate generator BR is 2^16.
405 max_speed_hz = spi_clk / 2;
406 if (speed_hz >= max_speed_hz)
409 br = (max_speed_hz / speed_hz) - 1;
414 ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
417 static void ltq_spi_clockmode_set(struct spi_device *spi)
419 struct ltq_spi *hw = ltq_spi_to_hw(spi);
422 con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
425 * SPI mode mapping in CON register:
426 * Mode CPOL CPHA CON.PO CON.PH
432 if (spi->mode & SPI_CPHA)
433 con &= ~LTQ_SPI_CON_PH;
435 con |= LTQ_SPI_CON_PH;
437 if (spi->mode & SPI_CPOL)
438 con |= LTQ_SPI_CON_PO;
440 con &= ~LTQ_SPI_CON_PO;
442 /* Set heading control */
443 if (spi->mode & SPI_LSB_FIRST)
444 con &= ~LTQ_SPI_CON_HB;
446 con |= LTQ_SPI_CON_HB;
448 ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
451 static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
455 con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
458 if (t->tx_buf && t->rx_buf) {
459 con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
460 } else if (t->rx_buf) {
461 con &= ~LTQ_SPI_CON_RXOFF;
462 con |= LTQ_SPI_CON_TXOFF;
463 } else if (t->tx_buf) {
464 con &= ~LTQ_SPI_CON_TXOFF;
465 con |= LTQ_SPI_CON_RXOFF;
468 con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
470 ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
473 static void ltq_spi_gpio_cs_activate(struct spi_device *spi)
475 struct ltq_spi_controller_data *cdata = spi->controller_data;
476 int val = spi->mode & SPI_CS_HIGH ? 1 : 0;
478 gpio_set_value(cdata->gpio, val);
481 static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi)
483 struct ltq_spi_controller_data *cdata = spi->controller_data;
484 int val = spi->mode & SPI_CS_HIGH ? 0 : 1;
486 gpio_set_value(cdata->gpio, val);
489 static void ltq_spi_internal_cs_activate(struct spi_device *spi)
491 struct ltq_spi *hw = ltq_spi_to_hw(spi);
494 fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
495 ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
498 static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
500 struct ltq_spi *hw = ltq_spi_to_hw(spi);
503 fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
504 ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
507 static void ltq_spi_chipselect(struct spi_device *spi, int cs)
509 struct ltq_spi *hw = ltq_spi_to_hw(spi);
510 struct ltq_spi_controller_state *cstate = spi->controller_state;
513 case BITBANG_CS_ACTIVE:
514 ltq_spi_bits_per_word_set(spi);
515 ltq_spi_speed_set(spi);
516 ltq_spi_clockmode_set(spi);
517 ltq_spi_run_mode_set(hw);
519 cstate->cs_activate(spi);
522 case BITBANG_CS_INACTIVE:
523 cstate->cs_deactivate(spi);
525 ltq_spi_config_mode_set(hw);
531 static int ltq_spi_setup_transfer(struct spi_device *spi,
532 struct spi_transfer *t)
534 struct ltq_spi *hw = ltq_spi_to_hw(spi);
535 u8 bits_per_word = spi->bits_per_word;
537 hw->curr_transfer = t;
539 if (t && t->bits_per_word)
540 bits_per_word = t->bits_per_word;
542 if (bits_per_word > 32)
545 ltq_spi_config_mode_set(hw);
550 static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = {
559 static const struct ltq_spi_cs_gpio_map ltq_spi_cs_ase[] = {
565 static int ltq_spi_setup(struct spi_device *spi)
567 struct ltq_spi *hw = ltq_spi_to_hw(spi);
568 struct ltq_spi_controller_data *cdata = spi->controller_data;
569 struct ltq_spi_controller_state *cstate;
573 /* Set default word length to 8 if not set */
574 if (!spi->bits_per_word)
575 spi->bits_per_word = 8;
577 if (spi->bits_per_word > 32)
580 if (!spi->controller_state) {
581 cstate = kzalloc(sizeof(struct ltq_spi_controller_state),
586 spi->controller_state = cstate;
591 * Up to six GPIOs can be connected to the SPI module
592 * via GPIO alternate function to control the chip select lines.
593 * For more flexibility in board layout this driver can also control
594 * the CS lines via GPIO API. If GPIOs should be used, board setup code
595 * have to register the SPI device with struct ltq_spi_controller_data
598 if (cdata && cdata->gpio) {
599 ret = gpio_request(cdata->gpio, "spi-cs");
603 ret = spi->mode & SPI_CS_HIGH ? 0 : 1;
604 gpio_direction_output(cdata->gpio, ret);
606 cstate->cs_activate = ltq_spi_gpio_cs_activate;
607 cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate;
609 struct ltq_spi_cs_gpio_map *cs_map =
610 ltq_is_ase() ? ltq_spi_cs_ase : ltq_spi_cs;
611 ret = ltq_gpio_request(&spi->dev, cs_map[spi->chip_select].gpio,
612 cs_map[spi->chip_select].mux,
617 gpocon = (1 << (spi->chip_select +
618 LTQ_SPI_GPOCON_ISCSBN_SHIFT));
620 if (spi->mode & SPI_CS_HIGH)
621 gpocon |= (1 << spi->chip_select);
623 fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
625 ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
626 ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
628 cstate->cs_activate = ltq_spi_internal_cs_activate;
629 cstate->cs_deactivate = ltq_spi_internal_cs_deactivate;
635 static void ltq_spi_cleanup(struct spi_device *spi)
637 struct ltq_spi_controller_data *cdata = spi->controller_data;
638 struct ltq_spi_controller_state *cstate = spi->controller_state;
641 if (cdata && cdata->gpio)
644 gpio = ltq_is_ase() ? ltq_spi_cs_ase[spi->chip_select].gpio :
645 ltq_spi_cs[spi->chip_select].gpio;
651 static void ltq_spi_txfifo_write(struct ltq_spi *hw)
656 /* Determine how much FIFOs are free for TX data */
657 fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
658 fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
659 LTQ_SPI_FSTAT_TXFFL_MASK);
664 while (hw->tx_cnt < hw->len && fifo_space) {
665 data = hw->get_tx(hw);
666 ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
671 static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
673 u32 fstat, data, *rx32;
675 u8 rxbv, shift, *rx8;
677 /* Determine how much FIFOs are filled with RX data */
678 fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
679 fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
680 & LTQ_SPI_FSTAT_RXFFL_MASK);
686 * The 32 bit FIFO is always used completely independent from the
687 * bits_per_word value. Thus four bytes have to be read at once
690 rx32 = (u32 *) hw->rx;
691 while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
692 *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
699 * If there are remaining bytes, read byte count from STAT.RXBV
700 * register and read the data byte-wise.
702 while (fifo_fill && hw->rx_cnt < hw->len) {
703 rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
704 LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
705 data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
707 shift = (rxbv - 1) * 8;
711 *rx8++ = (data >> shift) & 0xFF;
722 static void ltq_spi_rxreq_set(struct ltq_spi *hw)
724 u32 rxreq, rxreq_max, rxtodo;
726 rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
729 * In RX-only mode the serial clock is activated only after writing
730 * the expected amount of RX bytes into RXREQ register.
731 * To avoid receive overflows at high clocks it is better to request
732 * only the amount of bytes that fits into all FIFOs. This value
733 * depends on the FIFO size implemented in hardware.
735 rxreq = hw->len - hw->rx_cnt;
736 rxreq_max = hw->rxfs << 2;
737 rxreq = min(rxreq_max, rxreq);
739 if (!rxtodo && rxreq)
740 ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
743 static inline void ltq_spi_complete(struct ltq_spi *hw)
748 irqreturn_t ltq_spi_tx_irq(int irq, void *data)
750 struct ltq_spi *hw = data;
754 spin_lock_irqsave(&hw->lock, flags);
756 if (hw->tx_cnt < hw->len)
757 ltq_spi_txfifo_write(hw);
759 if (hw->tx_cnt == hw->len)
762 spin_unlock_irqrestore(&hw->lock, flags);
765 ltq_spi_complete(hw);
770 irqreturn_t ltq_spi_rx_irq(int irq, void *data)
772 struct ltq_spi *hw = data;
776 spin_lock_irqsave(&hw->lock, flags);
778 if (hw->rx_cnt < hw->len) {
779 ltq_spi_rxfifo_read(hw);
781 if (hw->tx && hw->tx_cnt < hw->len)
782 ltq_spi_txfifo_write(hw);
785 if (hw->rx_cnt == hw->len)
788 ltq_spi_rxreq_set(hw);
790 spin_unlock_irqrestore(&hw->lock, flags);
793 ltq_spi_complete(hw);
798 irqreturn_t ltq_spi_err_irq(int irq, void *data)
800 struct ltq_spi *hw = data;
803 spin_lock_irqsave(&hw->lock, flags);
805 /* Disable all interrupts */
806 ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
808 /* Clear all error flags */
809 ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
812 ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
813 ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
816 spin_unlock_irqrestore(&hw->lock, flags);
818 ltq_spi_complete(hw);
823 static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
825 struct ltq_spi *hw = ltq_spi_to_hw(spi);
834 INIT_COMPLETION(hw->done);
836 ltq_spi_xmit_set(hw, t);
838 /* Enable error interrupts */
839 ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
842 /* Initially fill TX FIFO with as much data as possible */
843 ltq_spi_txfifo_write(hw);
844 irq_flags |= LTQ_SPI_IRNEN_T;
846 /* Always enable RX interrupt in Full Duplex mode */
848 irq_flags |= LTQ_SPI_IRNEN_R;
851 ltq_spi_rxreq_set(hw);
853 /* Enable RX interrupt to receive data from RX FIFOs */
854 irq_flags |= LTQ_SPI_IRNEN_R;
857 /* Enable TX or RX interrupts */
858 ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
859 wait_for_completion_interruptible(&hw->done);
861 /* Disable all interrupts */
862 ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
865 * Return length of current transfer for bitbang utility code if
866 * no errors occured during transmission.
869 hw->status = hw->len;
874 static const struct ltq_spi_irq_map ltq_spi_irqs[] = {
875 { "spi_tx", ltq_spi_tx_irq },
876 { "spi_rx", ltq_spi_rx_irq },
877 { "spi_err", ltq_spi_err_irq },
881 ltq_spi_probe(struct platform_device *pdev)
883 struct spi_master *master;
886 struct ltq_spi_platform_data *pdata = pdev->dev.platform_data;
890 master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
892 dev_err(&pdev->dev, "spi_alloc_master\n");
897 hw = spi_master_get_devdata(master);
899 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
901 dev_err(&pdev->dev, "platform_get_resource\n");
906 r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
909 dev_err(&pdev->dev, "devm_request_mem_region\n");
914 hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
916 dev_err(&pdev->dev, "devm_ioremap_nocache\n");
921 hw->fpiclk = clk_get_fpi();
922 if (IS_ERR(hw->fpiclk)) {
923 dev_err(&pdev->dev, "fpi clk\n");
924 ret = PTR_ERR(hw->fpiclk);
928 hw->spiclk = clk_get(&pdev->dev, NULL);
929 if (IS_ERR(hw->spiclk)) {
930 dev_err(&pdev->dev, "spi clk\n");
931 ret = PTR_ERR(hw->spiclk);
935 memset(hw->irq, 0, sizeof(hw->irq));
936 for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
937 ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name);
939 dev_err(&pdev->dev, "platform_get_irq_byname\n");
944 ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
945 0, ltq_spi_irqs[i].name, hw);
947 dev_err(&pdev->dev, "request_irq\n");
952 hw->bitbang.master = spi_master_get(master);
953 hw->bitbang.chipselect = ltq_spi_chipselect;
954 hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
955 hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
957 master->bus_num = pdev->id;
958 master->num_chipselect = pdata->num_chipselect;
959 master->setup = ltq_spi_setup;
960 master->cleanup = ltq_spi_cleanup;
962 hw->dev = &pdev->dev;
963 init_completion(&hw->done);
964 spin_lock_init(&hw->lock);
966 /* Set GPIO alternate functions to SPI */
967 ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DI, 2, 0, "spi-di");
968 ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DO, 2, 1, "spi-do");
969 ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_CLK, 2, 1, "spi-clk");
971 ltq_spi_hw_enable(hw);
973 /* Read module capabilities */
974 id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
975 hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
976 hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
977 hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
979 ltq_spi_config_mode_set(hw);
981 /* Enable error checking, disable TX/RX, set idle value high */
982 data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
983 LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
984 LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
985 ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
987 /* Enable master mode and clear error flags */
988 ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
989 LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
991 /* Reset GPIO/CS registers */
992 ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
993 ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
995 /* Enable and flush FIFOs */
996 ltq_spi_reset_fifos(hw);
998 ret = spi_bitbang_start(&hw->bitbang);
1000 dev_err(&pdev->dev, "spi_bitbang_start\n");
1004 platform_set_drvdata(pdev, hw);
1006 pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
1007 id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
1012 ltq_spi_hw_disable(hw);
1015 clk_put(hw->fpiclk);
1018 free_irq(hw->irq[i], hw);
1021 spi_master_put(master);
1027 static int __devexit
1028 ltq_spi_remove(struct platform_device *pdev)
1030 struct ltq_spi *hw = platform_get_drvdata(pdev);
1033 ret = spi_bitbang_stop(&hw->bitbang);
1037 platform_set_drvdata(pdev, NULL);
1039 ltq_spi_config_mode_set(hw);
1040 ltq_spi_hw_disable(hw);
1042 for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
1044 free_irq(hw->irq[i], hw);
1046 gpio_free(LTQ_SPI_GPIO_DI);
1047 gpio_free(LTQ_SPI_GPIO_DO);
1048 gpio_free(LTQ_SPI_GPIO_CLK);
1050 clk_put(hw->fpiclk);
1051 spi_master_put(hw->bitbang.master);
1056 static struct platform_driver ltq_spi_driver = {
1057 .probe = ltq_spi_probe,
1058 .remove = __devexit_p(ltq_spi_remove),
1061 .owner = THIS_MODULE,
1065 module_platform_driver(ltq_spi_driver);
1067 MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1068 MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1069 MODULE_LICENSE("GPL");
1070 MODULE_ALIAS("platform:ltq-spi");