target/linux/lantiq/files/drivers/spi/spi-falcon.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/delay.h>
  14 #include <linux/workqueue.h>
  15
  16 #include <lantiq_soc.h>
  17
  18 #define DRV_NAME                        "falcon_spi"
  19
  20 #define FALCON_SPI_XFER_BEGIN           (1 << 0)
  21 #define FALCON_SPI_XFER_END             (1 << 1)
  22
  23 /* Bus Read Configuration Register0 */
  24 #define LTQ_BUSRCON0    0x00000010
  25 /* Bus Write Configuration Register0 */
  26 #define LTQ_BUSWCON0    0x00000018
  27 /* Serial Flash Configuration Register */
  28 #define LTQ_SFCON       0x00000080
  29 /* Serial Flash Time Register */
  30 #define LTQ_SFTIME      0x00000084
  31 /* Serial Flash Status Register */
  32 #define LTQ_SFSTAT      0x00000088
  33 /* Serial Flash Command Register */
  34 #define LTQ_SFCMD       0x0000008C
  35 /* Serial Flash Address Register */
  36 #define LTQ_SFADDR      0x00000090
  37 /* Serial Flash Data Register */
  38 #define LTQ_SFDATA      0x00000094
  39 /* Serial Flash I/O Control Register */
  40 #define LTQ_SFIO        0x00000098
  41 /* EBU Clock Control Register */
  42 #define LTQ_EBUCC       0x000000C4
  43
  44 /* Dummy Phase Length */
  45 #define SFCMD_DUMLEN_OFFSET     16
  46 #define SFCMD_DUMLEN_MASK       0x000F0000
  47 /* Chip Select */
  48 #define SFCMD_CS_OFFSET         24
  49 #define SFCMD_CS_MASK           0x07000000
  50 /* field offset */
  51 #define SFCMD_ALEN_OFFSET       20
  52 #define SFCMD_ALEN_MASK         0x00700000
  53 /* SCK Rise-edge Position */
  54 #define SFTIME_SCKR_POS_OFFSET  8
  55 #define SFTIME_SCKR_POS_MASK    0x00000F00
  56 /* SCK Period */
  57 #define SFTIME_SCK_PER_OFFSET   0
  58 #define SFTIME_SCK_PER_MASK     0x0000000F
  59 /* SCK Fall-edge Position */
  60 #define SFTIME_SCKF_POS_OFFSET  12
  61 #define SFTIME_SCKF_POS_MASK    0x0000F000
  62 /* Device Size */
  63 #define SFCON_DEV_SIZE_A23_0    0x03000000
  64 #define SFCON_DEV_SIZE_MASK     0x0F000000
  65 /* Read Data Position */
  66 #define SFTIME_RD_POS_MASK      0x000F0000
  67 /* Data Output */
  68 #define SFIO_UNUSED_WD_MASK     0x0000000F
  69 /* Command Opcode mask */
  70 #define SFCMD_OPC_MASK          0x000000FF
  71 /* dlen bytes of data to write */
  72 #define SFCMD_DIR_WRITE         0x00000100
  73 /* Data Length offset */
  74 #define SFCMD_DLEN_OFFSET       9
  75 /* Command Error */
  76 #define SFSTAT_CMD_ERR          0x20000000
  77 /* Access Command Pending */
  78 #define SFSTAT_CMD_PEND         0x00400000
  79 /* Frequency set to 100MHz. */
  80 #define EBUCC_EBUDIV_SELF100    0x00000001
  81 /* Serial Flash */
  82 #define BUSRCON0_AGEN_SERIAL_FLASH      0xF0000000
  83 /* 8-bit multiplexed */
  84 #define BUSRCON0_PORTW_8_BIT_MUX        0x00000000
  85 /* Serial Flash */
  86 #define BUSWCON0_AGEN_SERIAL_FLASH      0xF0000000
  87 /* Chip Select after opcode */
  88 #define SFCMD_KEEP_CS_KEEP_SELECTED     0x00008000
  89
  90 struct falcon_spi {
  91         u32 sfcmd; /* for caching of opcode, direction, ... */
  92         struct spi_master *master;
  93 };
  94
  95 int
  96 falcon_spi_xfer(struct spi_device *spi,
  97                     struct spi_transfer *t,
  98                     unsigned long flags)
  99 {
 100         struct device *dev = &spi->dev;
 101         struct falcon_spi *priv = spi_master_get_devdata(spi->master);
 102         const u8 *txp = t->tx_buf;
 103         u8 *rxp = t->rx_buf;
 104         unsigned int bytelen = ((8 * t->len + 7) / 8);
 105         unsigned int len, alen, dumlen;
 106         u32 val;
 107         enum {
 108                 state_init,
 109                 state_command_prepare,
 110                 state_write,
 111                 state_read,
 112                 state_disable_cs,
 113                 state_end
 114         } state = state_init;
 115
 116         do {
 117                 switch (state) {
 118                 case state_init: /* detect phase of upper layer sequence */
 119                 {
 120                         /* initial write ? */
 121                         if (flags & FALCON_SPI_XFER_BEGIN) {
 122                                 if (!txp) {
 123                                         dev_err(dev,
 124                                                 "BEGIN without tx data!\n");
 125                                         return -1;
 126                                 }
 127                                 /*
 128                                  * Prepare the parts of the sfcmd register,
 129                                  * which should not
 130                                  * change during a sequence!
 131                                  * Only exception are the length fields,
 132                                  * especially alen and dumlen.
 133                                  */
 134
 135                                 priv->sfcmd = ((spi->chip_select
 136                                                 << SFCMD_CS_OFFSET)
 137                                                & SFCMD_CS_MASK);
 138                                 priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
 139                                 priv->sfcmd |= *txp;
 140                                 txp++;
 141                                 bytelen--;
 142                                 if (bytelen) {
 143                                         /*
 144                                          * more data:
 145                                          * maybe address and/or dummy
 146                                          */
 147                                         state = state_command_prepare;
 148                                         break;
 149                                 } else {
 150                                         dev_dbg(dev, "write cmd %02X\n",
 151                                                 priv->sfcmd & SFCMD_OPC_MASK);
 152                                 }
 153                         }
 154                         /* continued write ? */
 155                         if (txp && bytelen) {
 156                                 state = state_write;
 157                                 break;
 158                         }
 159                         /* read data? */
 160                         if (rxp && bytelen) {
 161                                 state = state_read;
 162                                 break;
 163                         }
 164                         /* end of sequence? */
 165                         if (flags & FALCON_SPI_XFER_END)
 166                                 state = state_disable_cs;
 167                         else
 168                                 state = state_end;
 169                         break;
 170                 }
 171                 /* collect tx data for address and dummy phase */
 172                 case state_command_prepare:
 173                 {
 174                         /* txp is valid, already checked */
 175                         val = 0;
 176                         alen = 0;
 177                         dumlen = 0;
 178                         while (bytelen > 0) {
 179                                 if (alen < 3) {
 180                                         val = (val<<8)|(*txp++);
 181                                         alen++;
 182                                 } else if ((dumlen < 15) && (*txp == 0)) {
 183                                         /*
 184                                          * assume dummy bytes are set to 0
 185                                          * from upper layer
 186                                          */
 187                                         dumlen++;
 188                                         txp++;
 189                                 } else
 190                                         break;
 191                                 bytelen--;
 192                         }
 193                         priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
 194                         priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
 195                                          (dumlen << SFCMD_DUMLEN_OFFSET);
 196                         if (alen > 0)
 197                                 ltq_ebu_w32(val, LTQ_SFADDR);
 198
 199                         dev_dbg(dev, "write cmd %02X, alen=%d "
 200                                 "(addr=%06X) dumlen=%d\n",
 201                                 priv->sfcmd & SFCMD_OPC_MASK,
 202                                 alen, val, dumlen);
 203
 204                         if (bytelen > 0) {
 205                                 /* continue with write */
 206                                 state = state_write;
 207                         } else if (flags & FALCON_SPI_XFER_END) {
 208                                 /* end of sequence? */
 209                                 state = state_disable_cs;
 210                         } else {
 211                                 /*
 212                                  * go to end and expect another
 213                                  * call (read or write)
 214                                  */
 215                                 state = state_end;
 216                         }
 217                         break;
 218                 }
 219                 case state_write:
 220                 {
 221                         /* txp still valid */
 222                         priv->sfcmd |= SFCMD_DIR_WRITE;
 223                         len = 0;
 224                         val = 0;
 225                         do {
 226                                 if (bytelen--)
 227                                         val |= (*txp++) << (8 * len++);
 228                                 if ((flags & FALCON_SPI_XFER_END)
 229                                     && (bytelen == 0)) {
 230                                         priv->sfcmd &=
 231                                                 ~SFCMD_KEEP_CS_KEEP_SELECTED;
 232                                 }
 233                                 if ((len == 4) || (bytelen == 0)) {
 234                                         ltq_ebu_w32(val, LTQ_SFDATA);
 235                                         ltq_ebu_w32(priv->sfcmd
 236                                                 | (len<<SFCMD_DLEN_OFFSET),
 237                                                 LTQ_SFCMD);
 238                                         len = 0;
 239                                         val = 0;
 240                                         priv->sfcmd &= ~(SFCMD_ALEN_MASK
 241                                                          | SFCMD_DUMLEN_MASK);
 242                                 }
 243                         } while (bytelen);
 244                         state = state_end;
 245                         break;
 246                 }
 247                 case state_read:
 248                 {
 249                         /* read data */
 250                         priv->sfcmd &= ~SFCMD_DIR_WRITE;
 251                         do {
 252                                 if ((flags & FALCON_SPI_XFER_END)
 253                                     && (bytelen <= 4)) {
 254                                         priv->sfcmd &=
 255                                                 ~SFCMD_KEEP_CS_KEEP_SELECTED;
 256                                 }
 257                                 len = (bytelen > 4) ? 4 : bytelen;
 258                                 bytelen -= len;
 259                                 ltq_ebu_w32(priv->sfcmd
 260                                         |(len<<SFCMD_DLEN_OFFSET), LTQ_SFCMD);
 261                                 priv->sfcmd &= ~(SFCMD_ALEN_MASK
 262                                                  | SFCMD_DUMLEN_MASK);
 263                                 do {
 264                                         val = ltq_ebu_r32(LTQ_SFSTAT);
 265                                         if (val & SFSTAT_CMD_ERR) {
 266                                                 /* reset error status */
 267                                                 dev_err(dev, "SFSTAT: CMD_ERR "
 268                                                         "(%x)\n", val);
 269                                                 ltq_ebu_w32(SFSTAT_CMD_ERR,
 270                                                         LTQ_SFSTAT);
 271                                                 return -1;
 272                                         }
 273                                 } while (val & SFSTAT_CMD_PEND);
 274                                 val = ltq_ebu_r32(LTQ_SFDATA);
 275                                 do {
 276                                         *rxp = (val & 0xFF);
 277                                         rxp++;
 278                                         val >>= 8;
 279                                         len--;
 280                                 } while (len);
 281                         } while (bytelen);
 282                         state = state_end;
 283                         break;
 284                 }
 285                 case state_disable_cs:
 286                 {
 287                         priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
 288                         ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
 289                                 LTQ_SFCMD);
 290                         val = ltq_ebu_r32(LTQ_SFSTAT);
 291                         if (val & SFSTAT_CMD_ERR) {
 292                                 /* reset error status */
 293                                 dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
 294                                 ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT);
 295                                 return -1;
 296                         }
 297                         state = state_end;
 298                         break;
 299                 }
 300                 case state_end:
 301                         break;
 302                 }
 303         } while (state != state_end);
 304
 305         return 0;
 306 }
 307
 308 static int
 309 falcon_spi_setup(struct spi_device *spi)
 310 {
 311         struct device *dev = &spi->dev;
 312         const u32 ebuclk = 100000000;
 313         unsigned int i;
 314         unsigned long flags;
 315
 316         dev_dbg(dev, "setup\n");
 317
 318         if (spi->master->bus_num > 0 || spi->chip_select > 0)
 319                 return -ENODEV;
 320
 321         spin_lock_irqsave(&ebu_lock, flags);
 322
 323         if (ebuclk < spi->max_speed_hz) {
 324                 /* set EBU clock to 100 MHz */
 325                 ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC);
 326                 i = 1; /* divider */
 327         } else {
 328                 /* set EBU clock to 50 MHz */
 329                 ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC);
 330
 331                 /* search for suitable divider */
 332                 for (i = 1; i < 7; i++) {
 333                         if (ebuclk / i <= spi->max_speed_hz)
 334                                 break;
 335                 }
 336         }
 337
 338         /* setup period of serial clock */
 339         ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
 340                      | SFTIME_SCKR_POS_MASK
 341                      | SFTIME_SCK_PER_MASK,
 342                      (i << SFTIME_SCKR_POS_OFFSET)
 343                      | (i << (SFTIME_SCK_PER_OFFSET + 1)),
 344                      LTQ_SFTIME);
 345
 346         /*
 347          * set some bits of unused_wd, to not trigger HOLD/WP
 348          * signals on non QUAD flashes
 349          */
 350         ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO);
 351
 352         ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
 353                 LTQ_BUSRCON0);
 354         ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0);
 355         /* set address wrap around to maximum for 24-bit addresses */
 356         ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON);
 357
 358         spin_unlock_irqrestore(&ebu_lock, flags);
 359
 360         return 0;
 361 }
 362
 363 static int
 364 falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
 365 {
 366         struct falcon_spi *priv = spi_master_get_devdata(spi->master);
 367         struct spi_transfer *t;
 368         unsigned long spi_flags;
 369         unsigned long flags;
 370         int ret = 0;
 371
 372         priv->sfcmd = 0;
 373         m->actual_length = 0;
 374
 375         spi_flags = FALCON_SPI_XFER_BEGIN;
 376         list_for_each_entry(t, &m->transfers, transfer_list) {
 377                 if (list_is_last(&t->transfer_list, &m->transfers))
 378                         spi_flags |= FALCON_SPI_XFER_END;
 379
 380                 spin_lock_irqsave(&ebu_lock, flags);
 381                 ret = falcon_spi_xfer(spi, t, spi_flags);
 382                 spin_unlock_irqrestore(&ebu_lock, flags);
 383
 384                 if (ret)
 385                         break;
 386
 387                 m->actual_length += t->len;
 388
 389                 if (t->delay_usecs || t->cs_change)
 390                         BUG();
 391
 392                 spi_flags = 0;
 393         }
 394
 395         m->status = ret;
 396         m->complete(m->context);
 397
 398         return 0;
 399 }
 400
 401 static void
 402 falcon_spi_cleanup(struct spi_device *spi)
 403 {
 404         struct device *dev = &spi->dev;
 405
 406         dev_dbg(dev, "cleanup\n");
 407 }
 408
 409 static int __devinit
 410 falcon_spi_probe(struct platform_device *pdev)
 411 {
 412         struct device *dev = &pdev->dev;
 413         struct falcon_spi *priv;
 414         struct spi_master *master;
 415         int ret;
 416
 417         dev_dbg(dev, "probing\n");
 418
 419         master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 420         if (!master) {
 421                 dev_err(dev, "no memory for spi_master\n");
 422                 return -ENOMEM;
 423         }
 424
 425         priv = spi_master_get_devdata(master);
 426         priv->master = master;
 427
 428         master->mode_bits = SPI_MODE_3;
 429         master->num_chipselect = 1;
 430         master->bus_num = 0;
 431
 432         master->setup = falcon_spi_setup;
 433         master->transfer = falcon_spi_transfer;
 434         master->cleanup = falcon_spi_cleanup;
 435
 436         platform_set_drvdata(pdev, priv);
 437
 438         ret = spi_register_master(master);
 439         if (ret)
 440                 spi_master_put(master);
 441
 442         return ret;
 443 }
 444
 445 static int __devexit
 446 falcon_spi_remove(struct platform_device *pdev)
 447 {
 448         struct device *dev = &pdev->dev;
 449         struct falcon_spi *priv = platform_get_drvdata(pdev);
 450
 451         dev_dbg(dev, "removed\n");
 452
 453         spi_unregister_master(priv->master);
 454
 455         return 0;
 456 }
 457
 458 static struct platform_driver falcon_spi_driver = {
 459         .probe  = falcon_spi_probe,
 460         .remove = __devexit_p(falcon_spi_remove),
 461         .driver = {
 462                 .name   = DRV_NAME,
 463                 .owner  = THIS_MODULE
 464         }
 465 };
 466
 467 static int __init
 468 falcon_spi_init(void)
 469 {
 470         return platform_driver_register(&falcon_spi_driver);
 471 }
 472
 473 static void __exit
 474 falcon_spi_exit(void)
 475 {
 476         platform_driver_unregister(&falcon_spi_driver);
 477 }
 478
 479 module_init(falcon_spi_init);
 480 module_exit(falcon_spi_exit);
 481
 482 MODULE_LICENSE("GPL");
 483 MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");