target/linux/ipq806x/patches/0159-arm-ipq8064-Add-USB3-DT-information.patch

   1 From 269a71c81438604d27f01ec703daa7f5e3f39e8b Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Sun, 15 Jun 2014 00:48:18 -0500
   4 Subject: [PATCH 159/182] arm: ipq8064: Add USB3 DT information
   5
   6 This patch fleshes out the USB3 specific information for the IPQ8064 platform.
   7
   8 Signed-off-by: Andy Gross <agross@codeaurora.org>
   9 ---
  10  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   29 ++++++++++
  11  arch/arm/boot/dts/qcom-ipq8064.dtsi      |   90 ++++++++++++++++++++++++++++++
  12  2 files changed, 119 insertions(+)
  13
  14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  16 @@ -160,5 +160,34 @@
  17                         pinctrl-0 = <&nand_pins>;
  18                         pinctrl-names = "default";
  19                 };
  20 +
  21 +               tcsr@1a400000 {
  22 +                       status = "ok";
  23 +                       qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  24 +               };
  25 +
  26 +               phy@100f8800 {          /* USB3 port 1 HS phy */
  27 +                       status = "ok";
  28 +               };
  29 +
  30 +               phy@100f8830 {          /* USB3 port 1 SS phy */
  31 +                       status = "ok";
  32 +               };
  33 +
  34 +               phy@110f8800 {          /* USB3 port 0 HS phy */
  35 +                       status = "ok";
  36 +               };
  37 +
  38 +               phy@110f8830 {          /* USB3 port 0 SS phy */
  39 +                       status = "ok";
  40 +               };
  41 +
  42 +               usb30@0 {
  43 +                       status = "ok";
  44 +               };
  45 +
  46 +               usb30@1 {
  47 +                       status = "ok";
  48 +               };
  49         };
  50  };
  51 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  52 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  53 @@ -4,6 +4,7 @@
  54  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  55  #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  56  #include <dt-bindings/soc/qcom,gsbi.h>
  57 +#include <dt-bindings/soc/qcom,tcsr.h>
  58
  59  / {
  60         model = "Qualcomm IPQ8064";
  61 @@ -402,5 +403,94 @@
  62
  63                         status = "disabled";
  64                 };
  65 +
  66 +               tcsr: tcsr@1a400000 {
  67 +                       compatible = "qcom,tcsr";
  68 +                       reg = <0x1a400000 0x100>;
  69 +
  70 +                       status = "disabled";
  71 +               };
  72 +
  73 +               hs_phy_1: phy@100f8800 {
  74 +                       compatible = "qcom,dwc3-hsphy";
  75 +                       reg = <0x100f8800 0x30>;
  76 +                       clocks = <&gcc USB30_1_UTMI_CLK>;
  77 +                       clock-names = "utmi";
  78 +
  79 +                       status = "disabled";
  80 +               };
  81 +
  82 +               ss_phy_1: phy@100f8830 {
  83 +                       compatible = "qcom,dwc3-ssphy";
  84 +                       reg = <0x100f8830 0x30>;
  85 +
  86 +                       clocks = <&gcc USB30_1_MASTER_CLK>;
  87 +                       clock-names = "ref";
  88 +
  89 +                       status = "disabled";
  90 +               };
  91 +
  92 +               hs_phy_0: phy@110f8800 {
  93 +                       compatible = "qcom,dwc3-hsphy";
  94 +                       reg = <0x110f8800 0x30>;
  95 +                       clocks = <&gcc USB30_0_UTMI_CLK>;
  96 +                       clock-names = "utmi";
  97 +
  98 +                       status = "disabled";
  99 +               };
 100 +
 101 +               ss_phy_0: phy@110f8830 {
 102 +                       compatible = "qcom,dwc3-ssphy";
 103 +                       reg = <0x110f8830 0x30>;
 104 +
 105 +                       clocks = <&gcc USB30_0_MASTER_CLK>;
 106 +                       clock-names = "ref";
 107 +
 108 +                       status = "disabled";
 109 +               };
 110 +
 111 +               usb3_0: usb30@0 {
 112 +                       compatible = "qcom,dwc3";
 113 +                       #address-cells = <1>;
 114 +                       #size-cells = <1>;
 115 +                       clocks = <&gcc USB30_0_MASTER_CLK>;
 116 +                       clock-names = "core";
 117 +
 118 +                       ranges;
 119 +
 120 +                       status = "disabled";
 121 +
 122 +                       dwc3@11000000 {
 123 +                               compatible = "snps,dwc3";
 124 +                               reg = <0x11000000 0xcd00>;
 125 +                               interrupts = <0 110 0x4>;
 126 +                               usb-phy = <&hs_phy_0>, <&ss_phy_0>;
 127 +                               phy-names = "usb2-phy", "usb3-phy";
 128 +                               tx-fifo-resize;
 129 +                               dr_mode = "host";
 130 +                       };
 131 +               };
 132 +
 133 +               usb3_1: usb30@1 {
 134 +                       compatible = "qcom,dwc3";
 135 +                       #address-cells = <1>;
 136 +                       #size-cells = <1>;
 137 +                       clocks = <&gcc USB30_1_MASTER_CLK>;
 138 +                       clock-names = "core";
 139 +
 140 +                       ranges;
 141 +
 142 +                       status = "disabled";
 143 +
 144 +                       dwc3@10000000 {
 145 +                               compatible = "snps,dwc3";
 146 +                               reg = <0x10000000 0xcd00>;
 147 +                               interrupts = <0 205 0x4>;
 148 +                               usb-phy = <&hs_phy_1>, <&ss_phy_1>;
 149 +                               phy-names = "usb2-phy", "usb3-phy";
 150 +                               tx-fifo-resize;
 151 +                               dr_mode = "host";
 152 +                       };
 153 +               };
 154         };
 155  };