target/linux/ipq806x/patches/0137-ARM-qcom-ipq8064-ap148-Add-SPI-related-bindings.patch

   1 From b9eaa80146abb09bcc7e6d8b33fca476453c839c Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Wed, 14 May 2014 22:01:16 -0500
   4 Subject: [PATCH 137/182] ARM: qcom-ipq8064-ap148: Add SPI related bindings
   5
   6 Signed-off-by: Andy Gross <agross@codeaurora.org>
   7 ---
   8  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   42 ++++++++++++++++++++++++++
   9  arch/arm/boot/dts/qcom-ipq8064.dtsi      |   47 ++++++++++++++++++++++++++++++
  10  2 files changed, 89 insertions(+)
  11
  12 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  13 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  14 @@ -20,6 +20,15 @@
  15                                 function = "gsbi4";
  16                                 bias-disable;
  17                         };
  18 +
  19 +                       spi_pins: spi_pins {
  20 +                               mux {
  21 +                                       pins = "gpio18", "gpio19", "gpio21";
  22 +                                       function = "gsbi5";
  23 +                                       drive-strength = <10>;
  24 +                                       bias-none;
  25 +                               };
  26 +                       };
  27                 };
  28
  29                 gsbi@16300000 {
  30 @@ -38,5 +47,38 @@
  31                                 pinctrl-names = "default";
  32                         };
  33                 };
  34 +
  35 +               gsbi5: gsbi@1a200000 {
  36 +                       qcom,mode = <GSBI_PROT_SPI>;
  37 +                       status = "ok";
  38 +
  39 +                       spi4: spi@1a280000 {
  40 +                               status = "ok";
  41 +                               spi-max-frequency = <50000000>;
  42 +
  43 +                               pinctrl-0 = <&spi_pins>;
  44 +                               pinctrl-names = "default";
  45 +
  46 +                               cs-gpios = <&qcom_pinmux 20 0>;
  47 +
  48 +                               flash: m25p80@0 {
  49 +                                       compatible = "s25fl256s1";
  50 +                                       #address-cells = <1>;
  51 +                                       #size-cells = <1>;
  52 +                                       spi-max-frequency = <50000000>;
  53 +                                       reg = <0>;
  54 +
  55 +                                       partition@0 {
  56 +                                               label = "rootfs";
  57 +                                               reg = <0x0 0x1000000>;
  58 +                                       };
  59 +
  60 +                                       partition@1 {
  61 +                                               label = "scratch";
  62 +                                               reg = <0x1000000 0x1000000>;
  63 +                                       };
  64 +                               };
  65 +                       };
  66 +               };
  67         };
  68  };
  69 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  70 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  71 @@ -187,6 +187,53 @@
  72                         };
  73                 };
  74
  75 +               gsbi5: gsbi@1a200000 {
  76 +                       compatible = "qcom,gsbi-v1.0.0";
  77 +                       reg = <0x1a200000 0x100>;
  78 +                       clocks = <&gcc GSBI5_H_CLK>;
  79 +                       clock-names = "iface";
  80 +                       #address-cells = <1>;
  81 +                       #size-cells = <1>;
  82 +                       ranges;
  83 +                       status = "disabled";
  84 +
  85 +                       serial@1a240000 {
  86 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  87 +                               reg = <0x1a240000 0x1000>,
  88 +                                     <0x1a200000 0x1000>;
  89 +                               interrupts = <0 154 0x0>;
  90 +                               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
  91 +                               clock-names = "core", "iface";
  92 +                               status = "disabled";
  93 +                       };
  94 +
  95 +                       i2c@1a280000 {
  96 +                               compatible = "qcom,i2c-qup-v1.1.1";
  97 +                               reg = <0x1a280000 0x1000>;
  98 +                               interrupts = <0 155 0>;
  99 +
 100 +                               clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 101 +                               clock-names = "core", "iface";
 102 +                               status = "disabled";
 103 +
 104 +                               #address-cells = <1>;
 105 +                               #size-cells = <0>;
 106 +                       };
 107 +
 108 +                       spi@1a280000 {
 109 +                               compatible = "qcom,spi-qup-v1.1.1";
 110 +                               reg = <0x1a280000 0x1000>;
 111 +                               interrupts = <0 155 0>;
 112 +
 113 +                               clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 114 +                               clock-names = "core", "iface";
 115 +                               status = "disabled";
 116 +
 117 +                               #address-cells = <1>;
 118 +                               #size-cells = <0>;
 119 +                       };
 120 +               };
 121 +
 122                 qcom,ssbi@500000 {
 123                         compatible = "qcom,ssbi";
 124                         reg = <0x00500000 0x1000>;