target/linux/ipq806x/patches/0092-ARM-dts-qcom-Update-msm8960-device-trees.patch

   1 From 881200420e6ece87d9abbb13c0653d26455cdbdd Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Wed, 28 May 2014 12:09:53 -0500
   4 Subject: [PATCH 092/182] ARM: dts: qcom: Update msm8960 device trees
   5
   6 * Move SoC peripherals into an SoC container node
   7 * Move serial enabling into board file (qcom-msm8960-cdp.dts)
   8 * Cleanup cpu node to match binding spec, enable-method and compatible
   9   should be per cpu, not part of the container
  10 * Drop interrupts property from l2-cache node as its not part of the
  11   binding spec
  12 * Add GSBI node and configuration of GSBI controller
  13
  14 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  15 ---
  16  arch/arm/boot/dts/qcom-msm8960-cdp.dts |   10 ++
  17  arch/arm/boot/dts/qcom-msm8960.dtsi    |  176 ++++++++++++++++++--------------
  18  2 files changed, 108 insertions(+), 78 deletions(-)
  19
  20 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
  21 +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
  22 @@ -3,4 +3,14 @@
  23  / {
  24         model = "Qualcomm MSM8960 CDP";
  25         compatible = "qcom,msm8960-cdp", "qcom,msm8960";
  26 +
  27 +       soc {
  28 +               gsbi@16400000 {
  29 +                       status = "ok";
  30 +                       qcom,mode = <GSBI_PROT_I2C_UART>;
  31 +                       serial@16440000 {
  32 +                               status = "ok";
  33 +                       };
  34 +               };
  35 +       };
  36  };
  37 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi
  38 +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
  39 @@ -3,6 +3,7 @@
  40  /include/ "skeleton.dtsi"
  41
  42  #include <dt-bindings/clock/qcom,gcc-msm8960.h>
  43 +#include <dt-bindings/soc/qcom,gsbi.h>
  44
  45  / {
  46         model = "Qualcomm MSM8960";
  47 @@ -13,10 +14,10 @@
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 interrupts = <1 14 0x304>;
  51 -               compatible = "qcom,krait";
  52 -               enable-method = "qcom,kpss-acc-v1";
  53
  54                 cpu@0 {
  55 +                       compatible = "qcom,krait";
  56 +                       enable-method = "qcom,kpss-acc-v1";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         next-level-cache = <&L2>;
  60 @@ -25,6 +26,8 @@
  61                 };
  62
  63                 cpu@1 {
  64 +                       compatible = "qcom,krait";
  65 +                       enable-method = "qcom,kpss-acc-v1";
  66                         device_type = "cpu";
  67                         reg = <1>;
  68                         next-level-cache = <&L2>;
  69 @@ -35,7 +38,6 @@
  70                 L2: l2-cache {
  71                         compatible = "cache";
  72                         cache-level = <2>;
  73 -                       interrupts = <0 2 0x4>;
  74                 };
  75         };
  76
  77 @@ -45,91 +47,109 @@
  78                 qcom,no-pc-write;
  79         };
  80
  81 -       intc: interrupt-controller@2000000 {
  82 -               compatible = "qcom,msm-qgic2";
  83 -               interrupt-controller;
  84 -               #interrupt-cells = <3>;
  85 -               reg = < 0x02000000 0x1000 >,
  86 -                     < 0x02002000 0x1000 >;
  87 -       };
  88 +       soc: soc {
  89 +               #address-cells = <1>;
  90 +               #size-cells = <1>;
  91 +               ranges;
  92 +               compatible = "simple-bus";
  93 +
  94 +               intc: interrupt-controller@2000000 {
  95 +                       compatible = "qcom,msm-qgic2";
  96 +                       interrupt-controller;
  97 +                       #interrupt-cells = <3>;
  98 +                       reg = <0x02000000 0x1000>,
  99 +                             <0x02002000 0x1000>;
 100 +               };
 101
 102 -       timer@200a000 {
 103 -               compatible = "qcom,kpss-timer", "qcom,msm-timer";
 104 -               interrupts = <1 1 0x301>,
 105 -                            <1 2 0x301>,
 106 -                            <1 3 0x301>;
 107 -               reg = <0x0200a000 0x100>;
 108 -               clock-frequency = <27000000>,
 109 -                                 <32768>;
 110 -               cpu-offset = <0x80000>;
 111 -       };
 112 +               timer@200a000 {
 113 +                       compatible = "qcom,kpss-timer", "qcom,msm-timer";
 114 +                       interrupts = <1 1 0x301>,
 115 +                                    <1 2 0x301>,
 116 +                                    <1 3 0x301>;
 117 +                       reg = <0x0200a000 0x100>;
 118 +                       clock-frequency = <27000000>,
 119 +                                         <32768>;
 120 +                       cpu-offset = <0x80000>;
 121 +               };
 122
 123 -       msmgpio: gpio@800000 {
 124 -               compatible = "qcom,msm-gpio";
 125 -               gpio-controller;
 126 -               #gpio-cells = <2>;
 127 -               ngpio = <150>;
 128 -               interrupts = <0 16 0x4>;
 129 -               interrupt-controller;
 130 -               #interrupt-cells = <2>;
 131 -               reg = <0x800000 0x4000>;
 132 -       };
 133 +               msmgpio: gpio@800000 {
 134 +                       compatible = "qcom,msm-gpio";
 135 +                       gpio-controller;
 136 +                       #gpio-cells = <2>;
 137 +                       ngpio = <150>;
 138 +                       interrupts = <0 16 0x4>;
 139 +                       interrupt-controller;
 140 +                       #interrupt-cells = <2>;
 141 +                       reg = <0x800000 0x4000>;
 142 +               };
 143
 144 -       gcc: clock-controller@900000 {
 145 -               compatible = "qcom,gcc-msm8960";
 146 -               #clock-cells = <1>;
 147 -               #reset-cells = <1>;
 148 -               reg = <0x900000 0x4000>;
 149 -       };
 150 +               gcc: clock-controller@900000 {
 151 +                       compatible = "qcom,gcc-msm8960";
 152 +                       #clock-cells = <1>;
 153 +                       #reset-cells = <1>;
 154 +                       reg = <0x900000 0x4000>;
 155 +               };
 156
 157 -       clock-controller@4000000 {
 158 -               compatible = "qcom,mmcc-msm8960";
 159 -               reg = <0x4000000 0x1000>;
 160 -               #clock-cells = <1>;
 161 -               #reset-cells = <1>;
 162 -       };
 163 +               clock-controller@4000000 {
 164 +                       compatible = "qcom,mmcc-msm8960";
 165 +                       reg = <0x4000000 0x1000>;
 166 +                       #clock-cells = <1>;
 167 +                       #reset-cells = <1>;
 168 +               };
 169
 170 -       acc0: clock-controller@2088000 {
 171 -               compatible = "qcom,kpss-acc-v1";
 172 -               reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 173 -       };
 174 +               acc0: clock-controller@2088000 {
 175 +                       compatible = "qcom,kpss-acc-v1";
 176 +                       reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 177 +               };
 178
 179 -       acc1: clock-controller@2098000 {
 180 -               compatible = "qcom,kpss-acc-v1";
 181 -               reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 182 -       };
 183 +               acc1: clock-controller@2098000 {
 184 +                       compatible = "qcom,kpss-acc-v1";
 185 +                       reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 186 +               };
 187
 188 -       saw0: regulator@2089000 {
 189 -               compatible = "qcom,saw2";
 190 -               reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 191 -               regulator;
 192 -       };
 193 +               saw0: regulator@2089000 {
 194 +                       compatible = "qcom,saw2";
 195 +                       reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 196 +                       regulator;
 197 +               };
 198
 199 -       saw1: regulator@2099000 {
 200 -               compatible = "qcom,saw2";
 201 -               reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 202 -               regulator;
 203 -       };
 204 +               saw1: regulator@2099000 {
 205 +                       compatible = "qcom,saw2";
 206 +                       reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 207 +                       regulator;
 208 +               };
 209
 210 -       serial@16440000 {
 211 -               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 212 -               reg = <0x16440000 0x1000>,
 213 -                     <0x16400000 0x1000>;
 214 -               interrupts = <0 154 0x0>;
 215 -               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 216 -               clock-names = "core", "iface";
 217 -       };
 218 +               gsbi5: gsbi@16400000 {
 219 +                       compatible = "qcom,gsbi-v1.0.0";
 220 +                       reg = <0x16400000 0x100>;
 221 +                       clocks = <&gcc GSBI5_H_CLK>;
 222 +                       clock-names = "iface";
 223 +                       #address-cells = <1>;
 224 +                       #size-cells = <1>;
 225 +                       ranges;
 226 +
 227 +                       serial@16440000 {
 228 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 229 +                               reg = <0x16440000 0x1000>,
 230 +                                     <0x16400000 0x1000>;
 231 +                               interrupts = <0 154 0x0>;
 232 +                               clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 233 +                               clock-names = "core", "iface";
 234 +                               status = "disabled";
 235 +                       };
 236 +               };
 237
 238 -       qcom,ssbi@500000 {
 239 -               compatible = "qcom,ssbi";
 240 -               reg = <0x500000 0x1000>;
 241 -               qcom,controller-type = "pmic-arbiter";
 242 -       };
 243 +               qcom,ssbi@500000 {
 244 +                       compatible = "qcom,ssbi";
 245 +                       reg = <0x500000 0x1000>;
 246 +                       qcom,controller-type = "pmic-arbiter";
 247 +               };
 248
 249 -       rng@1a500000 {
 250 -               compatible = "qcom,prng";
 251 -               reg = <0x1a500000 0x200>;
 252 -               clocks = <&gcc PRNG_CLK>;
 253 -               clock-names = "core";
 254 +               rng@1a500000 {
 255 +                       compatible = "qcom,prng";
 256 +                       reg = <0x1a500000 0x200>;
 257 +                       clocks = <&gcc PRNG_CLK>;
 258 +                       clock-names = "core";
 259 +               };
 260         };
 261  };