target/linux/ipq806x/patches/0091-ARM-dts-qcom-Update-msm8974-apq8074-device-trees.patch

   1 From 63495b04141e60ceb40d4632a41b7cd4a3d23dd2 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Wed, 28 May 2014 12:01:29 -0500
   4 Subject: [PATCH 091/182] ARM: dts: qcom: Update msm8974/apq8074 device trees
   5
   6 * Move SoC peripherals into an SoC container node
   7 * Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
   8 * Move spi pinctrl into board file
   9 * Cleanup cpu node to match binding spec, enable-method and compatible
  10   should be per cpu, not part of the container
  11 * Drop interrupts property from l2-cache node as its not part of the
  12   binding spec
  13 * Move timer node out of SoC container
  14
  15 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  16 ---
  17  arch/arm/boot/dts/qcom-apq8074-dragonboard.dts |   28 +++++++++++++-
  18  arch/arm/boot/dts/qcom-msm8974.dtsi            |   49 +++++++++---------------
  19  2 files changed, 45 insertions(+), 32 deletions(-)
  20
  21 diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
  22 index 92320c4..b4dfb01 100644
  23 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
  24 +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
  25 @@ -4,7 +4,11 @@
  26         model = "Qualcomm APQ8074 Dragonboard";
  27         compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
  28
  29 -       soc: soc {
  30 +       soc {
  31 +               serial@f991e000 {
  32 +                       status = "ok";
  33 +               };
  34 +
  35                 sdhci@f9824900 {
  36                         bus-width = <8>;
  37                         non-removable;
  38 @@ -15,5 +19,27 @@
  39                         cd-gpios = <&msmgpio 62 0x1>;
  40                         bus-width = <4>;
  41                 };
  42 +
  43 +
  44 +               pinctrl@fd510000 {
  45 +                       spi8_default: spi8_default {
  46 +                               mosi {
  47 +                                       pins = "gpio45";
  48 +                                       function = "blsp_spi8";
  49 +                               };
  50 +                               miso {
  51 +                                       pins = "gpio46";
  52 +                                       function = "blsp_spi8";
  53 +                               };
  54 +                               cs {
  55 +                                       pins = "gpio47";
  56 +                                       function = "blsp_spi8";
  57 +                               };
  58 +                               clk {
  59 +                                       pins = "gpio48";
  60 +                                       function = "blsp_spi8";
  61 +                               };
  62 +                       };
  63 +               };
  64         };
  65  };
  66 diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
  67 index c530a33..69dca2a 100644
  68 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
  69 +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
  70 @@ -13,10 +13,10 @@
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73                 interrupts = <1 9 0xf04>;
  74 -               compatible = "qcom,krait";
  75 -               enable-method = "qcom,kpss-acc-v2";
  76
  77                 cpu@0 {
  78 +                       compatible = "qcom,krait";
  79 +                       enable-method = "qcom,kpss-acc-v2";
  80                         device_type = "cpu";
  81                         reg = <0>;
  82                         next-level-cache = <&L2>;
  83 @@ -24,6 +24,8 @@
  84                 };
  85
  86                 cpu@1 {
  87 +                       compatible = "qcom,krait";
  88 +                       enable-method = "qcom,kpss-acc-v2";
  89                         device_type = "cpu";
  90                         reg = <1>;
  91                         next-level-cache = <&L2>;
  92 @@ -31,6 +33,8 @@
  93                 };
  94
  95                 cpu@2 {
  96 +                       compatible = "qcom,krait";
  97 +                       enable-method = "qcom,kpss-acc-v2";
  98                         device_type = "cpu";
  99                         reg = <2>;
 100                         next-level-cache = <&L2>;
 101 @@ -38,6 +42,8 @@
 102                 };
 103
 104                 cpu@3 {
 105 +                       compatible = "qcom,krait";
 106 +                       enable-method = "qcom,kpss-acc-v2";
 107                         device_type = "cpu";
 108                         reg = <3>;
 109                         next-level-cache = <&L2>;
 110 @@ -47,7 +53,6 @@
 111                 L2: l2-cache {
 112                         compatible = "cache";
 113                         cache-level = <2>;
 114 -                       interrupts = <0 2 0x4>;
 115                         qcom,saw = <&saw_l2>;
 116                 };
 117         };
 118 @@ -57,6 +62,15 @@
 119                 interrupts = <1 7 0xf04>;
 120         };
 121
 122 +       timer {
 123 +               compatible = "arm,armv7-timer";
 124 +               interrupts = <1 2 0xf08>,
 125 +                            <1 3 0xf08>,
 126 +                            <1 4 0xf08>,
 127 +                            <1 1 0xf08>;
 128 +               clock-frequency = <19200000>;
 129 +       };
 130 +
 131         soc: soc {
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134 @@ -71,15 +85,6 @@
 135                               <0xf9002000 0x1000>;
 136                 };
 137
 138 -               timer {
 139 -                       compatible = "arm,armv7-timer";
 140 -                       interrupts = <1 2 0xf08>,
 141 -                                    <1 3 0xf08>,
 142 -                                    <1 4 0xf08>,
 143 -                                    <1 1 0xf08>;
 144 -                       clock-frequency = <19200000>;
 145 -               };
 146 -
 147                 timer@f9020000 {
 148                         #address-cells = <1>;
 149                         #size-cells = <1>;
 150 @@ -190,6 +195,7 @@
 151                         interrupts = <0 108 0x0>;
 152                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 153                         clock-names = "core", "iface";
 154 +                       status = "disabled";
 155                 };
 156
 157                 sdhci@f9824900 {
 158 @@ -229,25 +235,6 @@
 159                         interrupt-controller;
 160                         #interrupt-cells = <2>;
 161                         interrupts = <0 208 0>;
 162 -
 163 -                       spi8_default: spi8_default {
 164 -                               mosi {
 165 -                                       pins = "gpio45";
 166 -                                       function = "blsp_spi8";
 167 -                               };
 168 -                               miso {
 169 -                                       pins = "gpio46";
 170 -                                       function = "blsp_spi8";
 171 -                               };
 172 -                               cs {
 173 -                                       pins = "gpio47";
 174 -                                       function = "blsp_spi8";
 175 -                               };
 176 -                               clk {
 177 -                                       pins = "gpio48";
 178 -                                       function = "blsp_spi8";
 179 -                               };
 180 -                       };
 181                 };
 182         };
 183  };
 184 --
 185 1.7.10.4
 186