target/linux/ipq806x/patches/001-spi-qup-Add-DMA-capabilities.patch

   1 Content-Type: text/plain; charset="utf-8"
   2 MIME-Version: 1.0
   3 Content-Transfer-Encoding: 7bit
   4 Subject: spi: qup: Add DMA capabilities
   5 From: Andy Gross <agross@codeaurora.org>
   6 X-Patchwork-Id: 4432401
   7 Message-Id: <1403816781-31008-1-git-send-email-agross@codeaurora.org>
   8 To: Mark Brown <broonie@kernel.org>
   9 Cc: linux-spi@vger.kernel.org, Sagar Dharia <sdharia@codeaurora.org>,
  10         Daniel Sneddon <dsneddon@codeaurora.org>,
  11         Bjorn Andersson <bjorn.andersson@sonymobile.com>,
  12         "Ivan T. Ivanov" <iivanov@mm-sol.com>,
  13         linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
  14         linux-arm-msm@vger.kernel.org, Andy Gross <agross@codeaurora.org>
  15 Date: Thu, 26 Jun 2014 16:06:21 -0500
  16
  17 This patch adds DMA capabilities to the spi-qup driver.  If DMA channels are
  18 present, the QUP will use DMA instead of block mode for transfers to/from SPI
  19 peripherals for transactions larger than the length of a block.
  20
  21 Signed-off-by: Andy Gross <agross@codeaurora.org>
  22
  23 ---
  24 .../devicetree/bindings/spi/qcom,spi-qup.txt       |   10 +
  25  drivers/spi/spi-qup.c                              |  361 ++++++++++++++++++--
  26  2 files changed, 350 insertions(+), 21 deletions(-)
  27
  28 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  29 +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  30 @@ -27,6 +27,11 @@ Optional properties:
  31  - spi-max-frequency: Specifies maximum SPI clock frequency,
  32                       Units - Hz. Definition as per
  33                       Documentation/devicetree/bindings/spi/spi-bus.txt
  34 +- dmas :             Two DMA channel specifiers following the convention outlined
  35 +                     in bindings/dma/dma.txt
  36 +- dma-names:         Names for the dma channels, if present. There must be at
  37 +                     least one channel named "tx" for transmit and named "rx" for
  38 +                     receive.
  39  - num-cs:      total number of chipselects
  40  - cs-gpios:    should specify GPIOs used for chipselects.
  41                 The gpios will be referred to as reg = <index> in the SPI child
  42 @@ -51,6 +56,10 @@ Example:
  43                 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  44                 clock-names = "core", "iface";
  45
  46 +               dmas = <&blsp2_bam 2>,
  47 +                       <&blsp2_bam 3>;
  48 +               dma-names = "rx", "tx";
  49 +
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&spi8_default>;
  52
  53 --- a/drivers/spi/spi-qup.c
  54 +++ b/drivers/spi/spi-qup.c
  55 @@ -22,6 +22,8 @@
  56  #include <linux/platform_device.h>
  57  #include <linux/pm_runtime.h>
  58  #include <linux/spi/spi.h>
  59 +#include <linux/dmaengine.h>
  60 +#include <linux/dma-mapping.h>
  61
  62  #define QUP_CONFIG                     0x0000
  63  #define QUP_STATE                      0x0004
  64 @@ -116,6 +118,8 @@
  65
  66  #define SPI_NUM_CHIPSELECTS            4
  67
  68 +#define SPI_MAX_XFER                   (SZ_64K - 64)
  69 +
  70  /* high speed mode is when bus rate is greater then 26MHz */
  71  #define SPI_HS_MIN_RATE                        26000000
  72  #define SPI_MAX_RATE                   50000000
  73 @@ -143,6 +147,17 @@ struct spi_qup {
  74         int                     tx_bytes;
  75         int                     rx_bytes;
  76         int                     qup_v1;
  77 +
  78 +       int                     use_dma;
  79 +
  80 +       struct dma_chan         *rx_chan;
  81 +       struct dma_slave_config rx_conf;
  82 +       struct dma_chan         *tx_chan;
  83 +       struct dma_slave_config tx_conf;
  84 +       dma_addr_t              rx_dma;
  85 +       dma_addr_t              tx_dma;
  86 +       void                    *dummy;
  87 +       atomic_t                dma_outstanding;
  88  };
  89
  90
  91 @@ -266,6 +281,221 @@ static void spi_qup_fifo_write(struct sp
  92         }
  93  }
  94
  95 +static void qup_dma_callback(void *data)
  96 +{
  97 +       struct spi_qup *controller = data;
  98 +
  99 +       if (atomic_dec_and_test(&controller->dma_outstanding))
 100 +               complete(&controller->done);
 101 +}
 102 +
 103 +static int spi_qup_do_dma(struct spi_qup *controller, struct spi_transfer *xfer)
 104 +{
 105 +       struct dma_async_tx_descriptor *rxd, *txd;
 106 +       dma_cookie_t rx_cookie, tx_cookie;
 107 +       u32 xfer_len, rx_align = 0, tx_align = 0, n_words;
 108 +       struct scatterlist tx_sg[2], rx_sg[2];
 109 +       int ret = 0;
 110 +       u32 bytes_to_xfer = xfer->len;
 111 +       u32 offset = 0;
 112 +       u32 rx_nents = 0, tx_nents = 0;
 113 +       dma_addr_t rx_dma = 0, tx_dma = 0, rx_dummy_dma = 0, tx_dummy_dma = 0;
 114 +
 115 +
 116 +       if (xfer->rx_buf) {
 117 +               rx_dma = dma_map_single(controller->dev, xfer->rx_buf,
 118 +                       xfer->len, DMA_FROM_DEVICE);
 119 +
 120 +               if (dma_mapping_error(controller->dev, rx_dma)) {
 121 +                       ret = -ENOMEM;
 122 +                       return ret;
 123 +               }
 124 +
 125 +               /* check to see if we need dummy buffer for leftover bytes */
 126 +               rx_align = xfer->len % controller->in_blk_sz;
 127 +               if (rx_align) {
 128 +                       rx_dummy_dma = dma_map_single(controller->dev,
 129 +                               controller->dummy, controller->in_fifo_sz,
 130 +                               DMA_FROM_DEVICE);
 131 +
 132 +                       if (dma_mapping_error(controller->dev, rx_dummy_dma)) {
 133 +                               ret = -ENOMEM;
 134 +                               goto err_map_rx_dummy;
 135 +                       }
 136 +               }
 137 +       }
 138 +
 139 +       if (xfer->tx_buf) {
 140 +               tx_dma = dma_map_single(controller->dev,
 141 +                       (void *)xfer->tx_buf, xfer->len, DMA_TO_DEVICE);
 142 +
 143 +               if (dma_mapping_error(controller->dev, tx_dma)) {
 144 +                       ret = -ENOMEM;
 145 +                       goto err_map_tx;
 146 +               }
 147 +
 148 +               /* check to see if we need dummy buffer for leftover bytes */
 149 +               tx_align = xfer->len % controller->out_blk_sz;
 150 +               if (tx_align) {
 151 +                       memcpy(controller->dummy + SZ_1K,
 152 +                               xfer->tx_buf + xfer->len - tx_align,
 153 +                               tx_align);
 154 +                       memset(controller->dummy + SZ_1K + tx_align, 0,
 155 +                               controller->out_blk_sz - tx_align);
 156 +
 157 +                       tx_dummy_dma = dma_map_single(controller->dev,
 158 +                               controller->dummy + SZ_1K,
 159 +                               controller->out_blk_sz, DMA_TO_DEVICE);
 160 +
 161 +                       if (dma_mapping_error(controller->dev, tx_dummy_dma)) {
 162 +                               ret = -ENOMEM;
 163 +                               goto err_map_tx_dummy;
 164 +                       }
 165 +               }
 166 +       }
 167 +
 168 +       atomic_set(&controller->dma_outstanding, 0);
 169 +
 170 +       while (bytes_to_xfer > 0) {
 171 +               xfer_len = min_t(u32, bytes_to_xfer, SPI_MAX_XFER);
 172 +               n_words = DIV_ROUND_UP(xfer_len, controller->w_size);
 173 +
 174 +               /* write out current word count to controller */
 175 +               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 176 +               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 177 +
 178 +               reinit_completion(&controller->done);
 179 +
 180 +               if (xfer->tx_buf) {
 181 +                       /* recalc align for each transaction */
 182 +                       tx_align = xfer_len % controller->out_blk_sz;
 183 +
 184 +                       if (tx_align)
 185 +                               tx_nents = 2;
 186 +                       else
 187 +                               tx_nents = 1;
 188 +
 189 +                       /* initialize scatterlists */
 190 +                       sg_init_table(tx_sg, tx_nents);
 191 +                       sg_dma_len(&tx_sg[0]) = xfer_len - tx_align;
 192 +                       sg_dma_address(&tx_sg[0]) = tx_dma + offset;
 193 +
 194 +                       /* account for non block size transfer */
 195 +                       if (tx_align) {
 196 +                               sg_dma_len(&tx_sg[1]) = controller->out_blk_sz;
 197 +                               sg_dma_address(&tx_sg[1]) = tx_dummy_dma;
 198 +                       }
 199 +
 200 +                       txd = dmaengine_prep_slave_sg(controller->tx_chan,
 201 +                                       tx_sg, tx_nents, DMA_MEM_TO_DEV, 0);
 202 +                       if (!txd) {
 203 +                               ret = -ENOMEM;
 204 +                               goto err_unmap;
 205 +                       }
 206 +
 207 +                       atomic_inc(&controller->dma_outstanding);
 208 +
 209 +                       txd->callback = qup_dma_callback;
 210 +                       txd->callback_param = controller;
 211 +
 212 +                       tx_cookie = dmaengine_submit(txd);
 213 +
 214 +                       dma_async_issue_pending(controller->tx_chan);
 215 +               }
 216 +
 217 +               if (xfer->rx_buf) {
 218 +                       /* recalc align for each transaction */
 219 +                       rx_align = xfer_len % controller->in_blk_sz;
 220 +
 221 +                       if (rx_align)
 222 +                               rx_nents = 2;
 223 +                       else
 224 +                               rx_nents = 1;
 225 +
 226 +                       /* initialize scatterlists */
 227 +                       sg_init_table(rx_sg, rx_nents);
 228 +                       sg_dma_address(&rx_sg[0]) = rx_dma + offset;
 229 +                       sg_dma_len(&rx_sg[0]) = xfer_len - rx_align;
 230 +
 231 +                       /* account for non block size transfer */
 232 +                       if (rx_align) {
 233 +                               sg_dma_len(&rx_sg[1]) = controller->in_blk_sz;
 234 +                               sg_dma_address(&rx_sg[1]) = rx_dummy_dma;
 235 +                       }
 236 +
 237 +                       rxd = dmaengine_prep_slave_sg(controller->rx_chan,
 238 +                                       rx_sg, rx_nents, DMA_DEV_TO_MEM, 0);
 239 +                       if (!rxd) {
 240 +                               ret = -ENOMEM;
 241 +                               goto err_unmap;
 242 +                       }
 243 +
 244 +                       atomic_inc(&controller->dma_outstanding);
 245 +
 246 +                       rxd->callback = qup_dma_callback;
 247 +                       rxd->callback_param = controller;
 248 +
 249 +                       rx_cookie = dmaengine_submit(rxd);
 250 +
 251 +                       dma_async_issue_pending(controller->rx_chan);
 252 +               }
 253 +
 254 +               if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 255 +                       dev_warn(controller->dev, "cannot set EXECUTE state\n");
 256 +                       goto err_unmap;
 257 +               }
 258 +
 259 +               if (!wait_for_completion_timeout(&controller->done,
 260 +                       msecs_to_jiffies(1000))) {
 261 +                       ret = -ETIMEDOUT;
 262 +
 263 +                       /* clear out all the DMA transactions */
 264 +                       if (xfer->tx_buf)
 265 +                               dmaengine_terminate_all(controller->tx_chan);
 266 +                       if (xfer->rx_buf)
 267 +                               dmaengine_terminate_all(controller->rx_chan);
 268 +
 269 +                       goto err_unmap;
 270 +               }
 271 +
 272 +               if (rx_align)
 273 +                       memcpy(xfer->rx_buf + offset + xfer->len - rx_align,
 274 +                               controller->dummy, rx_align);
 275 +
 276 +               /* adjust remaining bytes to transfer */
 277 +               bytes_to_xfer -= xfer_len;
 278 +               offset += xfer_len;
 279 +
 280 +
 281 +               /* reset mini-core state so we can program next transaction */
 282 +               if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
 283 +                       dev_err(controller->dev, "cannot set RESET state\n");
 284 +                       goto err_unmap;
 285 +               }
 286 +       }
 287 +
 288 +       ret = 0;
 289 +
 290 +err_unmap:
 291 +       if (tx_align)
 292 +               dma_unmap_single(controller->dev, tx_dummy_dma,
 293 +                       controller->out_fifo_sz, DMA_TO_DEVICE);
 294 +err_map_tx_dummy:
 295 +       if (xfer->tx_buf)
 296 +               dma_unmap_single(controller->dev, tx_dma, xfer->len,
 297 +                       DMA_TO_DEVICE);
 298 +err_map_tx:
 299 +       if (rx_align)
 300 +               dma_unmap_single(controller->dev, rx_dummy_dma,
 301 +                       controller->in_fifo_sz, DMA_FROM_DEVICE);
 302 +err_map_rx_dummy:
 303 +       if (xfer->rx_buf)
 304 +               dma_unmap_single(controller->dev, rx_dma, xfer->len,
 305 +                       DMA_FROM_DEVICE);
 306 +
 307 +       return ret;
 308 +}
 309 +
 310  static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
 311  {
 312         struct spi_qup *controller = dev_id;
 313 @@ -315,11 +545,13 @@ static irqreturn_t spi_qup_qup_irq(int i
 314                 error = -EIO;
 315         }
 316
 317 -       if (opflags & QUP_OP_IN_SERVICE_FLAG)
 318 -               spi_qup_fifo_read(controller, xfer);
 319 +       if (!controller->use_dma) {
 320 +               if (opflags & QUP_OP_IN_SERVICE_FLAG)
 321 +                       spi_qup_fifo_read(controller, xfer);
 322
 323 -       if (opflags & QUP_OP_OUT_SERVICE_FLAG)
 324 -               spi_qup_fifo_write(controller, xfer);
 325 +               if (opflags & QUP_OP_OUT_SERVICE_FLAG)
 326 +                       spi_qup_fifo_write(controller, xfer);
 327 +       }
 328
 329         spin_lock_irqsave(&controller->lock, flags);
 330         controller->error = error;
 331 @@ -339,6 +571,8 @@ static int spi_qup_io_config(struct spi_
 332         struct spi_qup *controller = spi_master_get_devdata(spi->master);
 333         u32 config, iomode, mode;
 334         int ret, n_words, w_size;
 335 +       size_t dma_align = dma_get_cache_alignment();
 336 +       u32 dma_available = 0;
 337
 338         if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
 339                 dev_err(controller->dev, "too big size for loopback %d > %d\n",
 340 @@ -367,6 +601,11 @@ static int spi_qup_io_config(struct spi_
 341         n_words = xfer->len / w_size;
 342         controller->w_size = w_size;
 343
 344 +       if (controller->rx_chan &&
 345 +               IS_ALIGNED((size_t)xfer->tx_buf, dma_align) &&
 346 +               IS_ALIGNED((size_t)xfer->rx_buf, dma_align))
 347 +               dma_available = 1;
 348 +
 349         if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
 350                 mode = QUP_IO_M_MODE_FIFO;
 351                 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
 352 @@ -374,19 +613,31 @@ static int spi_qup_io_config(struct spi_
 353                 /* must be zero for FIFO */
 354                 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 355                 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 356 -       } else {
 357 +               controller->use_dma = 0;
 358 +       } else if (!dma_available) {
 359                 mode = QUP_IO_M_MODE_BLOCK;
 360                 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 361                 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 362                 /* must be zero for BLOCK and BAM */
 363                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 364                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 365 +               controller->use_dma = 0;
 366 +       } else {
 367 +               mode = QUP_IO_M_MODE_DMOV;
 368 +               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 369 +               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 370 +               controller->use_dma = 1;
 371         }
 372
 373         iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 374         /* Set input and output transfer mode */
 375         iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
 376 -       iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 377 +
 378 +       if (!controller->use_dma)
 379 +               iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 380 +       else
 381 +               iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
 382 +
 383         iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 384         iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 385
 386 @@ -419,6 +670,14 @@ static int spi_qup_io_config(struct spi_
 387         config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
 388         config |= xfer->bits_per_word - 1;
 389         config |= QUP_CONFIG_SPI_MODE;
 390 +
 391 +       if (controller->use_dma) {
 392 +               if (!xfer->tx_buf)
 393 +                       config |= QUP_CONFIG_NO_OUTPUT;
 394 +               if (!xfer->rx_buf)
 395 +                       config |= QUP_CONFIG_NO_INPUT;
 396 +       }
 397 +
 398         writel_relaxed(config, controller->base + QUP_CONFIG);
 399
 400         /* only write to OPERATIONAL_MASK when register is present */
 401 @@ -452,25 +711,29 @@ static int spi_qup_transfer_one(struct s
 402         controller->tx_bytes = 0;
 403         spin_unlock_irqrestore(&controller->lock, flags);
 404
 405 -       if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 406 -               dev_warn(controller->dev, "cannot set RUN state\n");
 407 -               goto exit;
 408 -       }
 409 +       if (controller->use_dma) {
 410 +               ret = spi_qup_do_dma(controller, xfer);
 411 +       } else {
 412 +               if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 413 +                       dev_warn(controller->dev, "cannot set RUN state\n");
 414 +                       goto exit;
 415 +               }
 416
 417 -       if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
 418 -               dev_warn(controller->dev, "cannot set PAUSE state\n");
 419 -               goto exit;
 420 -       }
 421 +               if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
 422 +                       dev_warn(controller->dev, "cannot set PAUSE state\n");
 423 +                       goto exit;
 424 +               }
 425
 426 -       spi_qup_fifo_write(controller, xfer);
 427 +               spi_qup_fifo_write(controller, xfer);
 428
 429 -       if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 430 -               dev_warn(controller->dev, "cannot set EXECUTE state\n");
 431 -               goto exit;
 432 -       }
 433 +               if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 434 +                       dev_warn(controller->dev, "cannot set EXECUTE state\n");
 435 +                       goto exit;
 436 +               }
 437
 438 -       if (!wait_for_completion_timeout(&controller->done, timeout))
 439 -               ret = -ETIMEDOUT;
 440 +               if (!wait_for_completion_timeout(&controller->done, timeout))
 441 +                       ret = -ETIMEDOUT;
 442 +       }
 443  exit:
 444         spi_qup_set_state(controller, QUP_STATE_RESET);
 445         spin_lock_irqsave(&controller->lock, flags);
 446 @@ -553,6 +816,7 @@ static int spi_qup_probe(struct platform
 447         master->transfer_one = spi_qup_transfer_one;
 448         master->dev.of_node = pdev->dev.of_node;
 449         master->auto_runtime_pm = true;
 450 +       master->dma_alignment = dma_get_cache_alignment();
 451
 452         platform_set_drvdata(pdev, master);
 453
 454 @@ -618,6 +882,56 @@ static int spi_qup_probe(struct platform
 455                         QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
 456                         base + QUP_ERROR_FLAGS_EN);
 457
 458 +       /* allocate dma resources, if available */
 459 +       controller->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
 460 +       if (controller->rx_chan) {
 461 +               controller->tx_chan =
 462 +                       dma_request_slave_channel(&pdev->dev, "tx");
 463 +
 464 +               if (!controller->tx_chan) {
 465 +                       dev_err(&pdev->dev, "Failed to allocate dma tx chan");
 466 +                       dma_release_channel(controller->rx_chan);
 467 +               }
 468 +
 469 +               /* set DMA parameters */
 470 +               controller->rx_conf.device_fc = 1;
 471 +               controller->rx_conf.src_addr = res->start + QUP_INPUT_FIFO;
 472 +               controller->rx_conf.src_maxburst = controller->in_blk_sz;
 473 +
 474 +               controller->tx_conf.device_fc = 1;
 475 +               controller->tx_conf.dst_addr = res->start + QUP_OUTPUT_FIFO;
 476 +               controller->tx_conf.dst_maxburst = controller->out_blk_sz;
 477 +
 478 +               if (dmaengine_slave_config(controller->rx_chan,
 479 +                               &controller->rx_conf)) {
 480 +                       dev_err(&pdev->dev, "failed to configure RX channel\n");
 481 +
 482 +                       dma_release_channel(controller->rx_chan);
 483 +                       dma_release_channel(controller->tx_chan);
 484 +                       controller->tx_chan = NULL;
 485 +                       controller->rx_chan = NULL;
 486 +               } else if (dmaengine_slave_config(controller->tx_chan,
 487 +                               &controller->tx_conf)) {
 488 +                       dev_err(&pdev->dev, "failed to configure TX channel\n");
 489 +
 490 +                       dma_release_channel(controller->rx_chan);
 491 +                       dma_release_channel(controller->tx_chan);
 492 +                       controller->tx_chan = NULL;
 493 +                       controller->rx_chan = NULL;
 494 +               }
 495 +
 496 +               controller->dummy = devm_kmalloc(controller->dev, PAGE_SIZE,
 497 +                       GFP_KERNEL);
 498 +
 499 +               if (!controller->dummy) {
 500 +                       dma_release_channel(controller->rx_chan);
 501 +                       dma_release_channel(controller->tx_chan);
 502 +                       controller->tx_chan = NULL;
 503 +                       controller->rx_chan = NULL;
 504 +               }
 505 +       }
 506 +
 507 +
 508         writel_relaxed(0, base + SPI_CONFIG);
 509         writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
 510
 511 @@ -730,6 +1044,11 @@ static int spi_qup_remove(struct platfor
 512         if (ret)
 513                 return ret;
 514
 515 +       if (controller->rx_chan)
 516 +               dma_release_channel(controller->rx_chan);
 517 +       if (controller->tx_chan)
 518 +               dma_release_channel(controller->tx_chan);
 519 +
 520         clk_disable_unprepare(controller->cclk);
 521         clk_disable_unprepare(controller->iclk);
 522